Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T17

10

T75

7

T76

8

auto[1]

984

1

T17

10

T75

13

T76

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T17

5

T75

4

T76

5

from_0to1

496

1

T17

5

T75

5

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

991

1

T17

12

T75

6

T76

9

auto[1]

965

1

T17

8

T75

14

T76

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

963

1

T17

11

T75

8

T76

10

auto[1]

993

1

T17

9

T75

12

T76

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T17

1

T76

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T79

2

T144

2

T294

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T17

1

T75

1

T144

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T75

1

T144

1

T37

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T17

1

T75

2

T76

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T17

1

T144

1

T105

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T75

1

T144

1

T294

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T76

1

T79

1

T144

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T17

1

T76

2

T37

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T17

1

T75

1

T76

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T17

1

T79

1

T144

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T75

1

T76

1

T294

4

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T79

1

T144

3

T294

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T76

1

T79

1

T144

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T17

2

T75

1

T76

2

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T17

1

T75

1

T294

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

970

1

T17

9

T75

6

T76

9

auto[1]

986

1

T17

11

T75

14

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

461

1

T17

2

T75

6

T76

5

from_0to1

460

1

T17

3

T75

5

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

944

1

T17

9

T75

8

T76

8

auto[1]

1012

1

T17

11

T75

12

T76

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

930

1

T17

11

T75

8

T76

7

auto[1]

1026

1

T17

9

T75

12

T76

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T17

1

T79

1

T294

3

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T144

2

T294

1

T37

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T75

2

T76

1

T79

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T76

1

T144

1

T37

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T17

1

T79

1

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T79

1

T294

1

T37

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T75

1

T79

1

T144

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T76

1

T294

1

T37

2

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T76

1

T144

1

T37

2

auto[1]

from_1to0

auto[0]

auto[1]

51

1

T17

1

T75

2

T76

2

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T75

1

T79

2

T105

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T75

1

T37

2

T34

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T294

2

T37

2

T180

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T76

2

T79

1

T144

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T17

1

T75

1

T76

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T17

1

T75

3

T76

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T17

6

T75

10

T76

10

auto[1]

975

1

T17

14

T75

10

T76

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

444

1

T17

4

T75

5

T76

5

from_0to1

457

1

T17

4

T75

6

T76

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T17

9

T75

6

T76

12

auto[1]

995

1

T17

11

T75

14

T76

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

942

1

T17

8

T75

9

T76

10

auto[1]

1014

1

T17

12

T75

11

T76

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T37

2

T180

2

T34

2

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T76

1

T37

2

T34

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T75

1

T76

1

T144

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T17

1

T79

2

T37

2

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T37

2

T105

3

T146

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T17

1

T75

1

T79

2

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T17

1

T75

1

T76

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T75

1

T76

1

T294

2

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T17

3

T75

2

T76

2

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T37

1

T105

3

T382

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T76

1

T294

2

T37

1

auto[1]

from_1to0

auto[1]

auto[1]

53

1

T75

2

T294

1

T37

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T17

1

T76

2

T144

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T75

1

T76

1

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T75

1

T294

2

T37

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T17

1

T75

1

T76

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T17

8

T75

6

T76

8

auto[1]

968

1

T17

12

T75

14

T76

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

462

1

T17

3

T75

3

T76

7

from_0to1

463

1

T17

3

T75

3

T76

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

943

1

T17

10

T75

5

T76

13

auto[1]

1013

1

T17

10

T75

15

T76

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1033

1

T17

6

T75

9

T76

11

auto[1]

923

1

T17

14

T75

11

T76

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T37

2

T34

2

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T76

1

T144

2

T37

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T75

1

T76

1

T79

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T76

1

T294

1

T37

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T76

1

T144

1

T294

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T17

1

T76

2

T79

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T294

1

T37

2

T180

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T144

1

T180

2

T105

5

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T76

2

T144

1

T37

2

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T79

1

T144

1

T294

3

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T17

1

T75

1

T76

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T17

2

T75

1

T76

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T76

2

T79

1

T37

2

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T17

1

T75

1

T79

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T17

1

T76

1

T79

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T75

2

T76

1

T144

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T17

11

T75

8

T76

11

auto[1]

954

1

T17

9

T75

12

T76

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

465

1

T17

5

T75

7

T76

5

from_0to1

463

1

T17

4

T75

8

T76

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T17

10

T75

10

T76

10

auto[1]

957

1

T17

10

T75

10

T76

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009

1

T17

11

T75

6

T76

9

auto[1]

947

1

T17

9

T75

14

T76

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T17

1

T75

2

T144

2

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T17

1

T75

1

T76

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T75

1

T79

1

T144

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T17

1

T75

1

T76

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T17

1

T76

1

T144

2

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T294

1

T37

2

T180

1

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T76

1

T144

1

T294

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T75

2

T76

1

T294

2

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T75

1

T294

1

T37

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T17

1

T37

2

T180

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T17

1

T75

1

T76

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T76

1

T79

3

T144

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T17

1

T75

1

T79

2

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T75

3

T76

1

T79

2

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T17

1

T37

1

T38

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T17

1

T75

2

T76

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T17

9

T75

13

T76

9

auto[1]

998

1

T17

11

T75

7

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

455

1

T17

5

T75

6

T76

4

from_0to1

465

1

T17

5

T75

5

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T17

9

T75

9

T76

11

auto[1]

956

1

T17

11

T75

11

T76

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T17

10

T75

8

T76

7

auto[1]

926

1

T17

10

T75

12

T76

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T17

2

T76

1

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T75

1

T144

2

T294

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T79

2

T144

2

T37

2

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T17

1

T75

4

T294

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T75

1

T294

1

T37

2

auto[0]

from_0to1

auto[0]

auto[1]

48

1

T75

1

T76

1

T79

2

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T75

1

T79

1

T294

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T17

2

T79

1

T37

3

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T17

1

T75

1

T37

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T76

1

T79

1

T37

4

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T76

2

T294

1

T37

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T17

1

T79

2

T294

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T75

2

T79

1

T37

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T76

1

T144

1

T294

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T17

2

T76

1

T79

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T17

1

T76

1

T144

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T17

11

T75

8

T76

9

auto[1]

995

1

T17

9

T75

12

T76

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

459

1

T17

7

T75

4

T76

2

from_0to1

470

1

T17

7

T75

5

T76

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T17

9

T75

10

T76

8

auto[1]

998

1

T17

11

T75

10

T76

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T17

6

T75

12

T76

9

auto[1]

995

1

T17

14

T75

8

T76

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T17

1

T75

2

T79

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T17

2

T144

1

T37

2

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T144

1

T37

4

T180

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T17

2

T37

1

T180

1

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T17

1

T144

1

T37

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T75

1

T79

1

T37

2

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T75

2

T79

1

T294

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T17

1

T76

1

T79

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T76

1

T79

2

T144

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T75

1

T79

2

T294

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T17

2

T75

1

T76

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T144

1

T294

2

T34

2

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T17

1

T37

1

T34

2

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T17

2

T75

1

T76

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T17

1

T79

2

T294

2

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T17

1

T75

1

T76

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

972

1

T17

9

T75

9

T76

10

auto[1]

984

1

T17

11

T75

11

T76

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

477

1

T17

5

T75

5

T76

5

from_0to1

473

1

T17

5

T75

5

T76

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

985

1

T17

11

T75

11

T76

12

auto[1]

971

1

T17

9

T75

9

T76

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

981

1

T17

10

T75

14

T76

8

auto[1]

975

1

T17

10

T75

6

T76

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T76

1

T79

1

T144

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T75

1

T76

1

T79

2

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T17

1

T75

1

T34

3

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T17

1

T144

1

T34

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T17

1

T75

1

T144

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T17

2

T79

2

T294

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T75

1

T144

1

T294

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T76

1

T294

1

T37

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T17

1

T75

1

T76

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T75

1

T76

1

T79

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T294

1

T37

1

T105

2

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T17

2

T75

1

T76

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T17

1

T75

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T76

1

T180

2

T105

4

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T17

1

T75

2

T76

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T76

1

T144

1

T294

2