Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150527	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117631

1

T1

266

T4

103

T5

267

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	135953	1			T1	404		T4	3		T5	390
values[0x0]	65602	1			T1	70		T4	210		T5	68
values[0x1]	66603	1			T1	71		T4	214		T5	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121954	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

146204

1

T1

319

T4

137

T5

319

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1069	1			T4	2		T2	1		T17	1
valid_sources[0x01]	985	1			T1	1		T5	2		T27	3
valid_sources[0x02]	913	1			T4	2		T13	9		T2	4
valid_sources[0x03]	914	1			T13	2		T2	3		T27	1
valid_sources[0x04]	1984	1			T1	3		T13	1		T27	2
valid_sources[0x05]	1059	1			T1	2		T13	2		T17	1
valid_sources[0x06]	983	1			T13	2		T17	1		T27	4
valid_sources[0x07]	964	1			T2	13		T17	1		T27	2
valid_sources[0x08]	907	1			T4	5		T48	2		T25	1
valid_sources[0x09]	931	1			T4	3		T5	2		T13	4
valid_sources[0x0a]	889	1			T1	3		T4	3		T5	11
valid_sources[0x0b]	967	1			T1	7		T4	3		T5	3
valid_sources[0x0c]	1606	1			T1	3		T4	1		T2	6
valid_sources[0x0d]	837	1			T4	3		T13	1		T2	17
valid_sources[0x0e]	962	1			T4	2		T5	1		T3	5
valid_sources[0x0f]	1074	1			T4	4		T5	1		T27	4
valid_sources[0x10]	850	1			T1	3		T13	1		T27	2
valid_sources[0x11]	1243	1			T4	5		T5	9		T2	4
valid_sources[0x12]	2075	1			T1	4		T4	2		T5	7
valid_sources[0x13]	876	1			T4	2		T27	10		T48	3
valid_sources[0x14]	1047	1			T4	1		T17	1		T27	3
valid_sources[0x15]	905	1			T1	20		T13	3		T27	2
valid_sources[0x16]	971	1			T4	2		T5	4		T13	6
valid_sources[0x17]	1018	1			T4	4		T2	8		T27	13
valid_sources[0x18]	975	1			T5	7		T2	7		T17	1
valid_sources[0x19]	897	1			T1	2		T4	5		T5	1
valid_sources[0x1a]	921	1			T4	3		T5	7		T13	1
valid_sources[0x1b]	1096	1			T4	2		T13	2		T27	11
valid_sources[0x1c]	926	1			T5	1		T13	1		T17	2
valid_sources[0x1d]	992	1			T13	3		T17	1		T27	3
valid_sources[0x1e]	882	1			T13	4		T48	3		T9	4
valid_sources[0x1f]	801	1			T4	2		T5	6		T13	1
valid_sources[0x20]	775	1			T13	3		T2	2		T48	4
valid_sources[0x21]	1134	1			T4	2		T13	4		T17	1
valid_sources[0x22]	979	1			T4	6		T27	5		T48	4
valid_sources[0x23]	795	1			T27	2		T48	7		T25	3
valid_sources[0x24]	1009	1			T4	3		T5	6		T13	2
valid_sources[0x25]	904	1			T4	1		T5	8		T2	8
valid_sources[0x26]	955	1			T1	5		T4	2		T5	1
valid_sources[0x27]	838	1			T4	1		T5	2		T13	4
valid_sources[0x28]	862	1			T4	2		T5	6		T2	4
valid_sources[0x29]	1502	1			T1	1		T4	1		T27	1
valid_sources[0x2a]	962	1			T4	3		T13	1		T27	5
valid_sources[0x2b]	1451	1			T1	9		T4	1		T13	3
valid_sources[0x2c]	1446	1			T4	2		T13	1		T2	20
valid_sources[0x2d]	1075	1			T4	3		T5	7		T2	4
valid_sources[0x2e]	987	1			T4	2		T5	6		T2	2
valid_sources[0x2f]	1648	1			T4	2		T5	3		T13	4
valid_sources[0x30]	1525	1			T5	3		T13	2		T2	8
valid_sources[0x31]	808	1			T13	2		T17	1		T27	1
valid_sources[0x32]	1514	1			T4	1		T13	3		T27	8
valid_sources[0x33]	965	1			T1	10		T4	2		T13	1
valid_sources[0x34]	912	1			T5	1		T2	12		T27	2
valid_sources[0x35]	975	1			T1	6		T4	2		T2	9
valid_sources[0x36]	820	1			T4	1		T13	2		T2	3
valid_sources[0x37]	2161	1			T4	3		T27	5		T48	3
valid_sources[0x38]	1047	1			T13	6		T6	1		T9	1
valid_sources[0x39]	1013	1			T13	9		T17	1		T27	4
valid_sources[0x3a]	1338	1			T1	20		T4	1		T13	2
valid_sources[0x3b]	830	1			T4	1		T2	8		T17	1
valid_sources[0x3c]	1051	1			T4	4		T5	1		T2	20
valid_sources[0x3d]	1175	1			T4	1		T5	7		T22	2
valid_sources[0x3e]	879	1			T1	2		T4	2		T13	3
valid_sources[0x3f]	1039	1			T5	5		T2	2		T17	2
valid_sources[0x40]	1499	1			T4	2		T5	11		T13	1
valid_sources[0x41]	1546	1			T5	1		T2	3		T27	6
valid_sources[0x42]	850	1			T1	4		T4	5		T13	1
valid_sources[0x43]	763	1			T4	5		T13	1		T22	2
valid_sources[0x44]	1372	1			T1	6		T4	1		T5	4
valid_sources[0x45]	904	1			T1	2		T4	3		T5	12
valid_sources[0x46]	1780	1			T5	1		T13	3		T17	1
valid_sources[0x47]	958	1			T4	1		T27	8		T48	3
valid_sources[0x48]	1564	1			T4	3		T13	3		T2	16
valid_sources[0x49]	1035	1			T4	2		T5	5		T2	4
valid_sources[0x4a]	1108	1			T4	1		T5	15		T17	1
valid_sources[0x4b]	1121	1			T1	1		T4	2		T5	5
valid_sources[0x4c]	830	1			T4	2		T5	1		T13	3
valid_sources[0x4d]	1853	1			T1	1		T4	1		T27	2
valid_sources[0x4e]	968	1			T4	2		T13	1		T17	1
valid_sources[0x4f]	864	1			T4	1		T13	5		T2	1
valid_sources[0x50]	947	1			T1	11		T4	4		T5	2
valid_sources[0x51]	868	1			T1	7		T2	3		T60	1
valid_sources[0x52]	853	1			T4	4		T5	2		T13	11
valid_sources[0x53]	823	1			T1	2		T4	7		T15	2
valid_sources[0x54]	837	1			T4	1		T5	11		T27	2
valid_sources[0x55]	817	1			T5	4		T13	2		T27	2
valid_sources[0x56]	1023	1			T17	1		T27	5		T48	3
valid_sources[0x57]	719	1			T4	1		T5	5		T13	1
valid_sources[0x58]	911	1			T4	1		T27	5		T48	6
valid_sources[0x59]	965	1			T1	1		T4	1		T5	1
valid_sources[0x5a]	877	1			T1	2		T4	2		T5	5
valid_sources[0x5b]	985	1			T4	3		T48	2		T7	4
valid_sources[0x5c]	1221	1			T1	3		T2	1		T17	1
valid_sources[0x5d]	860	1			T1	20		T4	5		T5	1
valid_sources[0x5e]	959	1			T4	3		T5	2		T2	20
valid_sources[0x5f]	884	1			T1	7		T4	1		T27	4
valid_sources[0x60]	1016	1			T4	1		T13	2		T17	1
valid_sources[0x61]	972	1			T1	6		T4	1		T5	3
valid_sources[0x62]	1135	1			T4	3		T5	7		T13	4
valid_sources[0x63]	995	1			T4	4		T5	2		T13	5
valid_sources[0x64]	826	1			T4	3		T5	1		T13	5
valid_sources[0x65]	1686	1			T1	2		T4	1		T13	1
valid_sources[0x66]	866	1			T4	3		T13	4		T17	1
valid_sources[0x67]	929	1			T4	2		T48	1		T9	3
valid_sources[0x68]	819	1			T4	1		T2	9		T17	2
valid_sources[0x69]	847	1			T1	11		T4	3		T13	9
valid_sources[0x6a]	868	1			T4	3		T17	2		T48	4
valid_sources[0x6b]	1024	1			T4	3		T5	1		T13	1
valid_sources[0x6c]	1540	1			T4	1		T27	14		T48	2
valid_sources[0x6d]	912	1			T5	8		T2	11		T27	1
valid_sources[0x6e]	831	1			T1	3		T4	1		T13	2
valid_sources[0x6f]	982	1			T1	1		T13	4		T27	10
valid_sources[0x70]	749	1			T4	1		T48	7		T25	1
valid_sources[0x71]	855	1			T4	2		T5	7		T13	2
valid_sources[0x72]	884	1			T1	1		T4	1		T48	2
valid_sources[0x73]	1051	1			T4	3		T2	1		T27	5
valid_sources[0x74]	916	1			T1	5		T4	1		T5	18
valid_sources[0x75]	1755	1			T4	4		T13	10		T17	2
valid_sources[0x76]	952	1			T1	1		T5	21		T27	1
valid_sources[0x77]	945	1			T1	4		T4	2		T27	5
valid_sources[0x78]	1025	1			T4	2		T5	1		T59	6
valid_sources[0x79]	1100	1			T4	1		T5	1		T27	7
valid_sources[0x7a]	968	1			T4	2		T17	2		T27	7
valid_sources[0x7b]	812	1			T1	11		T17	1		T27	1
valid_sources[0x7c]	895	1			T5	2		T13	1		T17	2
valid_sources[0x7d]	972	1			T4	2		T5	2		T13	6
valid_sources[0x7e]	918	1			T4	1		T5	5		T13	2
valid_sources[0x7f]	862	1			T4	1		T17	1		T27	4
valid_sources[0x80]	955	1			T13	4		T17	1		T27	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62875

1

T1

195

T4

1

T5

202

values[0x0]

all_enables

biggest_size

32239

1

T1

33

T4

62

T5

38

values[0x1]

all_enables

biggest_size

22517

1

T1

38

T4

40

T5

27