Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T15,T26,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T15,T25,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T15,T26,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T25,T26
1	0	Covered	T1,T4,T5
1	1	Covered	T15,T25,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T26,T9
0	1	Covered	T112,T116
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T26,T9
0	1	Covered	T15,T26,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T26,T9
1	-	Covered	T15,T26,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T25,T26
DetectSt	168	Covered	T15,T26,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T15,T26,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T26,T9
DebounceSt->IdleSt	163	Covered	T15,T25,T9
DetectSt->IdleSt	186	Covered	T112,T116
DetectSt->StableSt	191	Covered	T15,T26,T9
IdleSt->DebounceSt	148	Covered	T15,T25,T26
StableSt->IdleSt	206	Covered	T15,T26,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T26,T9
0	1	Covered	T15,T25,T26
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T26,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T25,T26
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T26,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T9,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T25,T26
DetectSt	-	-	-	-	1	-	-	Covered	T112,T116
DetectSt	-	-	-	-	0	1	-	Covered	T15,T26,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T26,T9
StableSt	-	-	-	-	-	-	0	Covered	T15,T26,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	260	0	0
CntIncr_A	7221089	163719	0	0
CntNoWrap_A	7221089	6526858	0	0
DetectStDropOut_A	7221089	2	0	0
DetectedOut_A	7221089	797	0	0
DetectedPulseOut_A	7221089	114	0	0
DisabledIdleSt_A	7221089	6357255	0	0
DisabledNoDetection_A	7221089	6359752	0	0
EnterDebounceSt_A	7221089	147	0	0
EnterDetectSt_A	7221089	116	0	0
EnterStableSt_A	7221089	114	0	0
PulseIsPulse_A	7221089	114	0	0
StayInStableSt	7221089	683	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	7015	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	114	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	260	0	0
T3	480	0	0	0
T9	0	9	0	0
T15	698	3	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	2	0	0
T27	13360	0	0	0
T37	0	7	0	0
T50	0	1	0	0
T53	0	2	0	0
T54	0	2	0	0
T56	0	3	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T101	0	1	0	0
T102	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	163719	0	0
T3	480	0	0	0
T9	0	182	0	0
T15	698	101	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T25	0	11	0	0
T26	0	98	0	0
T27	13360	0	0	0
T37	0	235	0	0
T50	0	34	0	0
T53	0	57	0	0
T54	0	27	0	0
T56	0	62	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T101	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526858	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	294	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2	0	0
T89	7400	0	0	0
T112	721	1	0	0
T116	0	1	0	0
T121	25802	0	0	0
T122	11036	0	0	0
T123	39961	0	0	0
T124	1425	0	0	0
T125	424	0	0	0
T126	665	0	0	0
T127	15138	0	0	0
T128	34456	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	797	0	0
T3	480	0	0	0
T9	0	21	0	0
T15	698	6	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	12	0	0
T27	13360	0	0	0
T37	0	24	0	0
T53	0	4	0	0
T54	0	8	0	0
T56	0	6	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T132	0	23	0	0
T133	0	17	0	0
T134	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	114	0	0
T3	480	0	0	0
T9	0	4	0	0
T15	698	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	1	0	0
T27	13360	0	0	0
T37	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6357255	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	114	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6359752	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	114	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	147	0	0
T3	480	0	0	0
T9	0	5	0	0
T15	698	2	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	13360	0	0	0
T37	0	4	0	0
T50	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T101	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	116	0	0
T3	480	0	0	0
T9	0	4	0	0
T15	698	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	1	0	0
T27	13360	0	0	0
T37	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	114	0	0
T3	480	0	0	0
T9	0	4	0	0
T15	698	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	1	0	0
T27	13360	0	0	0
T37	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	114	0	0
T3	480	0	0	0
T9	0	4	0	0
T15	698	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	1	0	0
T27	13360	0	0	0
T37	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	683	0	0
T3	480	0	0	0
T9	0	17	0	0
T15	698	5	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	11	0	0
T27	13360	0	0	0
T37	0	21	0	0
T53	0	3	0	0
T54	0	7	0	0
T56	0	5	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T132	0	20	0	0
T133	0	15	0	0
T134	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	7015	0	0
T1	21527	9	0	0
T2	20722	11	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	15	0	0
T13	10672	20	0	0
T14	521	3	0	0
T15	698	3	0	0
T16	407	0	0	0
T17	509	5	0	0
T57	0	2	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	114	0	0
T3	480	0	0	0
T9	0	4	0	0
T15	698	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T26	0	1	0	0
T27	13360	0	0	0
T37	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T132	0	3	0	0
T133	0	2	0	0
T134	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T11,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T9,T11,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T11,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T21
1	0	Covered	T1,T4,T5
1	1	Covered	T9,T11,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T21
0	1	Covered	T64,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T21
0	1	Unreachable
1	0	Covered	T9,T11,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T21
DetectSt	168	Covered	T9,T11,T21
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T11,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T21
DebounceSt->IdleSt	163	Covered	T83,T34,T137
DetectSt->IdleSt	186	Covered	T64,T82,T83
DetectSt->StableSt	191	Covered	T9,T11,T21
IdleSt->DebounceSt	148	Covered	T9,T11,T21
StableSt->IdleSt	206	Covered	T9,T11,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T21
0	1	Covered	T9,T11,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T21
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T83,T34,T137
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T21
DetectSt	-	-	-	-	1	-	-	Covered	T64,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T21
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	175	0	0
CntIncr_A	7221089	163177	0	0
CntNoWrap_A	7221089	6526943	0	0
DetectStDropOut_A	7221089	26	0	0
DetectedOut_A	7221089	546965	0	0
DetectedPulseOut_A	7221089	44	0	0
DisabledIdleSt_A	7221089	5137577	0	0
DisabledNoDetection_A	7221089	5140125	0	0
EnterDebounceSt_A	7221089	105	0	0
EnterDetectSt_A	7221089	70	0	0
EnterStableSt_A	7221089	44	0	0
PulseIsPulse_A	7221089	44	0	0
StayInStableSt	7221089	546921	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	7015	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_sticky_sva.StableStDropOut_A	7221089	539429	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	175	0	0
T9	72485	2	0	0
T11	0	2	0	0
T21	0	2	0	0
T34	0	5	0	0
T38	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	6	0	0
T68	0	2	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	8	0	0
T83	0	9	0	0
T84	0	2	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	163177	0	0
T9	72485	96	0	0
T11	0	57	0	0
T21	0	90	0	0
T34	0	142	0	0
T38	0	89	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	267	0	0
T68	0	12	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	316	0	0
T83	0	80	0	0
T84	0	22	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526943	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	26	0	0
T43	1235	0	0	0
T56	21149	0	0	0
T64	847	3	0	0
T66	512	0	0	0
T67	560	0	0	0
T82	0	3	0	0
T83	0	4	0	0
T101	750	0	0	0
T109	0	1	0	0
T129	19520	0	0	0
T130	34013	0	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	3	0	0
T143	423	0	0	0
T144	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	546965	0	0
T9	72485	396	0	0
T11	0	166	0	0
T21	0	650	0	0
T34	0	529	0	0
T38	0	403	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	81	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	243	0	0
T84	0	106	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T98	0	481	0	0
T100	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	44	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T98	0	1	0	0
T100	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5137577	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5140125	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	105	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	3	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	3	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	4	0	0
T83	0	5	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	70	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	3	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	4	0	0
T83	0	4	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	44	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T98	0	1	0	0
T100	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	44	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T98	0	1	0	0
T100	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	546921	0	0
T9	72485	395	0	0
T11	0	165	0	0
T21	0	649	0	0
T34	0	527	0	0
T38	0	402	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	80	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	242	0	0
T84	0	105	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T98	0	480	0	0
T100	0	58	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	7015	0	0
T1	21527	9	0	0
T2	20722	11	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	15	0	0
T13	10672	20	0	0
T14	521	3	0	0
T15	698	3	0	0
T16	407	0	0	0
T17	509	5	0	0
T57	0	2	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	539429	0	0
T9	72485	68	0	0
T11	0	50	0	0
T21	0	157	0	0
T34	0	303	0	0
T38	0	42529	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	768	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	273	0	0
T84	0	95	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T98	0	108	0	0
T100	0	88	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T14,T3,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T14,T3,T17
1	1	Covered	T14,T3,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T11,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T9,T11,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T11,T68

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T21
1	0	Covered	T14,T3,T17
1	1	Covered	T9,T11,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T68
0	1	Covered	T98,T39,T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T68
0	1	Unreachable
1	0	Covered	T9,T11,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T21
DetectSt	168	Covered	T9,T11,T68
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T11,T68

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T68
DebounceSt->IdleSt	163	Covered	T21,T64,T98
DetectSt->IdleSt	186	Covered	T98,T39,T99
DetectSt->StableSt	191	Covered	T9,T11,T68
IdleSt->DebounceSt	148	Covered	T9,T11,T21
StableSt->IdleSt	206	Covered	T9,T11,T68

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T21
0	1	Covered	T9,T11,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T68
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T21
IdleSt	0	-	-	-	-	-	-	Covered	T14,T3,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T68
DebounceSt	-	0	1	0	-	-	-	Covered	T21,T64,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T21
DetectSt	-	-	-	-	1	-	-	Covered	T98,T39,T99
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T68
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T68
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T68
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	171	0	0
CntIncr_A	7221089	27680	0	0
CntNoWrap_A	7221089	6526947	0	0
DetectStDropOut_A	7221089	12	0	0
DetectedOut_A	7221089	107540	0	0
DetectedPulseOut_A	7221089	47	0	0
DisabledIdleSt_A	7221089	5137577	0	0
DisabledNoDetection_A	7221089	5140125	0	0
EnterDebounceSt_A	7221089	112	0	0
EnterDetectSt_A	7221089	59	0	0
EnterStableSt_A	7221089	47	0	0
PulseIsPulse_A	7221089	47	0	0
StayInStableSt	7221089	107493	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_sticky_sva.StableStDropOut_A	7221089	794052	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	171	0	0
T9	72485	2	0	0
T11	0	2	0	0
T21	0	5	0	0
T34	0	6	0	0
T38	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	3	0	0
T68	0	2	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	4	0	0
T83	0	2	0	0
T84	0	2	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	27680	0	0
T9	72485	89	0	0
T11	0	68	0	0
T21	0	130	0	0
T34	0	200	0	0
T38	0	8152	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	231	0	0
T68	0	82	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	178	0	0
T83	0	85	0	0
T84	0	23	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526947	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	12	0	0
T39	0	2	0	0
T98	1144	3	0	0
T99	0	1	0	0
T145	0	6	0	0
T146	502	0	0	0
T147	1035	0	0	0
T148	499	0	0	0
T149	404	0	0	0
T150	767	0	0	0
T151	31119	0	0	0
T152	7592	0	0	0
T153	29825	0	0	0
T154	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	107540	0	0
T9	72485	181	0	0
T11	0	70	0	0
T34	0	733	0	0
T38	0	34794	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	691	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	737	0	0
T83	0	524	0	0
T84	0	112	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T100	0	29	0	0
T136	0	709	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	47	0	0
T9	72485	1	0	0
T11	0	1	0	0
T34	0	3	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T100	0	1	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5137577	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5140125	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	112	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	5	0	0
T34	0	3	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	3	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	59	0	0
T9	72485	1	0	0
T11	0	1	0	0
T34	0	3	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T98	0	3	0	0
T100	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	47	0	0
T9	72485	1	0	0
T11	0	1	0	0
T34	0	3	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T100	0	1	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	47	0	0
T9	72485	1	0	0
T11	0	1	0	0
T34	0	3	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T100	0	1	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	107493	0	0
T9	72485	180	0	0
T11	0	69	0	0
T34	0	730	0	0
T38	0	34793	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	690	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	735	0	0
T83	0	523	0	0
T84	0	111	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T100	0	28	0	0
T136	0	708	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	794052	0	0
T9	72485	286	0	0
T11	0	136	0	0
T34	0	516	0	0
T38	0	64	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T68	0	72	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	131	0	0
T83	0	101	0	0
T84	0	87	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T100	0	128	0	0
T136	0	372	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T11,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T9,T11,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T11,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T21
1	0	Covered	T1,T4,T5
1	1	Covered	T9,T11,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T21
0	1	Covered	T34,T39,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T21
0	1	Unreachable
1	0	Covered	T9,T11,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T21
DetectSt	168	Covered	T9,T11,T21
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T11,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T21
DebounceSt->IdleSt	163	Covered	T34,T100,T136
DetectSt->IdleSt	186	Covered	T34,T39,T96
DetectSt->StableSt	191	Covered	T9,T11,T21
IdleSt->DebounceSt	148	Covered	T9,T11,T21
StableSt->IdleSt	206	Covered	T9,T11,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T21
0	1	Covered	T9,T11,T21
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T21
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T21
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T100,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T21
DetectSt	-	-	-	-	1	-	-	Covered	T34,T39,T96
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T21
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	156	0	0
CntIncr_A	7221089	95000	0	0
CntNoWrap_A	7221089	6526962	0	0
DetectStDropOut_A	7221089	8	0	0
DetectedOut_A	7221089	468843	0	0
DetectedPulseOut_A	7221089	48	0	0
DisabledIdleSt_A	7221089	5137577	0	0
DisabledNoDetection_A	7221089	5140125	0	0
EnterDebounceSt_A	7221089	100	0	0
EnterDetectSt_A	7221089	56	0	0
EnterStableSt_A	7221089	48	0	0
PulseIsPulse_A	7221089	48	0	0
StayInStableSt	7221089	468795	0	0
gen_high_event_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_sticky_sva.StableStDropOut_A	7221089	718352	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	156	0	0
T9	72485	2	0	0
T11	0	2	0	0
T21	0	2	0	0
T34	0	10	0	0
T38	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	2	0	0
T68	0	2	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	4	0	0
T83	0	2	0	0
T84	0	2	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	95000	0	0
T9	72485	32	0	0
T11	0	86	0	0
T21	0	80	0	0
T34	0	414	0	0
T38	0	47	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	29	0	0
T68	0	89	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	138	0	0
T83	0	64	0	0
T84	0	48	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526962	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	8	0	0
T34	50437	2	0	0
T38	58391	0	0	0
T39	0	2	0	0
T74	496	0	0	0
T84	1885	0	0	0
T96	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	35175	0	0	0
T158	427	0	0	0
T159	530	0	0	0
T160	1009	0	0	0
T161	408	0	0	0
T162	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	468843	0	0
T9	72485	107	0	0
T11	0	114	0	0
T21	0	451	0	0
T34	0	470	0	0
T38	0	157	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	139	0	0
T68	0	362	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	769	0	0
T83	0	374	0	0
T84	0	139	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	48	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	1	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5137577	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5140125	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	100	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	6	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	1	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	56	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	4	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	1	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	48	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	1	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	48	0	0
T9	72485	1	0	0
T11	0	1	0	0
T21	0	1	0	0
T34	0	2	0	0
T38	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	1	0	0
T68	0	1	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	468795	0	0
T9	72485	106	0	0
T11	0	113	0	0
T21	0	450	0	0
T34	0	468	0	0
T38	0	156	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	138	0	0
T68	0	361	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	767	0	0
T83	0	373	0	0
T84	0	138	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	718352	0	0
T9	72485	428	0	0
T11	0	81	0	0
T21	0	383	0	0
T34	0	308	0	0
T38	0	42825	0	0
T49	6222	0	0	0
T50	690	0	0	0
T51	692	0	0	0
T64	0	240	0	0
T68	0	414	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T82	0	157	0	0
T83	0	289	0	0
T84	0	48	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T36,T42,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T36,T42,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T42,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T36,T44,T41
1	0	Covered	T1,T4,T5
1	1	Covered	T36,T42,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T45,T46
0	1	Covered	T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T45,T46
0	1	Covered	T45,T105,T147
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T45,T46
1	-	Covered	T45,T105,T147

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T42,T45
DetectSt	168	Covered	T42,T45,T46
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T42,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T45,T46
DebounceSt->IdleSt	163	Covered	T36,T89,T97
DetectSt->IdleSt	186	Covered	T97
DetectSt->StableSt	191	Covered	T42,T45,T46
IdleSt->DebounceSt	148	Covered	T36,T42,T45
StableSt->IdleSt	206	Covered	T45,T105,T147

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T42,T45
0	1	Covered	T36,T42,T45
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T45,T46
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T42,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T97,T163
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T42,T45
DetectSt	-	-	-	-	1	-	-	Covered	T97
DetectSt	-	-	-	-	0	1	-	Covered	T42,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T105,T147
StableSt	-	-	-	-	-	-	0	Covered	T42,T45,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	90	0	0
CntIncr_A	7221089	26872	0	0
CntNoWrap_A	7221089	6527028	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	17890	0	0
DetectedPulseOut_A	7221089	42	0	0
DisabledIdleSt_A	7221089	6438323	0	0
DisabledNoDetection_A	7221089	6440810	0	0
EnterDebounceSt_A	7221089	47	0	0
EnterDetectSt_A	7221089	43	0	0
EnterStableSt_A	7221089	42	0	0
PulseIsPulse_A	7221089	42	0	0
StayInStableSt	7221089	17825	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	90	0	0
T36	856	1	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	540	0	0	0
T42	0	2	0	0
T44	549	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	7812	0	0	0
T68	1300	0	0	0
T80	5274	0	0	0
T105	0	4	0	0
T147	0	2	0	0
T150	0	2	0	0
T164	0	4	0	0
T165	422	0	0	0
T166	654	0	0	0
T167	425	0	0	0
T168	405	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	26872	0	0
T36	856	88	0	0
T39	0	62	0	0
T40	0	22	0	0
T41	540	0	0	0
T42	0	29	0	0
T44	549	0	0	0
T45	0	59	0	0
T46	0	69	0	0
T47	7812	0	0	0
T68	1300	0	0	0
T80	5274	0	0	0
T105	0	98	0	0
T147	0	91	0	0
T150	0	81	0	0
T164	0	40	0	0
T165	422	0	0	0
T166	654	0	0	0
T167	425	0	0	0
T168	405	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6527028	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T97	21242	1	0	0
T169	1083	0	0	0
T170	9485	0	0	0
T171	528	0	0	0
T172	491	0	0	0
T173	625	0	0	0
T174	537	0	0	0
T175	490	0	0	0
T176	34467	0	0	0
T177	15064	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	17890	0	0
T39	0	132	0	0
T40	0	42	0	0
T42	618	87	0	0
T45	277156	55	0	0
T46	0	45	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T105	0	135	0	0
T109	0	44	0	0
T134	692	0	0	0
T147	0	40	0	0
T150	0	69	0	0
T164	0	106	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	618	1	0	0
T45	277156	1	0	0
T46	0	1	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T105	0	2	0	0
T109	0	1	0	0
T134	692	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	2	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6438323	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6440810	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	47	0	0
T36	856	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	540	0	0	0
T42	0	1	0	0
T44	549	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	7812	0	0	0
T68	1300	0	0	0
T80	5274	0	0	0
T105	0	2	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	2	0	0
T165	422	0	0	0
T166	654	0	0	0
T167	425	0	0	0
T168	405	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	43	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	618	1	0	0
T45	277156	1	0	0
T46	0	1	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T105	0	2	0	0
T109	0	1	0	0
T134	692	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	2	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	618	1	0	0
T45	277156	1	0	0
T46	0	1	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T105	0	2	0	0
T109	0	1	0	0
T134	692	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	2	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	618	1	0	0
T45	277156	1	0	0
T46	0	1	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T105	0	2	0	0
T109	0	1	0	0
T134	692	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	2	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	17825	0	0
T39	0	129	0	0
T40	0	41	0	0
T42	618	85	0	0
T45	277156	54	0	0
T46	0	43	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T105	0	132	0	0
T109	0	43	0	0
T134	692	0	0	0
T147	0	39	0	0
T150	0	67	0	0
T164	0	103	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	18	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	277156	1	0	0
T73	494	0	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T93	0	1	0	0
T105	0	1	0	0
T109	0	1	0	0
T134	692	0	0	0
T147	0	1	0	0
T164	0	1	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0
T183	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T10,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T10,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T10,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T5,T2
1	1	Covered	T6,T10,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T37
0	1	Covered	T155,T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T37
0	1	Covered	T10,T46,T105
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T10,T37
1	-	Covered	T10,T46,T105

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T10,T37
DetectSt	168	Covered	T6,T10,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T10,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T10,T37
DebounceSt->IdleSt	163	Covered	T183,T89,T186
DetectSt->IdleSt	186	Covered	T155,T185
DetectSt->StableSt	191	Covered	T6,T10,T37
IdleSt->DebounceSt	148	Covered	T6,T10,T37
StableSt->IdleSt	206	Covered	T6,T10,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T10,T37
0	1	Covered	T6,T10,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T10,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T10,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T183,T186,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T10,T37
DetectSt	-	-	-	-	1	-	-	Covered	T155,T185
DetectSt	-	-	-	-	0	1	-	Covered	T6,T10,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T46,T105
StableSt	-	-	-	-	-	-	0	Covered	T6,T10,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	141	0	0
CntIncr_A	7221089	40341	0	0
CntNoWrap_A	7221089	6526977	0	0
DetectStDropOut_A	7221089	2	0	0
DetectedOut_A	7221089	6013	0	0
DetectedPulseOut_A	7221089	66	0	0
DisabledIdleSt_A	7221089	6437330	0	0
DisabledNoDetection_A	7221089	6439813	0	0
EnterDebounceSt_A	7221089	73	0	0
EnterDetectSt_A	7221089	68	0	0
EnterStableSt_A	7221089	66	0	0
PulseIsPulse_A	7221089	66	0	0
StayInStableSt	7221089	5919	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	2724	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	141	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	4	0	0
T37	0	2	0	0
T46	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	4	0	0
T109	0	8	0	0
T150	0	2	0	0
T164	0	4	0	0
T188	0	2	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	40341	0	0
T6	3475	73	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	122	0	0
T37	0	15	0	0
T46	0	69	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	98	0	0
T109	0	240	0	0
T150	0	81	0	0
T164	0	40	0	0
T188	0	48	0	0
T189	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526977	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2	0	0
T155	41800	1	0	0
T185	0	1	0	0
T190	2243	0	0	0
T191	492	0	0	0
T192	423	0	0	0
T193	506	0	0	0
T194	6425	0	0	0
T195	21629	0	0	0
T196	420	0	0	0
T197	16924	0	0	0
T198	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6013	0	0
T6	3475	176	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	81	0	0
T37	0	75	0	0
T46	0	50	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	61	0	0
T109	0	268	0	0
T150	0	44	0	0
T164	0	57	0	0
T188	0	45	0	0
T189	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	2	0	0
T37	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T109	0	4	0	0
T150	0	1	0	0
T164	0	2	0	0
T188	0	1	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6437330	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6439813	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	73	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	2	0	0
T37	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T109	0	4	0	0
T150	0	1	0	0
T164	0	2	0	0
T188	0	1	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	68	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	2	0	0
T37	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T109	0	4	0	0
T150	0	1	0	0
T164	0	2	0	0
T188	0	1	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	2	0	0
T37	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T109	0	4	0	0
T150	0	1	0	0
T164	0	2	0	0
T188	0	1	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	2	0	0
T37	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T109	0	4	0	0
T150	0	1	0	0
T164	0	2	0	0
T188	0	1	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5919	0	0
T6	3475	174	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	78	0	0
T37	0	73	0	0
T46	0	49	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	59	0	0
T109	0	262	0	0
T150	0	43	0	0
T164	0	55	0	0
T188	0	43	0	0
T189	0	57	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2724	0	0
T3	480	0	0	0
T6	0	2	0	0
T7	0	12	0	0
T14	521	6	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	4	0	0
T22	488	6	0	0
T23	0	5	0	0
T25	0	3	0	0
T27	13360	0	0	0
T57	422	2	0	0
T58	426	0	0	0
T59	716	0	0	0
T61	0	6	0	0
T62	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	37	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T46	0	1	0	0
T79	502	0	0	0
T105	0	2	0	0
T109	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	1	0	0
T164	0	2	0	0
T183	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T202	438	0	0	0