Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T10,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T10,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T10,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T8,T10,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T36
0	1	Covered	T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T36
0	1	Covered	T8,T10,T39
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T10,T36
1	-	Covered	T8,T10,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T36
DetectSt	168	Covered	T8,T10,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T10,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T36
DebounceSt->IdleSt	163	Covered	T89,T203
DetectSt->IdleSt	186	Covered	T185
DetectSt->StableSt	191	Covered	T8,T10,T36
IdleSt->DebounceSt	148	Covered	T8,T10,T36
StableSt->IdleSt	206	Covered	T8,T10,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T10,T36
0	1	Covered	T8,T10,T36
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T203
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T36
DetectSt	-	-	-	-	1	-	-	Covered	T185
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	74	0	0
CntIncr_A	7221089	37032	0	0
CntNoWrap_A	7221089	6527044	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	2341	0	0
DetectedPulseOut_A	7221089	35	0	0
DisabledIdleSt_A	7221089	6307941	0	0
DisabledNoDetection_A	7221089	6310427	0	0
EnterDebounceSt_A	7221089	38	0	0
EnterDetectSt_A	7221089	36	0	0
EnterStableSt_A	7221089	35	0	0
PulseIsPulse_A	7221089	35	0	0
StayInStableSt	7221089	2285	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	74	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	0	2	0	0
T42	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	2	0	0
T109	0	2	0	0
T150	0	2	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	37032	0	0
T8	686	58	0	0
T9	72485	0	0	0
T10	0	61	0	0
T36	0	88	0	0
T37	0	15	0	0
T39	0	31	0	0
T42	0	29	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	45	0	0
T109	0	22	0	0
T150	0	81	0	0
T189	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6527044	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T185	2083	1	0	0
T186	68688	0	0	0
T204	684	0	0	0
T205	496	0	0	0
T206	781	0	0	0
T207	523	0	0	0
T208	494	0	0	0
T209	491	0	0	0
T210	18060	0	0	0
T211	8526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2341	0	0
T8	686	8	0	0
T9	72485	0	0	0
T10	0	49	0	0
T36	0	40	0	0
T37	0	60	0	0
T39	0	18	0	0
T42	0	86	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	42	0	0
T109	0	41	0	0
T150	0	194	0	0
T189	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	35	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	1	0	0
T109	0	1	0	0
T150	0	1	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6307941	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6310427	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	1	0	0
T109	0	1	0	0
T150	0	1	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	36	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	1	0	0
T109	0	1	0	0
T150	0	1	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	35	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	1	0	0
T109	0	1	0	0
T150	0	1	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	35	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	1	0	0
T109	0	1	0	0
T150	0	1	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2285	0	0
T8	686	7	0	0
T9	72485	0	0	0
T10	0	48	0	0
T36	0	38	0	0
T37	0	58	0	0
T39	0	17	0	0
T42	0	84	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T105	0	40	0	0
T109	0	39	0	0
T150	0	192	0	0
T189	0	41	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	13	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T39	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T93	0	2	0	0
T97	0	1	0	0
T183	0	1	0	0
T189	0	1	0	0
T201	0	1	0	0
T212	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T1,T5,T2
1	1	Covered	T6,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T37,T93,T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T43
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T10
1	-	Covered	T6,T8,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T10
DetectSt	168	Covered	T6,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T10
DebounceSt->IdleSt	163	Covered	T45,T179,T105
DetectSt->IdleSt	186	Covered	T37,T93,T213
DetectSt->StableSt	191	Covered	T6,T8,T10
IdleSt->DebounceSt	148	Covered	T6,T8,T10
StableSt->IdleSt	206	Covered	T6,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T179,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T37,T93,T213
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T43
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	146	0	0
CntIncr_A	7221089	17610	0	0
CntNoWrap_A	7221089	6526972	0	0
DetectStDropOut_A	7221089	3	0	0
DetectedOut_A	7221089	18947	0	0
DetectedPulseOut_A	7221089	66	0	0
DisabledIdleSt_A	7221089	6479949	0	0
DisabledNoDetection_A	7221089	6482433	0	0
EnterDebounceSt_A	7221089	77	0	0
EnterDetectSt_A	7221089	69	0	0
EnterStableSt_A	7221089	66	0	0
PulseIsPulse_A	7221089	66	0	0
StayInStableSt	7221089	18847	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	3196	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	146	0	0
T6	3475	4	0	0
T7	33409	0	0	0
T8	686	4	0	0
T9	72485	0	0	0
T10	0	2	0	0
T37	0	4	0	0
T42	0	2	0	0
T43	0	4	0	0
T45	0	1	0	0
T46	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T179	0	1	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	17610	0	0
T6	3475	119	0	0
T7	33409	0	0	0
T8	686	116	0	0
T9	72485	0	0	0
T10	0	77	0	0
T37	0	53	0	0
T42	0	29	0	0
T43	0	192	0	0
T45	0	59	0	0
T46	0	69	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T179	0	73	0	0
T188	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526972	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3	0	0
T33	14496	0	0	0
T37	25849	1	0	0
T93	0	1	0	0
T102	577	0	0	0
T132	712	0	0	0
T133	812	0	0	0
T213	0	1	0	0
T214	525	0	0	0
T215	424	0	0	0
T216	18015	0	0	0
T217	576	0	0	0
T218	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	18947	0	0
T6	3475	450	0	0
T7	33409	0	0	0
T8	686	82	0	0
T9	72485	0	0	0
T10	0	237	0	0
T37	0	50	0	0
T38	0	268	0	0
T42	0	44	0	0
T43	0	136	0	0
T46	0	44	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	19	0	0
T219	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T42	0	1	0	0
T43	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0
T219	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6479949	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6482433	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	77	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T37	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T179	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	69	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T37	0	2	0	0
T38	0	3	0	0
T42	0	1	0	0
T43	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0
T219	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T42	0	1	0	0
T43	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0
T219	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T37	0	1	0	0
T38	0	3	0	0
T42	0	1	0	0
T43	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0
T219	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	18847	0	0
T6	3475	447	0	0
T7	33409	0	0	0
T8	686	79	0	0
T9	72485	0	0	0
T10	0	235	0	0
T37	0	48	0	0
T38	0	263	0	0
T42	0	43	0	0
T43	0	133	0	0
T46	0	42	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	18	0	0
T219	0	57	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3196	0	0
T3	480	0	0	0
T14	521	5	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	5	0	0
T22	488	5	0	0
T23	0	5	0	0
T25	0	2	0	0
T27	13360	0	0	0
T57	422	4	0	0
T58	426	3	0	0
T59	716	4	0	0
T60	0	3	0	0
T61	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	31	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T109	0	1	0	0
T188	0	1	0	0
T219	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T41
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T10
1	-	Covered	T6,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T10
DetectSt	168	Covered	T6,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T10
DebounceSt->IdleSt	163	Covered	T105,T147,T189
DetectSt->IdleSt	186	Covered	T41
DetectSt->StableSt	191	Covered	T6,T8,T10
IdleSt->DebounceSt	148	Covered	T6,T8,T10
StableSt->IdleSt	206	Covered	T6,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T109,T183
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T41
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	162	0	0
CntIncr_A	7221089	4822	0	0
CntNoWrap_A	7221089	6526956	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	5907	0	0
DetectedPulseOut_A	7221089	76	0	0
DisabledIdleSt_A	7221089	6505921	0	0
DisabledNoDetection_A	7221089	6508405	0	0
EnterDebounceSt_A	7221089	87	0	0
EnterDetectSt_A	7221089	77	0	0
EnterStableSt_A	7221089	76	0	0
PulseIsPulse_A	7221089	76	0	0
StayInStableSt	7221089	5795	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	162	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	4	0	0
T9	72485	0	0	0
T10	0	2	0	0
T36	0	4	0	0
T37	0	4	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T46	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	4822	0	0
T6	3475	73	0	0
T7	33409	0	0	0
T8	686	116	0	0
T9	72485	0	0	0
T10	0	61	0	0
T36	0	176	0	0
T37	0	76	0	0
T38	0	89	0	0
T41	0	44	0	0
T42	0	58	0	0
T46	0	69	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526956	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T41	540	1	0	0
T47	7812	0	0	0
T68	1300	0	0	0
T80	5274	0	0	0
T135	32518	0	0	0
T166	654	0	0	0
T167	425	0	0	0
T168	405	0	0	0
T220	444	0	0	0
T221	430	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5907	0	0
T6	3475	5	0	0
T7	33409	0	0	0
T8	686	93	0	0
T9	72485	0	0	0
T10	0	40	0	0
T36	0	119	0	0
T37	0	140	0	0
T38	0	43	0	0
T42	0	115	0	0
T46	0	166	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	136	0	0
T150	0	277	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	76	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6505921	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	3	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6508405	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	3	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	87	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	77	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	76	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	76	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	5795	0	0
T6	3475	4	0	0
T7	33409	0	0	0
T8	686	90	0	0
T9	72485	0	0	0
T10	0	39	0	0
T36	0	116	0	0
T37	0	137	0	0
T38	0	41	0	0
T42	0	112	0	0
T46	0	164	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	133	0	0
T150	0	275	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	39	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T42	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T109	0	1	0	0
T147	0	1	0	0
T164	0	2	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T8,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T43
0	1	Covered	T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T43
0	1	Covered	T8,T36,T37
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T43
1	-	Covered	T8,T36,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T43
DetectSt	168	Covered	T6,T8,T43
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T43
DebounceSt->IdleSt	163	Covered	T89,T163,T186
DetectSt->IdleSt	186	Covered	T40
DetectSt->StableSt	191	Covered	T6,T8,T43
IdleSt->DebounceSt	148	Covered	T6,T8,T43
StableSt->IdleSt	206	Covered	T6,T8,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T43
0	1	Covered	T6,T8,T43
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T43
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T186
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T43
DetectSt	-	-	-	-	1	-	-	Covered	T40
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	87	0	0
CntIncr_A	7221089	63051	0	0
CntNoWrap_A	7221089	6527031	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	2858	0	0
DetectedPulseOut_A	7221089	41	0	0
DisabledIdleSt_A	7221089	6221043	0	0
DisabledNoDetection_A	7221089	6223529	0	0
EnterDebounceSt_A	7221089	45	0	0
EnterDetectSt_A	7221089	42	0	0
EnterStableSt_A	7221089	41	0	0
PulseIsPulse_A	7221089	41	0	0
StayInStableSt	7221089	2801	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	6679	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	87	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T40	0	2	0	0
T43	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	4	0	0
T147	0	4	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	63051	0	0
T6	3475	73	0	0
T7	33409	0	0	0
T8	686	58	0	0
T9	72485	0	0	0
T34	0	53	0	0
T36	0	88	0	0
T37	0	53	0	0
T40	0	62	0	0
T43	0	96	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	98	0	0
T147	0	182	0	0
T189	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6527031	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T40	11779	1	0	0
T137	1569	0	0	0
T164	660	0	0	0
T222	16535	0	0	0
T223	994	0	0	0
T224	492	0	0	0
T225	1147	0	0	0
T226	507	0	0	0
T227	78378	0	0	0
T228	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2858	0	0
T6	3475	290	0	0
T7	33409	0	0	0
T8	686	8	0	0
T9	72485	0	0	0
T34	0	112	0	0
T36	0	61	0	0
T37	0	143	0	0
T43	0	168	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	61	0	0
T147	0	84	0	0
T164	0	107	0	0
T189	0	147	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	41	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T43	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T147	0	2	0	0
T164	0	2	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6221043	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	3	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6223529	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	3	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	45	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T43	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T147	0	2	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T43	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T147	0	2	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	41	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T43	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T147	0	2	0	0
T164	0	2	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	41	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T43	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	2	0	0
T147	0	2	0	0
T164	0	2	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2801	0	0
T6	3475	288	0	0
T7	33409	0	0	0
T8	686	7	0	0
T9	72485	0	0	0
T34	0	111	0	0
T36	0	60	0	0
T37	0	140	0	0
T43	0	166	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T105	0	59	0	0
T147	0	82	0	0
T164	0	104	0	0
T189	0	146	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6679	0	0
T1	21527	11	0	0
T2	20722	10	0	0
T3	480	0	0	0
T4	5866	27	0	0
T5	23035	10	0	0
T13	10672	31	0	0
T14	521	5	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	5	0	0
T22	0	7	0	0
T57	0	2	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	24	0	0
T8	686	1	0	0
T9	72485	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T93	0	1	0	0
T105	0	2	0	0
T147	0	2	0	0
T164	0	1	0	0
T183	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T6,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T10
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T6,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T10
1	-	Covered	T3,T6,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T10
DetectSt	168	Covered	T3,T6,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T6,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T10
DebounceSt->IdleSt	163	Covered	T105,T150,T199
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T6,T10
IdleSt->DebounceSt	148	Covered	T3,T6,T10
StableSt->IdleSt	206	Covered	T3,T6,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T199,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	140	0	0
CntIncr_A	7221089	39158	0	0
CntNoWrap_A	7221089	6526978	0	0
DetectStDropOut_A	7221089	0	0	0
DetectedOut_A	7221089	126774	0	0
DetectedPulseOut_A	7221089	67	0	0
DisabledIdleSt_A	7221089	6315879	0	0
DisabledNoDetection_A	7221089	6318367	0	0
EnterDebounceSt_A	7221089	74	0	0
EnterDetectSt_A	7221089	67	0	0
EnterStableSt_A	7221089	67	0	0
PulseIsPulse_A	7221089	67	0	0
StayInStableSt	7221089	126679	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	140	0	0
T3	480	2	0	0
T6	0	4	0	0
T10	0	2	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T45	0	2	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	2	0	0
T150	0	1	0	0
T164	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	39158	0	0
T3	480	14	0	0
T6	0	119	0	0
T10	0	61	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	15	0	0
T38	0	45	0	0
T40	0	62	0	0
T45	0	59	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	79	0	0
T150	0	81	0	0
T164	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526978	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	77	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	126774	0	0
T3	480	4	0	0
T6	0	106	0	0
T10	0	111	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	60	0	0
T38	0	124	0	0
T40	0	103	0	0
T45	0	89	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	396	0	0
T109	0	151	0	0
T164	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	67	0	0
T3	480	1	0	0
T6	0	2	0	0
T10	0	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T45	0	1	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	1	0	0
T109	0	2	0	0
T164	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6315879	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	3	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6318367	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	3	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	74	0	0
T3	480	1	0	0
T6	0	2	0	0
T10	0	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T45	0	1	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	2	0	0
T150	0	1	0	0
T164	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	67	0	0
T3	480	1	0	0
T6	0	2	0	0
T10	0	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T45	0	1	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	1	0	0
T109	0	2	0	0
T164	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	67	0	0
T3	480	1	0	0
T6	0	2	0	0
T10	0	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T45	0	1	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	1	0	0
T109	0	2	0	0
T164	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	67	0	0
T3	480	1	0	0
T6	0	2	0	0
T10	0	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T45	0	1	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	1	0	0
T109	0	2	0	0
T164	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	126679	0	0
T3	480	3	0	0
T6	0	104	0	0
T10	0	110	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T37	0	58	0	0
T38	0	122	0	0
T40	0	102	0	0
T45	0	88	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T105	0	394	0	0
T109	0	149	0	0
T164	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38	0	0
T3	480	1	0	0
T6	0	2	0	0
T10	0	1	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T40	0	1	0	0
T45	0	1	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T109	0	2	0	0
T164	0	1	0	0
T183	0	1	0	0
T199	0	3	0	0
T229	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T10,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T10,T44
1	0	Covered	T1,T4,T5
1	1	Covered	T10,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T42
0	1	Covered	T42,T34,T147
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T41,T42
1	-	Covered	T42,T34,T147

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T41,T42
DetectSt	168	Covered	T10,T41,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T10,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T41,T42
DebounceSt->IdleSt	163	Covered	T89,T230
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T41,T42
IdleSt->DebounceSt	148	Covered	T10,T41,T42
StableSt->IdleSt	206	Covered	T10,T42,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T41,T42
0	1	Covered	T10,T41,T42
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T41,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T230
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T34,T147
StableSt	-	-	-	-	-	-	0	Covered	T10,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	102	0	0
CntIncr_A	7221089	38029	0	0
CntNoWrap_A	7221089	6527016	0	0
DetectStDropOut_A	7221089	0	0	0
DetectedOut_A	7221089	3559	0	0
DetectedPulseOut_A	7221089	50	0	0
DisabledIdleSt_A	7221089	6305070	0	0
DisabledNoDetection_A	7221089	6307556	0	0
EnterDebounceSt_A	7221089	52	0	0
EnterDetectSt_A	7221089	50	0	0
EnterStableSt_A	7221089	50	0	0
PulseIsPulse_A	7221089	50	0	0
StayInStableSt	7221089	3482	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	6209	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	102	0	0
T10	2446	2	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T79	502	0	0	0
T109	0	4	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	2	0	0
T150	0	2	0	0
T164	0	2	0	0
T179	0	2	0	0
T202	438	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38029	0	0
T10	2446	61	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	71	0	0
T41	0	44	0	0
T42	0	29	0	0
T45	0	59	0	0
T79	502	0	0	0
T109	0	196	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	91	0	0
T150	0	81	0	0
T164	0	20	0	0
T179	0	73	0	0
T202	438	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6527016	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3559	0	0
T10	2446	154	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	42	0	0
T41	0	42	0	0
T42	0	44	0	0
T45	0	156	0	0
T79	502	0	0	0
T109	0	89	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	1	0	0
T150	0	42	0	0
T164	0	95	0	0
T179	0	290	0	0
T202	438	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T79	502	0	0	0
T109	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	1	0	0
T179	0	1	0	0
T202	438	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6305070	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6307556	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	52	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T79	502	0	0	0
T109	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	1	0	0
T179	0	1	0	0
T202	438	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T79	502	0	0	0
T109	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	1	0	0
T179	0	1	0	0
T202	438	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T79	502	0	0	0
T109	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	1	0	0
T179	0	1	0	0
T202	438	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T45	0	1	0	0
T79	502	0	0	0
T109	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T147	0	1	0	0
T150	0	1	0	0
T164	0	1	0	0
T179	0	1	0	0
T202	438	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3482	0	0
T10	2446	152	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	41	0	0
T41	0	40	0	0
T42	0	43	0	0
T45	0	154	0	0
T79	502	0	0	0
T109	0	86	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	40	0	0
T164	0	94	0	0
T179	0	288	0	0
T199	0	206	0	0
T202	438	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6209	0	0
T1	21527	10	0	0
T2	20722	13	0	0
T3	480	1	0	0
T4	5866	25	0	0
T5	23035	10	0	0
T13	10672	16	0	0
T14	521	5	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	4	0	0
T57	0	3	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	22	0	0
T34	0	1	0	0
T42	618	1	0	0
T45	277156	0	0	0
T82	1680	0	0	0
T83	3148	0	0	0
T93	0	1	0	0
T109	0	1	0	0
T134	692	0	0	0
T147	0	1	0	0
T164	0	1	0	0
T178	425	0	0	0
T179	839	0	0	0
T180	509	0	0	0
T181	55849	0	0	0
T182	402	0	0	0
T183	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0
T213	0	1	0	0