Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T6,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T6,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T10
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T6,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T190
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T6,T10,T43
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T10
1	-	Covered	T6,T10,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T10
DetectSt	168	Covered	T3,T6,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T6,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T10
DebounceSt->IdleSt	163	Covered	T36,T37,T105
DetectSt->IdleSt	186	Covered	T190
DetectSt->StableSt	191	Covered	T3,T6,T10
IdleSt->DebounceSt	148	Covered	T3,T6,T10
StableSt->IdleSt	206	Covered	T6,T10,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T37,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	1	-	-	Covered	T190
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T10,T43
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	166	0	0
CntIncr_A	7221089	29818	0	0
CntNoWrap_A	7221089	6526952	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	46647	0	0
DetectedPulseOut_A	7221089	78	0	0
DisabledIdleSt_A	7221089	6407174	0	0
DisabledNoDetection_A	7221089	6409656	0	0
EnterDebounceSt_A	7221089	89	0	0
EnterDetectSt_A	7221089	79	0	0
EnterStableSt_A	7221089	78	0	0
PulseIsPulse_A	7221089	78	0	0
StayInStableSt	7221089	46535	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	166	0	0
T3	480	2	0	0
T6	0	2	0	0
T10	0	6	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	6	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	29818	0	0
T3	480	14	0	0
T6	0	46	0	0
T10	0	199	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	176	0	0
T37	0	38	0	0
T38	0	45	0	0
T41	0	44	0	0
T42	0	29	0	0
T43	0	288	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T179	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526952	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	77	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T142	36599	0	0	0
T190	2243	1	0	0
T191	492	0	0	0
T192	423	0	0	0
T193	506	0	0	0
T194	6425	0	0	0
T195	21629	0	0	0
T196	420	0	0	0
T197	16924	0	0	0
T198	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	46647	0	0
T3	480	38	0	0
T6	0	43	0	0
T10	0	362	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	79	0	0
T38	0	40	0	0
T41	0	41	0	0
T42	0	3	0	0
T43	0	273	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T147	0	46	0	0
T179	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	78	0	0
T3	480	1	0	0
T6	0	1	0	0
T10	0	3	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T147	0	2	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6407174	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	3	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6409656	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	3	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	89	0	0
T3	480	1	0	0
T6	0	1	0	0
T10	0	3	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	79	0	0
T3	480	1	0	0
T6	0	1	0	0
T10	0	3	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T147	0	2	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	78	0	0
T3	480	1	0	0
T6	0	1	0	0
T10	0	3	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T147	0	2	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	78	0	0
T3	480	1	0	0
T6	0	1	0	0
T10	0	3	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	3	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T147	0	2	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	46535	0	0
T3	480	36	0	0
T6	0	42	0	0
T10	0	358	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	13360	0	0	0
T36	0	78	0	0
T38	0	38	0	0
T41	0	39	0	0
T42	0	2	0	0
T43	0	269	0	0
T48	15670	0	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T60	1591	0	0	0
T147	0	43	0	0
T179	0	169	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	43	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	2	0	0
T36	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T109	0	1	0	0
T147	0	1	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T231
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T10
0	1	Covered	T8,T36,T147
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T10
1	-	Covered	T8,T36,T147

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T10
DetectSt	168	Covered	T6,T8,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T10
DebounceSt->IdleSt	163	Covered	T189,T89
DetectSt->IdleSt	186	Covered	T231
DetectSt->StableSt	191	Covered	T6,T8,T10
IdleSt->DebounceSt	148	Covered	T6,T8,T10
StableSt->IdleSt	206	Covered	T6,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T10
0	1	Covered	T6,T8,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T10
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T231
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T36,T147
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	87	0	0
CntIncr_A	7221089	84667	0	0
CntNoWrap_A	7221089	6527031	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	3309	0	0
DetectedPulseOut_A	7221089	42	0	0
DisabledIdleSt_A	7221089	6239436	0	0
DisabledNoDetection_A	7221089	6241923	0	0
EnterDebounceSt_A	7221089	45	0	0
EnterDetectSt_A	7221089	43	0	0
EnterStableSt_A	7221089	42	0	0
PulseIsPulse_A	7221089	42	0	0
StayInStableSt	7221089	3247	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	6303	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	87	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	0	0	0
T10	0	2	0	0
T36	0	4	0	0
T45	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	4	0	0
T150	0	2	0	0
T199	0	2	0	0
T219	0	2	0	0
T232	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	84667	0	0
T6	3475	73	0	0
T7	33409	0	0	0
T8	686	58	0	0
T9	72485	0	0	0
T10	0	77	0	0
T36	0	176	0	0
T45	0	59	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	182	0	0
T150	0	81	0	0
T189	0	63	0	0
T199	0	73	0	0
T219	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6527031	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T155	41800	0	0	0
T163	6549	0	0	0
T190	2243	0	0	0
T191	492	0	0	0
T231	922	1	0	0
T233	3409	0	0	0
T234	9732	0	0	0
T235	523	0	0	0
T236	580	0	0	0
T237	13691	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3309	0	0
T6	3475	290	0	0
T7	33409	0	0	0
T8	686	9	0	0
T9	72485	0	0	0
T10	0	39	0	0
T36	0	82	0	0
T45	0	40	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	174	0	0
T150	0	42	0	0
T199	0	42	0	0
T219	0	43	0	0
T232	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T45	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0
T199	0	1	0	0
T219	0	1	0	0
T232	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6239436	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6241923	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	45	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T45	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0
T189	0	1	0	0
T199	0	1	0	0
T219	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	43	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T45	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0
T199	0	1	0	0
T219	0	1	0	0
T232	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T45	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0
T199	0	1	0	0
T219	0	1	0	0
T232	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	0	0	0
T10	0	1	0	0
T36	0	2	0	0
T45	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	2	0	0
T150	0	1	0	0
T199	0	1	0	0
T219	0	1	0	0
T232	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3247	0	0
T6	3475	288	0	0
T7	33409	0	0	0
T8	686	8	0	0
T9	72485	0	0	0
T10	0	37	0	0
T36	0	79	0	0
T45	0	38	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T147	0	172	0	0
T150	0	40	0	0
T199	0	40	0	0
T219	0	42	0	0
T232	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6303	0	0
T1	21527	12	0	0
T2	20722	12	0	0
T3	480	0	0	0
T4	5866	26	0	0
T5	23035	12	0	0
T13	10672	22	0	0
T14	521	4	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	4	0	0
T22	0	6	0	0
T57	0	1	0	0
T58	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	21	0	0
T8	686	1	0	0
T9	72485	0	0	0
T36	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T93	0	2	0	0
T147	0	2	0	0
T203	0	1	0	0
T213	0	1	0	0
T219	0	1	0	0
T232	0	1	0	0
T238	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T9
0	1	Covered	T37
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T9
0	1	Covered	T6,T10,T43
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T9
1	-	Covered	T6,T10,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T8,T9
DetectSt	168	Covered	T6,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T9
DebounceSt->IdleSt	163	Covered	T105,T39,T189
DetectSt->IdleSt	186	Covered	T37
DetectSt->StableSt	191	Covered	T6,T8,T9
IdleSt->DebounceSt	148	Covered	T6,T8,T9
StableSt->IdleSt	206	Covered	T6,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T8,T9
0	1	Covered	T6,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T105,T39,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T37
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T10,T43
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	127	0	0
CntIncr_A	7221089	52010	0	0
CntNoWrap_A	7221089	6526991	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	111777	0	0
DetectedPulseOut_A	7221089	59	0	0
DisabledIdleSt_A	7221089	6280270	0	0
DisabledNoDetection_A	7221089	6282756	0	0
EnterDebounceSt_A	7221089	69	0	0
EnterDetectSt_A	7221089	60	0	0
EnterStableSt_A	7221089	59	0	0
PulseIsPulse_A	7221089	59	0	0
StayInStableSt	7221089	111690	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	127	0	0
T6	3475	4	0	0
T7	33409	0	0	0
T8	686	2	0	0
T9	72485	2	0	0
T10	0	2	0	0
T34	0	2	0	0
T37	0	6	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T44	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	52010	0	0
T6	3475	92	0	0
T7	33409	0	0	0
T8	686	58	0	0
T9	72485	16	0	0
T10	0	77	0	0
T34	0	53	0	0
T37	0	91	0	0
T41	0	44	0	0
T42	0	58	0	0
T43	0	192	0	0
T44	0	33	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526991	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T33	14496	0	0	0
T37	25849	1	0	0
T102	577	0	0	0
T132	712	0	0	0
T133	812	0	0	0
T214	525	0	0	0
T215	424	0	0	0
T216	18015	0	0	0
T217	576	0	0	0
T218	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	111777	0	0
T6	3475	93	0	0
T7	33409	0	0	0
T8	686	207	0	0
T9	72485	57	0	0
T10	0	119	0	0
T34	0	183	0	0
T37	0	213	0	0
T41	0	86	0	0
T42	0	118	0	0
T43	0	370	0	0
T44	0	30	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	59	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	1	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6280270	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	3	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6282756	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	3	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	69	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	1	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	3	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	60	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	1	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	3	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	59	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	1	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	59	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	1	0	0
T9	72485	1	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	111690	0	0
T6	3475	90	0	0
T7	33409	0	0	0
T8	686	205	0	0
T9	72485	55	0	0
T10	0	118	0	0
T34	0	182	0	0
T37	0	210	0	0
T41	0	84	0	0
T42	0	115	0	0
T43	0	367	0	0
T44	0	29	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	30	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T199	0	2	0	0
T229	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T38,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T38,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T38,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T41
1	0	Covered	T1,T4,T5
1	1	Covered	T38,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T39,T164,T183
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T40
1	-	Covered	T39,T164,T183

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T38,T39,T40
DetectSt	168	Covered	T38,T39,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T38,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T40
DebounceSt->IdleSt	163	Covered	T89,T240
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T38,T39,T40
IdleSt->DebounceSt	148	Covered	T38,T39,T40
StableSt->IdleSt	206	Covered	T38,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T38,T39,T40
0	1	Covered	T38,T39,T40
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T38,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T240
DebounceSt	-	0	0	-	-	-	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T164,T183
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	78	0	0
CntIncr_A	7221089	2196	0	0
CntNoWrap_A	7221089	6527040	0	0
DetectStDropOut_A	7221089	0	0	0
DetectedOut_A	7221089	2626	0	0
DetectedPulseOut_A	7221089	38	0	0
DisabledIdleSt_A	7221089	6305298	0	0
DisabledNoDetection_A	7221089	6307781	0	0
EnterDebounceSt_A	7221089	40	0	0
EnterDetectSt_A	7221089	38	0	0
EnterStableSt_A	7221089	38	0	0
PulseIsPulse_A	7221089	38	0	0
StayInStableSt	7221089	2565	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	6279	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	78	0	0
T38	58391	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T74	496	0	0	0
T89	0	1	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	2	0	0
T183	0	4	0	0
T199	0	4	0	0
T229	0	2	0	0
T241	0	2	0	0
T242	0	4	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2196	0	0
T38	58391	45	0	0
T39	0	31	0	0
T40	0	62	0	0
T74	496	0	0	0
T89	0	34	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	20	0	0
T183	0	20	0	0
T199	0	138	0	0
T229	0	55	0	0
T241	0	100	0	0
T242	0	160	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6527040	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2626	0	0
T38	58391	40	0	0
T39	0	40	0	0
T40	0	42	0	0
T74	496	0	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	42	0	0
T183	0	101	0	0
T199	0	218	0	0
T203	0	94	0	0
T229	0	153	0	0
T241	0	40	0	0
T242	0	84	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38	0	0
T38	58391	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T74	496	0	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	1	0	0
T183	0	2	0	0
T199	0	2	0	0
T203	0	2	0	0
T229	0	1	0	0
T241	0	1	0	0
T242	0	2	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6305298	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6307781	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	40	0	0
T38	58391	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T74	496	0	0	0
T89	0	1	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	1	0	0
T183	0	2	0	0
T199	0	2	0	0
T229	0	1	0	0
T241	0	1	0	0
T242	0	2	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38	0	0
T38	58391	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T74	496	0	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	1	0	0
T183	0	2	0	0
T199	0	2	0	0
T203	0	2	0	0
T229	0	1	0	0
T241	0	1	0	0
T242	0	2	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38	0	0
T38	58391	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T74	496	0	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	1	0	0
T183	0	2	0	0
T199	0	2	0	0
T203	0	2	0	0
T229	0	1	0	0
T241	0	1	0	0
T242	0	2	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38	0	0
T38	58391	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T74	496	0	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	1	0	0
T183	0	2	0	0
T199	0	2	0	0
T203	0	2	0	0
T229	0	1	0	0
T241	0	1	0	0
T242	0	2	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2565	0	0
T38	58391	38	0	0
T39	0	39	0	0
T40	0	40	0	0
T74	496	0	0	0
T104	6327	0	0	0
T105	31185	0	0	0
T161	408	0	0	0
T162	423	0	0	0
T164	0	41	0	0
T183	0	99	0	0
T199	0	214	0	0
T203	0	91	0	0
T229	0	151	0	0
T241	0	38	0	0
T242	0	81	0	0
T243	426	0	0	0
T244	496	0	0	0
T245	402	0	0	0
T246	427	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6279	0	0
T1	21527	12	0	0
T2	20722	13	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	14	0	0
T13	10672	21	0	0
T14	521	4	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	5	0	0
T22	0	10	0	0
T57	0	4	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	14	0	0
T39	38011	1	0	0
T97	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T169	0	1	0	0
T183	0	2	0	0
T189	452157	0	0	0
T203	0	1	0	0
T242	0	1	0	0
T247	0	1	0	0
T248	0	1	0	0
T249	402	0	0	0
T250	448	0	0	0
T251	14047	0	0	0
T252	2925	0	0	0
T253	497	0	0	0
T254	567	0	0	0
T255	522	0	0	0
T256	11344	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T10,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T6,T10,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T10,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T9
1	0	Covered	T1,T4,T5
1	1	Covered	T6,T10,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T44
0	1	Covered	T257
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T44
0	1	Covered	T10,T41,T37
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T10,T44
1	-	Covered	T10,T41,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T10,T44
DetectSt	168	Covered	T6,T10,T44
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T10,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T10,T44
DebounceSt->IdleSt	163	Covered	T10,T37,T105
DetectSt->IdleSt	186	Covered	T257
DetectSt->StableSt	191	Covered	T6,T10,T44
IdleSt->DebounceSt	148	Covered	T6,T10,T44
StableSt->IdleSt	206	Covered	T6,T10,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T10,T44
0	1	Covered	T6,T10,T44
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T10,T44
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T10,T44
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T10,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T37,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T10,T44
DetectSt	-	-	-	-	1	-	-	Covered	T257
DetectSt	-	-	-	-	0	1	-	Covered	T6,T10,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T41,T37
StableSt	-	-	-	-	-	-	0	Covered	T6,T10,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	137	0	0
CntIncr_A	7221089	48598	0	0
CntNoWrap_A	7221089	6526981	0	0
DetectStDropOut_A	7221089	1	0	0
DetectedOut_A	7221089	126192	0	0
DetectedPulseOut_A	7221089	63	0	0
DisabledIdleSt_A	7221089	6307181	0	0
DisabledNoDetection_A	7221089	6309669	0	0
EnterDebounceSt_A	7221089	75	0	0
EnterDetectSt_A	7221089	64	0	0
EnterStableSt_A	7221089	63	0	0
PulseIsPulse_A	7221089	63	0	0
StayInStableSt	7221089	126105	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	137	0	0
T6	3475	2	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	3	0	0
T34	0	2	0	0
T37	0	3	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T46	0	2	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	48598	0	0
T6	3475	73	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	138	0	0
T34	0	53	0	0
T37	0	76	0	0
T38	0	89	0	0
T41	0	44	0	0
T42	0	29	0	0
T44	0	33	0	0
T46	0	69	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526981	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1	0	0
T257	822	1	0	0
T258	524	0	0	0
T259	419	0	0	0
T260	126548	0	0	0
T261	1021	0	0	0
T262	493	0	0	0
T263	27760	0	0	0
T264	676	0	0	0
T265	7184	0	0	0
T266	626	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	126192	0	0
T6	3475	291	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	223	0	0
T34	0	111	0	0
T37	0	146	0	0
T38	0	54	0	0
T41	0	1	0	0
T42	0	63	0	0
T44	0	43	0	0
T46	0	45	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	63	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6307181	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	3	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6309669	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	3	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	75	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	2	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	64	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	63	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	63	0	0
T6	3475	1	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	126105	0	0
T6	3475	289	0	0
T7	33409	0	0	0
T8	686	0	0	0
T9	72485	0	0	0
T10	0	222	0	0
T34	0	110	0	0
T37	0	145	0	0
T38	0	53	0	0
T42	0	62	0	0
T44	0	41	0	0
T46	0	43	0	0
T49	6222	0	0	0
T50	690	0	0	0
T70	540	0	0	0
T75	502	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T188	0	44	0	0
T189	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	38	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T79	502	0	0	0
T109	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T189	0	1	0	0
T199	0	2	0	0
T202	438	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T10,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T43
1	0	Covered	T1,T4,T5
1	1	Covered	T10,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T36,T37
0	1	Covered	T36,T37,T105
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T36,T37
1	-	Covered	T36,T37,T105

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T36,T37
DetectSt	168	Covered	T10,T36,T37
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T10,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T36,T37
DebounceSt->IdleSt	163	Covered	T89,T267
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T36,T37
IdleSt->DebounceSt	148	Covered	T10,T36,T37
StableSt->IdleSt	206	Covered	T10,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T36,T37
0	1	Covered	T10,T36,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T36,T37
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T267
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T105
StableSt	-	-	-	-	-	-	0	Covered	T10,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	102	0	0
CntIncr_A	7221089	37772	0	0
CntNoWrap_A	7221089	6527016	0	0
DetectStDropOut_A	7221089	0	0	0
DetectedOut_A	7221089	3381	0	0
DetectedPulseOut_A	7221089	50	0	0
DisabledIdleSt_A	7221089	6277469	0	0
DisabledNoDetection_A	7221089	6279946	0	0
EnterDebounceSt_A	7221089	52	0	0
EnterDetectSt_A	7221089	50	0	0
EnterStableSt_A	7221089	50	0	0
PulseIsPulse_A	7221089	50	0	0
StayInStableSt	7221089	3310	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7221089	7015	0	0
gen_low_level_sva.LowLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	102	0	0
T10	2446	2	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T40	0	6	0	0
T79	502	0	0	0
T105	0	2	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	2	0	0
T164	0	2	0	0
T202	438	0	0	0
T219	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	37772	0	0
T10	2446	61	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	53	0	0
T36	0	88	0	0
T37	0	76	0	0
T38	0	89	0	0
T40	0	146	0	0
T79	502	0	0	0
T105	0	49	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	81	0	0
T164	0	20	0	0
T202	438	0	0	0
T219	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6527016	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3381	0	0
T10	2446	41	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	48	0	0
T36	0	43	0	0
T37	0	94	0	0
T38	0	42	0	0
T40	0	153	0	0
T79	502	0	0	0
T105	0	93	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	195	0	0
T164	0	158	0	0
T202	438	0	0	0
T219	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	3	0	0
T79	502	0	0	0
T105	0	1	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	1	0	0
T164	0	1	0	0
T202	438	0	0	0
T219	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6277469	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6279946	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	52	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	3	0	0
T79	502	0	0	0
T105	0	1	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	1	0	0
T164	0	1	0	0
T202	438	0	0	0
T219	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	3	0	0
T79	502	0	0	0
T105	0	1	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	1	0	0
T164	0	1	0	0
T202	438	0	0	0
T219	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	3	0	0
T79	502	0	0	0
T105	0	1	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	1	0	0
T164	0	1	0	0
T202	438	0	0	0
T219	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50	0	0
T10	2446	1	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	3	0	0
T79	502	0	0	0
T105	0	1	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	1	0	0
T164	0	1	0	0
T202	438	0	0	0
T219	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	3310	0	0
T10	2446	39	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T31	14169	0	0	0
T34	0	46	0	0
T36	0	42	0	0
T37	0	91	0	0
T38	0	40	0	0
T40	0	148	0	0
T79	502	0	0	0
T105	0	92	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T150	0	193	0	0
T164	0	157	0	0
T202	438	0	0	0
T219	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	7015	0	0
T1	21527	9	0	0
T2	20722	11	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	15	0	0
T13	10672	20	0	0
T14	521	3	0	0
T15	698	3	0	0
T16	407	0	0	0
T17	509	5	0	0
T57	0	2	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	28	0	0
T36	856	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	540	0	0	0
T44	549	0	0	0
T47	7812	0	0	0
T68	1300	0	0	0
T80	5274	0	0	0
T105	0	1	0	0
T109	0	1	0	0
T164	0	1	0	0
T165	422	0	0	0
T166	654	0	0	0
T167	425	0	0	0
T168	405	0	0	0
T199	0	1	0	0
T200	0	1	0	0
T219	0	1	0	0
T229	0	1	0	0