Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T27,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T27
1	0	Covered	T27,T48,T49
1	1	Covered	T4,T13,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T27,T48
0	1	Covered	T4,T48,T49
1	0	Covered	T48,T49,T12

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T31,T47
0	1	Covered	T27,T31,T47
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T31,T47
1	-	Covered	T27,T31,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T13,T27
DetectSt	168	Covered	T4,T27,T48
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T27,T31,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T27,T48
DebounceSt->IdleSt	163	Covered	T13,T268,T269
DetectSt->IdleSt	186	Covered	T4,T48,T49
DetectSt->StableSt	191	Covered	T27,T31,T47
IdleSt->DebounceSt	148	Covered	T4,T13,T27
StableSt->IdleSt	206	Covered	T27,T31,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T13,T27
0	1	Covered	T4,T13,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T27,T48
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T13,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T27,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T268,T269
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T13,T27
DetectSt	-	-	-	-	1	-	-	Covered	T4,T48,T49
DetectSt	-	-	-	-	0	1	-	Covered	T27,T31,T47
DetectSt	-	-	-	-	0	0	-	Covered	T4,T27,T48
StableSt	-	-	-	-	-	-	1	Covered	T27,T31,T47
StableSt	-	-	-	-	-	-	0	Covered	T27,T31,T47
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	2789	0	0
CntIncr_A	7221089	105232	0	0
CntNoWrap_A	7221089	6524329	0	0
DetectStDropOut_A	7221089	375	0	0
DetectedOut_A	7221089	66677	0	0
DetectedPulseOut_A	7221089	844	0	0
DisabledIdleSt_A	7221089	6055785	0	0
DisabledNoDetection_A	7221089	6058161	0	0
EnterDebounceSt_A	7221089	1420	0	0
EnterDetectSt_A	7221089	1370	0	0
EnterStableSt_A	7221089	844	0	0
PulseIsPulse_A	7221089	844	0	0
StayInStableSt	7221089	65749	0	0
gen_high_event_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	759	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2789	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	48	0	0
T5	23035	0	0	0
T12	0	40	0	0
T13	10672	4	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	20	0	0
T31	0	50	0	0
T47	0	48	0	0
T48	0	66	0	0
T49	0	52	0	0
T57	422	0	0	0
T80	0	24	0	0
T81	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	105232	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	1561	0	0
T5	23035	0	0	0
T12	0	2671	0	0
T13	10672	744	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	490	0	0
T31	0	1550	0	0
T47	0	1272	0	0
T48	0	2050	0	0
T49	0	1291	0	0
T57	422	0	0	0
T80	0	620	0	0
T81	0	1264	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6524329	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5417	0	0
T5	23035	22591	0	0
T13	10672	10267	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	375	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	0	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T48	0	27	0	0
T49	0	6	0	0
T57	422	0	0	0
T80	0	12	0	0
T81	0	24	0	0
T103	0	16	0	0
T104	0	12	0	0
T107	0	4	0	0
T108	0	24	0	0
T270	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66677	0	0
T23	494	0	0	0
T25	2370	0	0	0
T26	724	0	0	0
T27	13360	498	0	0
T31	0	1783	0	0
T33	0	1907	0	0
T47	0	1884	0	0
T48	15670	0	0	0
T60	1591	0	0	0
T61	444	0	0	0
T62	446	0	0	0
T65	548	0	0	0
T69	402	0	0	0
T131	0	2325	0	0
T151	0	1521	0	0
T152	0	413	0	0
T216	0	748	0	0
T271	0	346	0	0
T272	0	78	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	844	0	0
T23	494	0	0	0
T25	2370	0	0	0
T26	724	0	0	0
T27	13360	10	0	0
T31	0	25	0	0
T33	0	25	0	0
T47	0	24	0	0
T48	15670	0	0	0
T60	1591	0	0	0
T61	444	0	0	0
T62	446	0	0	0
T65	548	0	0	0
T69	402	0	0	0
T131	0	25	0	0
T151	0	13	0	0
T152	0	11	0	0
T216	0	12	0	0
T271	0	9	0	0
T272	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6055785	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	2014	0	0
T5	23035	22591	0	0
T13	10672	2015	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6058161	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	2014	0	0
T5	23035	22599	0	0
T13	10672	2015	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1420	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	0	0	0
T12	0	20	0	0
T13	10672	4	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	10	0	0
T31	0	25	0	0
T47	0	24	0	0
T48	0	33	0	0
T49	0	26	0	0
T57	422	0	0	0
T80	0	12	0	0
T81	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1370	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	0	0	0
T12	0	20	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	10	0	0
T31	0	25	0	0
T47	0	24	0	0
T48	0	33	0	0
T49	0	26	0	0
T57	422	0	0	0
T80	0	12	0	0
T81	0	24	0	0
T131	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	844	0	0
T23	494	0	0	0
T25	2370	0	0	0
T26	724	0	0	0
T27	13360	10	0	0
T31	0	25	0	0
T33	0	25	0	0
T47	0	24	0	0
T48	15670	0	0	0
T60	1591	0	0	0
T61	444	0	0	0
T62	446	0	0	0
T65	548	0	0	0
T69	402	0	0	0
T131	0	25	0	0
T151	0	13	0	0
T152	0	11	0	0
T216	0	12	0	0
T271	0	9	0	0
T272	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	844	0	0
T23	494	0	0	0
T25	2370	0	0	0
T26	724	0	0	0
T27	13360	10	0	0
T31	0	25	0	0
T33	0	25	0	0
T47	0	24	0	0
T48	15670	0	0	0
T60	1591	0	0	0
T61	444	0	0	0
T62	446	0	0	0
T65	548	0	0	0
T69	402	0	0	0
T131	0	25	0	0
T151	0	13	0	0
T152	0	11	0	0
T216	0	12	0	0
T271	0	9	0	0
T272	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	65749	0	0
T23	494	0	0	0
T25	2370	0	0	0
T26	724	0	0	0
T27	13360	486	0	0
T31	0	1756	0	0
T33	0	1880	0	0
T47	0	1860	0	0
T48	15670	0	0	0
T60	1591	0	0	0
T61	444	0	0	0
T62	446	0	0	0
T65	548	0	0	0
T69	402	0	0	0
T131	0	2297	0	0
T151	0	1499	0	0
T152	0	402	0	0
T216	0	735	0	0
T271	0	337	0	0
T272	0	76	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	759	0	0
T23	494	0	0	0
T25	2370	0	0	0
T26	724	0	0	0
T27	13360	8	0	0
T31	0	23	0	0
T33	0	23	0	0
T47	0	24	0	0
T48	15670	0	0	0
T60	1591	0	0	0
T61	444	0	0	0
T62	446	0	0	0
T65	548	0	0	0
T69	402	0	0	0
T131	0	22	0	0
T151	0	4	0	0
T152	0	11	0	0
T216	0	11	0	0
T268	0	2	0	0
T271	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T5,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T5,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T52,T88,T105
1	0	Covered	T89,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
1	0	Covered	T92

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T2
1	-	Covered	T1,T5,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T2
DetectSt	168	Covered	T1,T5,T2
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T5,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T2
DebounceSt->IdleSt	163	Covered	T6,T9,T10
DetectSt->IdleSt	186	Covered	T52,T88,T105
DetectSt->StableSt	191	Covered	T1,T5,T2
IdleSt->DebounceSt	148	Covered	T1,T5,T2
StableSt->IdleSt	206	Covered	T1,T5,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T9,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	1	-	-	Covered	T52,T88,T105
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	1029	0	0
CntIncr_A	7221089	60305	0	0
CntNoWrap_A	7221089	6526089	0	0
DetectStDropOut_A	7221089	49	0	0
DetectedOut_A	7221089	15105	0	0
DetectedPulseOut_A	7221089	417	0	0
DisabledIdleSt_A	7221089	6116690	0	0
DisabledNoDetection_A	7221089	6118412	0	0
EnterDebounceSt_A	7221089	561	0	0
EnterDetectSt_A	7221089	469	0	0
EnterStableSt_A	7221089	417	0	0
PulseIsPulse_A	7221089	417	0	0
StayInStableSt	7221089	14662	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	387	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1029	0	0
T1	21527	14	0	0
T2	20722	4	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	14	0	0
T6	0	1	0	0
T7	0	10	0	0
T9	0	1	0	0
T10	0	1	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	4	0	0
T31	0	4	0	0
T52	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	60305	0	0
T1	21527	959	0	0
T2	20722	296	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	1029	0	0
T6	0	20	0	0
T7	0	840	0	0
T9	0	20	0	0
T10	0	20	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	156	0	0
T31	0	90	0	0
T52	0	274	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526089	0	0
T1	21527	21060	0	0
T2	20722	20267	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22577	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	49	0	0
T10	2446	0	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T52	20491	2	0	0
T79	502	0	0	0
T88	0	9	0	0
T105	0	3	0	0
T106	0	4	0	0
T109	0	1	0	0
T110	0	4	0	0
T111	0	10	0	0
T113	0	2	0	0
T114	0	3	0	0
T115	0	2	0	0
T117	421	0	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	15105	0	0
T1	21527	189	0	0
T2	20722	23	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	68	0	0
T7	0	26	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	110	0	0
T31	0	168	0	0
T35	0	851	0	0
T47	0	47	0	0
T129	0	78	0	0
T130	0	150	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	417	0	0
T1	21527	7	0	0
T2	20722	2	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	5	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	2	0	0
T31	0	2	0	0
T35	0	7	0	0
T47	0	1	0	0
T129	0	2	0	0
T130	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6116690	0	0
T1	21527	16117	0	0
T2	20722	16117	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	16117	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6118412	0	0
T1	21527	16117	0	0
T2	20722	16117	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	16117	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	561	0	0
T1	21527	7	0	0
T2	20722	2	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T6	0	1	0	0
T7	0	5	0	0
T9	0	1	0	0
T10	0	1	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	2	0	0
T31	0	2	0	0
T52	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	469	0	0
T1	21527	7	0	0
T2	20722	2	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	5	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	2	0	0
T31	0	2	0	0
T35	0	7	0	0
T52	0	2	0	0
T129	0	2	0	0
T130	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	417	0	0
T1	21527	7	0	0
T2	20722	2	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	5	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	2	0	0
T31	0	2	0	0
T35	0	7	0	0
T47	0	1	0	0
T129	0	2	0	0
T130	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	417	0	0
T1	21527	7	0	0
T2	20722	2	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	5	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	2	0	0
T31	0	2	0	0
T35	0	7	0	0
T47	0	1	0	0
T129	0	2	0	0
T130	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	14662	0	0
T1	21527	182	0	0
T2	20722	21	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	61	0	0
T7	0	21	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	106	0	0
T31	0	166	0	0
T35	0	844	0	0
T47	0	46	0	0
T129	0	76	0	0
T130	0	148	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	387	0	0
T1	21527	7	0	0
T2	20722	2	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	5	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	2	0	0
T35	0	7	0	0
T47	0	1	0	0
T129	0	2	0	0
T130	0	2	0	0
T135	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T27
1	0	Covered	T27,T48,T49
1	1	Covered	T4,T13,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T27
0	1	Covered	T4,T49,T80
1	0	Covered	T49,T31,T103

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T48
0	1	Covered	T13,T27,T48
1	0	Covered	T89,T63,T273

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T27,T48
1	-	Covered	T13,T27,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T13,T27
DetectSt	168	Covered	T4,T13,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T13,T27,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T13,T27
DebounceSt->IdleSt	163	Covered	T13,T268,T269
DetectSt->IdleSt	186	Covered	T4,T49,T31
DetectSt->StableSt	191	Covered	T13,T27,T48
IdleSt->DebounceSt	148	Covered	T4,T13,T27
StableSt->IdleSt	206	Covered	T13,T27,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T13,T27
0	1	Covered	T4,T13,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T13,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T13,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T268,T269
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T13,T27
DetectSt	-	-	-	-	1	-	-	Covered	T4,T49,T31
DetectSt	-	-	-	-	0	1	-	Covered	T13,T27,T48
DetectSt	-	-	-	-	0	0	-	Covered	T4,T13,T27
StableSt	-	-	-	-	-	-	1	Covered	T13,T27,T48
StableSt	-	-	-	-	-	-	0	Covered	T13,T27,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	2659	0	0
CntIncr_A	7221089	100169	0	0
CntNoWrap_A	7221089	6524459	0	0
DetectStDropOut_A	7221089	257	0	0
DetectedOut_A	7221089	88672	0	0
DetectedPulseOut_A	7221089	911	0	0
DisabledIdleSt_A	7221089	6039159	0	0
DisabledNoDetection_A	7221089	6041503	0	0
EnterDebounceSt_A	7221089	1356	0	0
EnterDetectSt_A	7221089	1305	0	0
EnterStableSt_A	7221089	911	0	0
PulseIsPulse_A	7221089	911	0	0
StayInStableSt	7221089	87645	0	0
gen_high_event_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	787	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2659	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	26	0	0
T5	23035	0	0	0
T12	0	58	0	0
T13	10672	19	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	30	0	0
T31	0	20	0	0
T47	0	12	0	0
T48	0	22	0	0
T49	0	48	0	0
T57	422	0	0	0
T80	0	22	0	0
T81	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	100169	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	836	0	0
T5	23035	0	0	0
T12	0	2001	0	0
T13	10672	3022	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	720	0	0
T31	0	728	0	0
T47	0	354	0	0
T48	0	473	0	0
T49	0	1194	0	0
T57	422	0	0	0
T80	0	568	0	0
T81	0	735	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6524459	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5439	0	0
T5	23035	22591	0	0
T13	10672	10252	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	257	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	13	0	0
T5	23035	0	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T49	0	6	0	0
T57	422	0	0	0
T80	0	11	0	0
T81	0	14	0	0
T107	0	10	0	0
T108	0	24	0	0
T151	0	2	0	0
T270	0	23	0	0
T274	0	6	0	0
T275	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	88672	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	2531	0	0
T13	10672	451	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	1517	0	0
T33	0	590	0	0
T47	0	123	0	0
T48	0	2064	0	0
T57	422	0	0	0
T58	426	0	0	0
T104	0	895	0	0
T131	0	1740	0	0
T216	0	1143	0	0
T271	0	2382	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	911	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	29	0	0
T13	10672	5	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	15	0	0
T33	0	15	0	0
T47	0	6	0	0
T48	0	11	0	0
T57	422	0	0	0
T58	426	0	0	0
T104	0	7	0	0
T131	0	29	0	0
T216	0	22	0	0
T271	0	34	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6039159	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	2014	0	0
T5	23035	22591	0	0
T13	10672	2015	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6041503	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	2014	0	0
T5	23035	22599	0	0
T13	10672	2015	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1356	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	13	0	0
T5	23035	0	0	0
T12	0	29	0	0
T13	10672	15	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	15	0	0
T31	0	10	0	0
T47	0	6	0	0
T48	0	11	0	0
T49	0	24	0	0
T57	422	0	0	0
T80	0	11	0	0
T81	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1305	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	13	0	0
T5	23035	0	0	0
T12	0	29	0	0
T13	10672	5	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	15	0	0
T31	0	10	0	0
T47	0	6	0	0
T48	0	11	0	0
T49	0	24	0	0
T57	422	0	0	0
T80	0	11	0	0
T81	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	911	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	29	0	0
T13	10672	5	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	15	0	0
T33	0	15	0	0
T47	0	6	0	0
T48	0	11	0	0
T57	422	0	0	0
T58	426	0	0	0
T104	0	7	0	0
T131	0	29	0	0
T216	0	22	0	0
T271	0	34	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	911	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	29	0	0
T13	10672	5	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	15	0	0
T33	0	15	0	0
T47	0	6	0	0
T48	0	11	0	0
T57	422	0	0	0
T58	426	0	0	0
T104	0	7	0	0
T131	0	29	0	0
T216	0	22	0	0
T271	0	34	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	87645	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	2498	0	0
T13	10672	446	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	1501	0	0
T33	0	575	0	0
T47	0	117	0	0
T48	0	2049	0	0
T57	422	0	0	0
T58	426	0	0	0
T104	0	888	0	0
T131	0	1708	0	0
T216	0	1119	0	0
T271	0	2345	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	787	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	25	0	0
T13	10672	5	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	14	0	0
T33	0	15	0	0
T47	0	6	0	0
T48	0	7	0	0
T57	422	0	0	0
T58	426	0	0	0
T104	0	7	0	0
T131	0	26	0	0
T216	0	20	0	0
T271	0	31	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T2,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T5,T2,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T2,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T13,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T2,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T27
0	1	Covered	T37,T88,T276
1	0	Covered	T89,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T2,T27
0	1	Covered	T5,T2,T7
1	0	Covered	T90,T89,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T2,T27
1	-	Covered	T5,T2,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T2,T27
DetectSt	168	Covered	T5,T2,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T5,T2,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T2,T27
DebounceSt->IdleSt	163	Covered	T5,T48,T7
DetectSt->IdleSt	186	Covered	T37,T88,T276
DetectSt->StableSt	191	Covered	T5,T2,T27
IdleSt->DebounceSt	148	Covered	T5,T2,T27
StableSt->IdleSt	206	Covered	T5,T2,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T2,T27
0	1	Covered	T5,T2,T27
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T2,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T2,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T2,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T48,T7
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T2,T27
DetectSt	-	-	-	-	1	-	-	Covered	T37,T88,T276
DetectSt	-	-	-	-	0	1	-	Covered	T5,T2,T27
DetectSt	-	-	-	-	0	0	-	Covered	T5,T2,T27
StableSt	-	-	-	-	-	-	1	Covered	T5,T2,T7
StableSt	-	-	-	-	-	-	0	Covered	T5,T2,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	891	0	0
CntIncr_A	7221089	50372	0	0
CntNoWrap_A	7221089	6526227	0	0
DetectStDropOut_A	7221089	42	0	0
DetectedOut_A	7221089	18198	0	0
DetectedPulseOut_A	7221089	375	0	0
DisabledIdleSt_A	7221089	6105416	0	0
DisabledNoDetection_A	7221089	6107193	0	0
EnterDebounceSt_A	7221089	471	0	0
EnterDetectSt_A	7221089	420	0	0
EnterStableSt_A	7221089	375	0	0
PulseIsPulse_A	7221089	375	0	0
StayInStableSt	7221089	17792	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	337	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	891	0	0
T2	20722	4	0	0
T3	480	0	0	0
T5	23035	3	0	0
T7	0	13	0	0
T12	0	6	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	2	0	0
T35	0	15	0	0
T48	0	9	0	0
T52	0	2	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	13	0	0
T130	0	21	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	50372	0	0
T2	20722	224	0	0
T3	480	0	0	0
T5	23035	254	0	0
T7	0	627	0	0
T12	0	279	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	52	0	0
T35	0	1037	0	0
T48	0	300	0	0
T52	0	121	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	763	0	0
T130	0	1683	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526227	0	0
T1	21527	21074	0	0
T2	20722	20267	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22588	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	42	0	0
T33	14496	0	0	0
T37	25849	9	0	0
T88	0	4	0	0
T89	0	1	0	0
T97	0	4	0	0
T102	577	0	0	0
T132	712	0	0	0
T133	812	0	0	0
T214	525	0	0	0
T215	424	0	0	0
T216	18015	0	0	0
T217	576	0	0	0
T218	427	0	0	0
T276	0	3	0	0
T277	0	1	0	0
T278	0	7	0	0
T279	0	1	0	0
T280	0	6	0	0
T281	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	18198	0	0
T2	20722	95	0	0
T3	480	0	0	0
T5	23035	5	0	0
T7	0	488	0	0
T12	0	141	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	81	0	0
T35	0	925	0	0
T48	0	242	0	0
T52	0	16	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	512	0	0
T130	0	348	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	375	0	0
T2	20722	2	0	0
T3	480	0	0	0
T5	23035	1	0	0
T7	0	6	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	1	0	0
T35	0	7	0	0
T48	0	4	0	0
T52	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	6	0	0
T130	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6105416	0	0
T1	21527	21074	0	0
T2	20722	16117	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	16117	0	0
T13	10672	9820	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6107193	0	0
T1	21527	21082	0	0
T2	20722	16117	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	16117	0	0
T13	10672	9821	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	471	0	0
T2	20722	2	0	0
T3	480	0	0	0
T5	23035	2	0	0
T7	0	7	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	1	0	0
T35	0	8	0	0
T48	0	5	0	0
T52	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	7	0	0
T130	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	420	0	0
T2	20722	2	0	0
T3	480	0	0	0
T5	23035	1	0	0
T7	0	6	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	1	0	0
T35	0	7	0	0
T48	0	4	0	0
T52	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	6	0	0
T130	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	375	0	0
T2	20722	2	0	0
T3	480	0	0	0
T5	23035	1	0	0
T7	0	6	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	1	0	0
T35	0	7	0	0
T48	0	4	0	0
T52	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	6	0	0
T130	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	375	0	0
T2	20722	2	0	0
T3	480	0	0	0
T5	23035	1	0	0
T7	0	6	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	1	0	0
T35	0	7	0	0
T48	0	4	0	0
T52	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	6	0	0
T130	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	17792	0	0
T2	20722	93	0	0
T3	480	0	0	0
T5	23035	4	0	0
T7	0	482	0	0
T12	0	135	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	79	0	0
T35	0	918	0	0
T48	0	234	0	0
T52	0	15	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	506	0	0
T130	0	339	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	337	0	0
T2	20722	2	0	0
T3	480	0	0	0
T5	23035	1	0	0
T7	0	6	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T32	0	3	0	0
T33	0	1	0	0
T35	0	7	0	0
T52	0	1	0	0
T57	422	0	0	0
T58	426	0	0	0
T129	0	6	0	0
T130	0	9	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T27
1	0	Covered	T27,T48,T49
1	1	Covered	T4,T13,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T13,T27
0	1	Covered	T4,T48,T80
1	0	Covered	T48,T282,T283

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T49
0	1	Covered	T13,T27,T49
1	0	Covered	T284,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T27,T49
1	-	Covered	T13,T27,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T13,T27
DetectSt	168	Covered	T4,T13,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T13,T27,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T13,T27
DebounceSt->IdleSt	163	Covered	T13,T268,T269
DetectSt->IdleSt	186	Covered	T4,T48,T80
DetectSt->StableSt	191	Covered	T13,T27,T49
IdleSt->DebounceSt	148	Covered	T4,T13,T27
StableSt->IdleSt	206	Covered	T13,T27,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T13,T27
0	1	Covered	T4,T13,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T13,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T13,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T268,T269
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T13,T27
DetectSt	-	-	-	-	1	-	-	Covered	T4,T48,T80
DetectSt	-	-	-	-	0	1	-	Covered	T13,T27,T49
DetectSt	-	-	-	-	0	0	-	Covered	T4,T13,T27
StableSt	-	-	-	-	-	-	1	Covered	T13,T27,T49
StableSt	-	-	-	-	-	-	0	Covered	T13,T27,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	2986	0	0
CntIncr_A	7221089	114018	0	0
CntNoWrap_A	7221089	6524132	0	0
DetectStDropOut_A	7221089	333	0	0
DetectedOut_A	7221089	81704	0	0
DetectedPulseOut_A	7221089	1009	0	0
DisabledIdleSt_A	7221089	6045730	0	0
DisabledNoDetection_A	7221089	6048090	0	0
EnterDebounceSt_A	7221089	1526	0	0
EnterDetectSt_A	7221089	1463	0	0
EnterStableSt_A	7221089	1009	0	0
PulseIsPulse_A	7221089	1009	0	0
StayInStableSt	7221089	80595	0	0
gen_high_event_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	903	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2986	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	26	0	0
T5	23035	0	0	0
T12	0	22	0	0
T13	10672	6	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	24	0	0
T31	0	48	0	0
T47	0	16	0	0
T48	0	42	0	0
T49	0	48	0	0
T57	422	0	0	0
T80	0	42	0	0
T81	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	114018	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	836	0	0
T5	23035	0	0	0
T12	0	1045	0	0
T13	10672	1111	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	360	0	0
T31	0	1080	0	0
T47	0	312	0	0
T48	0	1301	0	0
T49	0	600	0	0
T57	422	0	0	0
T80	0	1091	0	0
T81	0	629	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6524132	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5439	0	0
T5	23035	22591	0	0
T13	10672	10265	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	333	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	13	0	0
T5	23035	0	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T48	0	18	0	0
T57	422	0	0	0
T80	0	21	0	0
T81	0	12	0	0
T90	0	8	0	0
T108	0	18	0	0
T270	0	2	0	0
T275	0	32	0	0
T283	0	2	0	0
T285	0	20	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	81704	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	905	0	0
T13	10672	126	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	340	0	0
T31	0	2173	0	0
T33	0	800	0	0
T47	0	322	0	0
T49	0	645	0	0
T57	422	0	0	0
T58	426	0	0	0
T103	0	2320	0	0
T131	0	1307	0	0
T271	0	2960	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1009	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	11	0	0
T13	10672	1	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	12	0	0
T31	0	24	0	0
T33	0	28	0	0
T47	0	8	0	0
T49	0	24	0	0
T57	422	0	0	0
T58	426	0	0	0
T103	0	25	0	0
T131	0	25	0	0
T271	0	34	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6045730	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	2014	0	0
T5	23035	22591	0	0
T13	10672	2015	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6048090	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	2014	0	0
T5	23035	22599	0	0
T13	10672	2015	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1526	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	13	0	0
T5	23035	0	0	0
T12	0	11	0	0
T13	10672	6	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	12	0	0
T31	0	24	0	0
T47	0	8	0	0
T48	0	21	0	0
T49	0	24	0	0
T57	422	0	0	0
T80	0	21	0	0
T81	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1463	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	13	0	0
T5	23035	0	0	0
T12	0	11	0	0
T13	10672	1	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	12	0	0
T31	0	24	0	0
T47	0	8	0	0
T48	0	21	0	0
T49	0	24	0	0
T57	422	0	0	0
T80	0	21	0	0
T81	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1009	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	11	0	0
T13	10672	1	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	12	0	0
T31	0	24	0	0
T33	0	28	0	0
T47	0	8	0	0
T49	0	24	0	0
T57	422	0	0	0
T58	426	0	0	0
T103	0	25	0	0
T131	0	25	0	0
T271	0	34	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1009	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	11	0	0
T13	10672	1	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	12	0	0
T31	0	24	0	0
T33	0	28	0	0
T47	0	8	0	0
T49	0	24	0	0
T57	422	0	0	0
T58	426	0	0	0
T103	0	25	0	0
T131	0	25	0	0
T271	0	34	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	80595	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	891	0	0
T13	10672	125	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	328	0	0
T31	0	2148	0	0
T33	0	769	0	0
T47	0	314	0	0
T49	0	621	0	0
T57	422	0	0	0
T58	426	0	0	0
T103	0	2290	0	0
T131	0	1280	0	0
T271	0	2923	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	903	0	0
T2	20722	0	0	0
T3	480	0	0	0
T12	0	8	0	0
T13	10672	1	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T27	0	12	0	0
T31	0	23	0	0
T33	0	25	0	0
T47	0	8	0	0
T49	0	24	0	0
T57	422	0	0	0
T58	426	0	0	0
T103	0	20	0	0
T131	0	23	0	0
T271	0	31	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T5,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T5,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T52,T34,T276
1	0	Covered	T89,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
1	0	Covered	T91,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T5,T2
1	-	Covered	T1,T5,T2

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T2
DetectSt	168	Covered	T1,T5,T2
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T5,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T5,T2
DebounceSt->IdleSt	163	Covered	T2,T31,T35
DetectSt->IdleSt	186	Covered	T52,T34,T276
DetectSt->StableSt	191	Covered	T1,T5,T2
IdleSt->DebounceSt	148	Covered	T1,T5,T2
StableSt->IdleSt	206	Covered	T1,T5,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T5,T2
0	1	Covered	T1,T5,T2
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T2
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T2
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T5,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T31,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	1	-	-	Covered	T52,T34,T276
DetectSt	-	-	-	-	0	1	-	Covered	T1,T5,T2
DetectSt	-	-	-	-	0	0	-	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T5,T2
StableSt	-	-	-	-	-	-	0	Covered	T1,T5,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	967	0	0
CntIncr_A	7221089	61769	0	0
CntNoWrap_A	7221089	6526151	0	0
DetectStDropOut_A	7221089	75	0	0
DetectedOut_A	7221089	16684	0	0
DetectedPulseOut_A	7221089	382	0	0
DisabledIdleSt_A	7221089	6107635	0	0
DisabledNoDetection_A	7221089	6109430	0	0
EnterDebounceSt_A	7221089	507	0	0
EnterDetectSt_A	7221089	460	0	0
EnterStableSt_A	7221089	382	0	0
PulseIsPulse_A	7221089	382	0	0
StayInStableSt	7221089	16278	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	351	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	967	0	0
T1	21527	12	0	0
T2	20722	9	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	14	0	0
T7	0	8	0	0
T12	0	6	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	3	0	0
T35	0	11	0	0
T52	0	2	0	0
T129	0	11	0	0
T130	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	61769	0	0
T1	21527	930	0	0
T2	20722	529	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	840	0	0
T7	0	480	0	0
T12	0	264	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	112	0	0
T35	0	1059	0	0
T52	0	137	0	0
T129	0	1043	0	0
T130	0	935	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526151	0	0
T1	21527	21062	0	0
T2	20722	20262	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22577	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	75	0	0
T10	2446	0	0	0
T11	5200	0	0	0
T12	26049	0	0	0
T24	496	0	0	0
T34	0	4	0	0
T52	20491	1	0	0
T79	502	0	0	0
T89	0	1	0	0
T93	0	4	0	0
T110	0	4	0	0
T117	421	0	0	0
T118	426	0	0	0
T119	452	0	0	0
T120	710	0	0	0
T139	0	6	0	0
T276	0	11	0	0
T279	0	13	0	0
T286	0	3	0	0
T287	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	16684	0	0
T1	21527	54	0	0
T2	20722	157	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	257	0	0
T7	0	213	0	0
T12	0	162	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	49	0	0
T35	0	368	0	0
T129	0	34	0	0
T130	0	28	0	0
T135	0	247	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	382	0	0
T1	21527	6	0	0
T2	20722	4	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	4	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	1	0	0
T35	0	5	0	0
T129	0	5	0	0
T130	0	5	0	0
T135	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6107635	0	0
T1	21527	16117	0	0
T2	20722	16117	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	16117	0	0
T13	10672	10145	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6109430	0	0
T1	21527	16117	0	0
T2	20722	16117	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	16117	0	0
T13	10672	10146	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	507	0	0
T1	21527	6	0	0
T2	20722	5	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	4	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	2	0	0
T35	0	6	0	0
T52	0	1	0	0
T129	0	6	0	0
T130	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	460	0	0
T1	21527	6	0	0
T2	20722	4	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	4	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	1	0	0
T35	0	5	0	0
T52	0	1	0	0
T129	0	5	0	0
T130	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	382	0	0
T1	21527	6	0	0
T2	20722	4	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	4	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	1	0	0
T35	0	5	0	0
T129	0	5	0	0
T130	0	5	0	0
T135	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	382	0	0
T1	21527	6	0	0
T2	20722	4	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	4	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	1	0	0
T35	0	5	0	0
T129	0	5	0	0
T130	0	5	0	0
T135	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	16278	0	0
T1	21527	48	0	0
T2	20722	153	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	250	0	0
T7	0	209	0	0
T12	0	159	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	48	0	0
T35	0	363	0	0
T129	0	29	0	0
T130	0	23	0	0
T135	0	243	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	351	0	0
T1	21527	6	0	0
T2	20722	4	0	0
T3	480	0	0	0
T4	5866	0	0	0
T5	23035	7	0	0
T7	0	4	0	0
T12	0	3	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T31	0	1	0	0
T35	0	5	0	0
T129	0	5	0	0
T130	0	5	0	0
T135	0	4	0	0