Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T27,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T27
1	0	Covered	T27,T48,T49
1	1	Covered	T4,T13,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T27,T48
0	1	Covered	T4,T27,T48
1	0	Covered	T27,T48,T104

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T12,T31
0	1	Covered	T49,T12,T31
1	0	Covered	T94,T95,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T12,T31
1	-	Covered	T49,T12,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T13,T27
DetectSt	168	Covered	T4,T27,T48
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T49,T12,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T27,T48
DebounceSt->IdleSt	163	Covered	T13,T268,T269
DetectSt->IdleSt	186	Covered	T4,T27,T48
DetectSt->StableSt	191	Covered	T49,T12,T31
IdleSt->DebounceSt	148	Covered	T4,T13,T27
StableSt->IdleSt	206	Covered	T49,T12,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T13,T27
0	1	Covered	T4,T13,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T27,T48
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T13,T27
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T27,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T268,T269
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T13,T27
DetectSt	-	-	-	-	1	-	-	Covered	T4,T27,T48
DetectSt	-	-	-	-	0	1	-	Covered	T49,T12,T31
DetectSt	-	-	-	-	0	0	-	Covered	T4,T27,T48
StableSt	-	-	-	-	-	-	1	Covered	T49,T12,T31
StableSt	-	-	-	-	-	-	0	Covered	T49,T12,T31
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	2909	0	0
CntIncr_A	7221089	104397	0	0
CntNoWrap_A	7221089	6524209	0	0
DetectStDropOut_A	7221089	424	0	0
DetectedOut_A	7221089	66994	0	0
DetectedPulseOut_A	7221089	893	0	0
DisabledIdleSt_A	7221089	6056953	0	0
DisabledNoDetection_A	7221089	6059321	0	0
EnterDebounceSt_A	7221089	1485	0	0
EnterDetectSt_A	7221089	1426	0	0
EnterStableSt_A	7221089	893	0	0
PulseIsPulse_A	7221089	893	0	0
StayInStableSt	7221089	66009	0	0
gen_high_event_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	785	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	2909	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	48	0	0
T5	23035	0	0	0
T12	0	54	0	0
T13	10672	2	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	62	0	0
T31	0	46	0	0
T47	0	26	0	0
T48	0	50	0	0
T49	0	42	0	0
T57	422	0	0	0
T80	0	60	0	0
T81	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	104397	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	1561	0	0
T5	23035	0	0	0
T12	0	2295	0	0
T13	10672	372	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	1759	0	0
T31	0	1656	0	0
T47	0	1001	0	0
T48	0	1566	0	0
T49	0	693	0	0
T57	422	0	0	0
T80	0	1563	0	0
T81	0	1114	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6524209	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	5417	0	0
T5	23035	22591	0	0
T13	10672	10269	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	424	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	0	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	9	0	0
T48	0	14	0	0
T57	422	0	0	0
T80	0	30	0	0
T81	0	21	0	0
T104	0	1	0	0
T107	0	20	0	0
T108	0	24	0	0
T151	0	7	0	0
T274	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66994	0	0
T12	0	3558	0	0
T31	0	202	0	0
T33	0	1248	0	0
T47	0	30	0	0
T49	6222	1408	0	0
T51	692	0	0	0
T52	20491	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T78	525	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T103	0	2345	0	0
T131	0	682	0	0
T216	0	248	0	0
T271	0	349	0	0
T288	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	893	0	0
T12	0	27	0	0
T31	0	23	0	0
T33	0	28	0	0
T47	0	13	0	0
T49	6222	21	0	0
T51	692	0	0	0
T52	20491	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T78	525	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T103	0	25	0	0
T131	0	25	0	0
T216	0	6	0	0
T271	0	11	0	0
T288	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6056953	0	0
T1	21527	21074	0	0
T2	20722	20271	0	0
T3	480	79	0	0
T4	5866	2014	0	0
T5	23035	22591	0	0
T13	10672	2015	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6059321	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	2014	0	0
T5	23035	22599	0	0
T13	10672	2015	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1485	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	0	0	0
T12	0	27	0	0
T13	10672	2	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	31	0	0
T31	0	23	0	0
T47	0	13	0	0
T48	0	25	0	0
T49	0	21	0	0
T57	422	0	0	0
T80	0	30	0	0
T81	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	1426	0	0
T2	20722	0	0	0
T3	480	0	0	0
T4	5866	24	0	0
T5	23035	0	0	0
T12	0	27	0	0
T13	10672	0	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T27	0	31	0	0
T31	0	23	0	0
T47	0	13	0	0
T48	0	25	0	0
T49	0	21	0	0
T57	422	0	0	0
T80	0	30	0	0
T81	0	21	0	0
T131	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	893	0	0
T12	0	27	0	0
T31	0	23	0	0
T33	0	28	0	0
T47	0	13	0	0
T49	6222	21	0	0
T51	692	0	0	0
T52	20491	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T78	525	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T103	0	25	0	0
T131	0	25	0	0
T216	0	6	0	0
T271	0	11	0	0
T288	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	893	0	0
T12	0	27	0	0
T31	0	23	0	0
T33	0	28	0	0
T47	0	13	0	0
T49	6222	21	0	0
T51	692	0	0	0
T52	20491	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T78	525	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T103	0	25	0	0
T131	0	25	0	0
T216	0	6	0	0
T271	0	11	0	0
T288	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	66009	0	0
T12	0	3526	0	0
T31	0	178	0	0
T33	0	1217	0	0
T47	0	17	0	0
T49	6222	1387	0	0
T51	692	0	0	0
T52	20491	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T78	525	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T103	0	2315	0	0
T131	0	655	0	0
T216	0	241	0	0
T271	0	338	0	0
T288	0	158	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	785	0	0
T12	0	22	0	0
T31	0	22	0	0
T33	0	25	0	0
T47	0	13	0	0
T49	6222	21	0	0
T51	692	0	0	0
T52	20491	0	0	0
T75	502	0	0	0
T76	509	0	0	0
T77	522	0	0	0
T78	525	0	0	0
T85	703	0	0	0
T86	423	0	0	0
T87	426	0	0	0
T103	0	20	0	0
T131	0	23	0	0
T216	0	5	0	0
T271	0	11	0	0
T288	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T13
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T7,T52

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T2,T7,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T52
0	1	Covered	T32,T37,T45
1	0	Covered	T89,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T52
0	1	Covered	T2,T7,T52
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T52
1	-	Covered	T2,T7,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T52
DetectSt	168	Covered	T2,T7,T52
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T52
DebounceSt->IdleSt	163	Covered	T7,T35,T34
DetectSt->IdleSt	186	Covered	T32,T37,T45
DetectSt->StableSt	191	Covered	T2,T7,T52
IdleSt->DebounceSt	148	Covered	T2,T7,T52
StableSt->IdleSt	206	Covered	T2,T7,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T52
0	1	Covered	T2,T7,T52
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T52
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T52
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T89,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T35,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T52
DetectSt	-	-	-	-	1	-	-	Covered	T32,T37,T45
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T52
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T52
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T52
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7221089	914	0	0
CntIncr_A	7221089	59668	0	0
CntNoWrap_A	7221089	6526204	0	0
DetectStDropOut_A	7221089	68	0	0
DetectedOut_A	7221089	14589	0	0
DetectedPulseOut_A	7221089	363	0	0
DisabledIdleSt_A	7221089	6133206	0	0
DisabledNoDetection_A	7221089	6135012	0	0
EnterDebounceSt_A	7221089	480	0	0
EnterDetectSt_A	7221089	434	0	0
EnterStableSt_A	7221089	363	0	0
PulseIsPulse_A	7221089	363	0	0
StayInStableSt	7221089	14207	0	0
gen_high_level_sva.HighLevelEvent_A	7221089	6529666	0	0
gen_not_sticky_sva.StableStDropOut_A	7221089	343	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	914	0	0
T2	20722	6	0	0
T3	480	0	0	0
T7	0	14	0	0
T12	0	8	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	2	0	0
T32	0	6	0	0
T35	0	20	0	0
T52	0	12	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	10	0	0
T130	0	10	0	0
T135	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	59668	0	0
T2	20722	441	0	0
T3	480	0	0	0
T7	0	780	0	0
T12	0	372	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	77	0	0
T32	0	307	0	0
T35	0	2547	0	0
T52	0	708	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	425	0	0
T130	0	770	0	0
T135	0	2178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6526204	0	0
T1	21527	21074	0	0
T2	20722	20265	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	68	0	0
T32	14733	3	0	0
T37	25849	6	0	0
T45	0	3	0	0
T89	0	1	0	0
T103	18417	0	0	0
T106	0	4	0	0
T109	0	1	0	0
T131	14477	0	0	0
T251	0	2	0	0
T271	14832	0	0	0
T286	0	1	0	0
T289	0	1	0	0
T290	0	2	0	0
T291	433	0	0	0
T292	403	0	0	0
T293	452	0	0	0
T294	507	0	0	0
T295	8424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	14589	0	0
T2	20722	37	0	0
T3	480	0	0	0
T7	0	410	0	0
T12	0	192	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	51	0	0
T33	0	46	0	0
T35	0	47	0	0
T52	0	115	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	246	0	0
T130	0	192	0	0
T135	0	58	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	363	0	0
T2	20722	3	0	0
T3	480	0	0	0
T7	0	6	0	0
T12	0	4	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	9	0	0
T52	0	6	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	5	0	0
T130	0	5	0	0
T135	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6133206	0	0
T1	21527	16117	0	0
T2	20722	16117	0	0
T3	480	79	0	0
T4	5866	5465	0	0
T5	23035	22591	0	0
T13	10672	10271	0	0
T14	521	120	0	0
T15	698	297	0	0
T16	407	6	0	0
T17	509	108	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6135012	0	0
T1	21527	16117	0	0
T2	20722	16117	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	480	0	0
T2	20722	3	0	0
T3	480	0	0	0
T7	0	8	0	0
T12	0	4	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T35	0	11	0	0
T52	0	6	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	5	0	0
T130	0	5	0	0
T135	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	434	0	0
T2	20722	3	0	0
T3	480	0	0	0
T7	0	6	0	0
T12	0	4	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T35	0	9	0	0
T52	0	6	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	5	0	0
T130	0	5	0	0
T135	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	363	0	0
T2	20722	3	0	0
T3	480	0	0	0
T7	0	6	0	0
T12	0	4	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	9	0	0
T52	0	6	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	5	0	0
T130	0	5	0	0
T135	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	363	0	0
T2	20722	3	0	0
T3	480	0	0	0
T7	0	6	0	0
T12	0	4	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	9	0	0
T52	0	6	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	5	0	0
T130	0	5	0	0
T135	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	14207	0	0
T2	20722	34	0	0
T3	480	0	0	0
T7	0	404	0	0
T12	0	187	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	50	0	0
T33	0	45	0	0
T35	0	38	0	0
T52	0	109	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	241	0	0
T130	0	187	0	0
T135	0	47	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	6529666	0	0
T1	21527	21082	0	0
T2	20722	20279	0	0
T3	480	80	0	0
T4	5866	5466	0	0
T5	23035	22599	0	0
T13	10672	10272	0	0
T14	521	121	0	0
T15	698	298	0	0
T16	407	7	0	0
T17	509	109	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7221089	343	0	0
T2	20722	3	0	0
T3	480	0	0	0
T7	0	6	0	0
T12	0	3	0	0
T14	521	0	0	0
T15	698	0	0	0
T16	407	0	0	0
T17	509	0	0	0
T22	488	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T35	0	9	0	0
T52	0	6	0	0
T57	422	0	0	0
T58	426	0	0	0
T59	716	0	0	0
T103	0	5	0	0
T130	0	5	0	0
T135	0	11	0	0