Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1277240674	10249	0	0
auto_block_debounce_ctl_rd_A	1277240674	2168	0	0
auto_block_out_ctl_rd_A	1277240674	2888	0	0
com_det_ctl_0_rd_A	1277240674	3909	0	0
com_det_ctl_1_rd_A	1277240674	3866	0	0
com_det_ctl_2_rd_A	1277240674	4111	0	0
com_det_ctl_3_rd_A	1277240674	3888	0	0
com_out_ctl_0_rd_A	1277240674	4361	0	0
com_out_ctl_1_rd_A	1277240674	4605	0	0
com_out_ctl_2_rd_A	1277240674	4708	0	0
com_out_ctl_3_rd_A	1277240674	4479	0	0
com_pre_det_ctl_0_rd_A	1277240674	1466	0	0
com_pre_det_ctl_1_rd_A	1277240674	1432	0	0
com_pre_det_ctl_2_rd_A	1277240674	1326	0	0
com_pre_det_ctl_3_rd_A	1277240674	1519	0	0
com_pre_sel_ctl_0_rd_A	1277240674	4623	0	0
com_pre_sel_ctl_1_rd_A	1277240674	4519	0	0
com_pre_sel_ctl_2_rd_A	1277240674	4658	0	0
com_pre_sel_ctl_3_rd_A	1277240674	4516	0	0
com_sel_ctl_0_rd_A	1277240674	4631	0	0
com_sel_ctl_1_rd_A	1277240674	4733	0	0
com_sel_ctl_2_rd_A	1277240674	4677	0	0
com_sel_ctl_3_rd_A	1277240674	4702	0	0
ec_rst_ctl_rd_A	1277240674	2611	0	0
intr_enable_rd_A	1277240674	2845	0	0
key_intr_ctl_rd_A	1277240674	3669	0	0
key_intr_debounce_ctl_rd_A	1277240674	1465	0	0
key_invert_ctl_rd_A	1277240674	6329	0	0
pin_allowed_ctl_rd_A	1277240674	7231	0	0
pin_out_ctl_rd_A	1277240674	5092	0	0
pin_out_value_rd_A	1277240674	5520	0	0
regwen_rd_A	1277240674	1894	0	0
ulp_ac_debounce_ctl_rd_A	1277240674	1520	0	0
ulp_ctl_rd_A	1277240674	1752	0	0
ulp_lid_debounce_ctl_rd_A	1277240674	1749	0	0
ulp_pwrb_debounce_ctl_rd_A	1277240674	1671	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	10249	0	0
T6	153340	0	0	0
T7	149569	0	0	0
T8	303069	0	0	0
T9	339047	3	0	0
T11	0	5	0	0
T25	903567	14	0	0
T26	90540	0	0	0
T34	0	8	0	0
T37	0	9	0	0
T38	0	6	0	0
T39	0	5	0	0
T62	49059	0	0	0
T65	136997	0	0	0
T69	191277	0	0	0
T70	64818	0	0	0
T105	0	6	0	0
T189	0	12	0	0
T251	0	6	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2168	0	0
T3	240086	0	0	0
T15	342330	12	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T26	0	7	0	0
T27	668016	0	0	0
T37	0	47	0	0
T50	0	6	0	0
T53	0	6	0	0
T54	0	16	0	0
T55	0	8	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T102	0	9	0	0
T181	0	9	0	0
T313	0	5	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2888	0	0
T3	240086	0	0	0
T15	342330	4	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T26	0	8	0	0
T27	668016	0	0	0
T37	0	66	0	0
T50	0	8	0	0
T53	0	6	0	0
T54	0	11	0	0
T55	0	18	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T102	0	7	0	0
T132	0	10	0	0
T181	0	15	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	3909	0	0
T1	102256	44	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	60	0	0
T34	0	132	0	0
T37	0	105	0	0
T39	0	54	0	0
T103	0	68	0	0
T105	0	102	0	0
T152	0	58	0	0
T189	0	64	0	0
T314	0	81	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	3866	0	0
T1	102256	63	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	34	0	0
T34	0	89	0	0
T37	0	86	0	0
T39	0	104	0	0
T103	0	63	0	0
T105	0	106	0	0
T152	0	34	0	0
T189	0	54	0	0
T314	0	53	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4111	0	0
T1	102256	81	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	45	0	0
T34	0	109	0	0
T37	0	87	0	0
T39	0	87	0	0
T103	0	60	0	0
T105	0	71	0	0
T152	0	36	0	0
T189	0	76	0	0
T314	0	78	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	3888	0	0
T1	102256	76	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	59	0	0
T34	0	98	0	0
T37	0	90	0	0
T39	0	68	0	0
T103	0	52	0	0
T105	0	71	0	0
T152	0	39	0	0
T189	0	37	0	0
T314	0	87	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4361	0	0
T1	102256	80	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	55	0	0
T34	0	124	0	0
T37	0	88	0	0
T39	0	57	0	0
T103	0	49	0	0
T105	0	56	0	0
T152	0	39	0	0
T189	0	51	0	0
T314	0	71	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4605	0	0
T1	102256	68	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	42	0	0
T34	0	107	0	0
T37	0	71	0	0
T39	0	98	0	0
T103	0	45	0	0
T105	0	96	0	0
T152	0	25	0	0
T189	0	63	0	0
T314	0	71	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4708	0	0
T1	102256	87	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	67	0	0
T34	0	125	0	0
T37	0	99	0	0
T39	0	89	0	0
T103	0	64	0	0
T105	0	91	0	0
T152	0	40	0	0
T189	0	73	0	0
T314	0	73	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4479	0	0
T1	102256	70	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	57	0	0
T34	0	132	0	0
T37	0	92	0	0
T39	0	85	0	0
T103	0	52	0	0
T105	0	66	0	0
T152	0	43	0	0
T189	0	54	0	0
T314	0	76	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1466	0	0
T33	355147	0	0	0
T34	0	2	0	0
T37	851931	30	0	0
T39	0	21	0	0
T40	0	31	0	0
T102	277085	0	0	0
T105	0	21	0	0
T109	0	12	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	24	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T299	0	56	0	0
T315	0	27	0	0
T316	0	2	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1432	0	0
T33	355147	0	0	0
T34	0	14	0	0
T37	851931	26	0	0
T39	0	17	0	0
T40	0	41	0	0
T102	277085	0	0	0
T105	0	22	0	0
T109	0	7	0	0
T127	0	4	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	29	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T299	0	33	0	0
T315	0	9	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1326	0	0
T33	355147	0	0	0
T34	0	10	0	0
T37	851931	24	0	0
T39	0	9	0	0
T40	0	37	0	0
T102	277085	0	0	0
T105	0	10	0	0
T109	0	4	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	17	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T299	0	39	0	0
T315	0	19	0	0
T316	0	1	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1519	0	0
T33	355147	0	0	0
T34	0	13	0	0
T37	851931	14	0	0
T39	0	17	0	0
T40	0	47	0	0
T102	277085	0	0	0
T105	0	15	0	0
T109	0	11	0	0
T127	0	4	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	28	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T299	0	18	0	0
T315	0	29	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4623	0	0
T1	102256	66	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	36	0	0
T34	0	120	0	0
T37	0	116	0	0
T39	0	73	0	0
T103	0	43	0	0
T105	0	86	0	0
T152	0	34	0	0
T189	0	65	0	0
T314	0	74	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4519	0	0
T1	102256	78	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	43	0	0
T34	0	111	0	0
T37	0	86	0	0
T39	0	76	0	0
T103	0	38	0	0
T105	0	83	0	0
T152	0	34	0	0
T189	0	45	0	0
T314	0	56	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4658	0	0
T1	102256	43	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	51	0	0
T34	0	122	0	0
T37	0	94	0	0
T39	0	88	0	0
T103	0	63	0	0
T105	0	78	0	0
T152	0	35	0	0
T189	0	73	0	0
T314	0	84	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4516	0	0
T1	102256	66	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	37	0	0
T34	0	133	0	0
T37	0	76	0	0
T39	0	89	0	0
T103	0	70	0	0
T105	0	61	0	0
T152	0	35	0	0
T189	0	51	0	0
T314	0	75	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4631	0	0
T1	102256	67	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	48	0	0
T34	0	111	0	0
T37	0	103	0	0
T39	0	74	0	0
T103	0	55	0	0
T105	0	76	0	0
T152	0	31	0	0
T189	0	71	0	0
T314	0	79	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4733	0	0
T1	102256	71	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	64	0	0
T34	0	117	0	0
T37	0	108	0	0
T39	0	99	0	0
T103	0	73	0	0
T105	0	101	0	0
T152	0	47	0	0
T189	0	49	0	0
T314	0	74	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4677	0	0
T1	102256	84	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	41	0	0
T34	0	106	0	0
T37	0	117	0	0
T39	0	84	0	0
T103	0	70	0	0
T105	0	78	0	0
T152	0	37	0	0
T189	0	67	0	0
T314	0	64	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	4702	0	0
T1	102256	52	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	0	0	0
T5	115176	0	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	48	0	0
T34	0	117	0	0
T37	0	81	0	0
T39	0	91	0	0
T103	0	62	0	0
T105	0	76	0	0
T152	0	48	0	0
T189	0	56	0	0
T314	0	51	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2611	0	0
T1	102256	25	0	0
T2	248674	0	0	0
T3	240086	0	0	0
T4	281603	1	0	0
T5	115176	0	0	0
T6	0	2	0	0
T13	128064	0	0	0
T14	250527	0	0	0
T15	342330	0	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T33	0	9	0	0
T37	0	35	0	0
T54	0	4	0	0
T80	0	3	0	0
T81	0	5	0	0
T85	0	7	0	0
T103	0	28	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	2845	0	0
T6	153340	26	0	0
T7	149569	0	0	0
T8	303069	0	0	0
T9	339047	0	0	0
T34	0	77	0	0
T37	0	86	0	0
T39	0	23	0	0
T40	0	38	0	0
T49	777818	0	0	0
T50	86236	0	0	0
T70	64818	0	0	0
T75	243728	0	0	0
T85	172589	0	0	0
T86	50827	0	0	0
T105	0	98	0	0
T109	0	17	0	0
T189	0	89	0	0
T299	0	30	0	0
T315	0	38	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	3669	0	0
T3	240086	5	0	0
T6	0	15	0	0
T16	44781	0	0	0
T17	25470	0	0	0
T22	197835	0	0	0
T27	668016	0	0	0
T34	0	13	0	0
T37	0	32	0	0
T39	0	16	0	0
T40	0	36	0	0
T41	0	5	0	0
T48	783542	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T105	0	40	0	0
T109	0	15	0	0
T189	0	39	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1465	0	0
T33	355147	0	0	0
T34	0	17	0	0
T37	851931	24	0	0
T39	0	14	0	0
T40	0	39	0	0
T102	277085	0	0	0
T105	0	31	0	0
T109	0	6	0	0
T127	0	3	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	18	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T299	0	36	0	0
T315	0	9	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	6329	0	0
T32	368349	0	0	0
T34	0	87	0	0
T37	0	22	0	0
T39	0	245	0	0
T40	0	39	0	0
T72	233811	29	0	0
T103	202592	0	0	0
T105	0	151	0	0
T109	0	132	0	0
T131	180972	0	0	0
T189	0	89	0	0
T253	0	65	0	0
T271	726784	0	0	0
T291	51965	0	0	0
T292	96876	0	0	0
T293	67883	0	0	0
T294	60836	0	0	0
T295	101092	0	0	0
T317	0	84	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	7231	0	0
T17	25470	89	0	0
T22	197835	0	0	0
T23	247353	0	0	0
T27	668016	0	0	0
T34	0	135	0	0
T37	0	212	0	0
T39	0	231	0	0
T40	0	121	0	0
T48	783542	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T61	108953	0	0	0
T105	0	258	0	0
T146	0	23	0	0
T180	0	52	0	0
T189	0	70	0	0
T226	0	42	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	5092	0	0
T17	25470	63	0	0
T22	197835	0	0	0
T23	247353	0	0	0
T27	668016	0	0	0
T34	0	143	0	0
T37	0	155	0	0
T39	0	195	0	0
T40	0	107	0	0
T48	783542	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T61	108953	0	0	0
T105	0	191	0	0
T146	0	54	0	0
T180	0	79	0	0
T189	0	91	0	0
T226	0	42	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	5520	0	0
T17	25470	77	0	0
T22	197835	0	0	0
T23	247353	0	0	0
T27	668016	0	0	0
T34	0	124	0	0
T37	0	157	0	0
T39	0	210	0	0
T40	0	125	0	0
T48	783542	0	0	0
T57	206645	0	0	0
T58	51198	0	0	0
T59	89548	0	0	0
T60	763886	0	0	0
T61	108953	0	0	0
T105	0	226	0	0
T146	0	33	0	0
T180	0	65	0	0
T189	0	107	0	0
T226	0	57	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1894	0	0
T33	355147	0	0	0
T34	0	3	0	0
T37	851931	7	0	0
T39	0	8	0	0
T40	0	24	0	0
T102	277085	0	0	0
T105	0	22	0	0
T109	0	7	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	18	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T299	0	33	0	0
T315	0	14	0	0
T316	0	5	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1520	0	0
T33	355147	0	0	0
T34	0	6	0	0
T37	851931	18	0	0
T39	0	17	0	0
T40	0	24	0	0
T82	0	7	0	0
T102	277085	0	0	0
T105	0	45	0	0
T109	0	6	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	25	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T315	0	15	0	0
T318	0	4	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1752	0	0
T33	355147	0	0	0
T34	0	28	0	0
T37	851931	18	0	0
T39	0	26	0	0
T40	0	28	0	0
T82	0	8	0	0
T83	0	1	0	0
T102	277085	0	0	0
T105	0	41	0	0
T109	0	15	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	53	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T318	0	15	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1749	0	0
T34	0	19	0	0
T37	0	15	0	0
T39	0	21	0	0
T40	0	30	0	0
T47	507802	0	0	0
T68	40941	2	0	0
T80	369245	0	0	0
T81	131708	0	0	0
T82	0	16	0	0
T83	0	2	0	0
T105	0	41	0	0
T109	0	19	0	0
T135	406477	0	0	0
T166	320501	0	0	0
T167	51131	0	0	0
T168	62814	0	0	0
T189	0	35	0	0
T220	11119	0	0	0
T221	15079	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1277240674	1671	0	0
T33	355147	0	0	0
T34	0	12	0	0
T37	851931	27	0	0
T39	0	8	0	0
T40	0	33	0	0
T82	0	17	0	0
T83	0	5	0	0
T102	277085	0	0	0
T105	0	23	0	0
T109	0	20	0	0
T132	21383	0	0	0
T133	394336	0	0	0
T189	0	25	0	0
T214	57787	0	0	0
T215	82689	0	0	0
T216	891743	0	0	0
T217	141439	0	0	0
T218	49110	0	0	0
T319	0	7	0	0