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 LINE       6677
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T15,T22
110CoveredT302,T306,T305
111CoveredT9,T11,T21

 LINE       6680
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T5,T13
110CoveredT302,T305,T307
111CoveredT1,T2,T7

 LINE       6682
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T15,T22
110CoveredT305,T307,T308
111CoveredT22,T23,T24

 LINE       6695
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T14,T15
110CoveredT30,T302,T304
111CoveredT14,T17,T22

 LINE       6712
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT304,T305,T307
111CoveredT1,T4,T5

 LINE       6721
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T14,T15
110CoveredT300,T304,T306
111CoveredT14,T17,T25

 LINE       6730
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T15,T3
110CoveredT302,T306,T305
111CoveredT3,T6,T8

 LINE       6745
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT305,T307,T308
111CoveredT1,T4,T5

 LINE       6747
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T15,T22
110CoveredT306,T305,T307
111CoveredT15,T25,T26

 LINE       6750
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T15,T22
110CoveredT302,T304,T306
111CoveredT15,T25,T26

 LINE       6757
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT304,T305,T307
111CoveredT4,T13,T27

 LINE       6763
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT302,T306,T305
111CoveredT4,T13,T27

 LINE       6769
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT306,T305,T307
111CoveredT4,T13,T27

 LINE       6775
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT302,T304,T306
111CoveredT4,T13,T27

 LINE       6781
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT4,T13,T15
110CoveredT302,T305,T307
111CoveredT4,T13,T27

 LINE       6783
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT4,T13,T15
110CoveredT302,T304,T305
111CoveredT4,T13,T27

 LINE       6785
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT4,T13,T15
110CoveredT304,T306,T305
111CoveredT4,T13,T27

 LINE       6787
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT4,T13,T15
110CoveredT302,T298,T304
111CoveredT4,T13,T27

 LINE       6789
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT304,T306,T305
111CoveredT1,T4,T5

 LINE       6795
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT305,T307,T308
111CoveredT1,T4,T5

 LINE       6801
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT304,T306,T305
111CoveredT1,T4,T5

 LINE       6807
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT302,T304,T306
111CoveredT1,T4,T5

 LINE       6813
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT302,T304,T305
111CoveredT1,T4,T5

 LINE       6815
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT302,T305,T307
111CoveredT1,T4,T5

 LINE       6817
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT29,T302,T304
111CoveredT1,T4,T5

 LINE       6819
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT299,T302,T306
111CoveredT1,T4,T5

 LINE       6821
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT302,T306,T305
111CoveredT1,T4,T5

 LINE       6826
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT306,T305,T308
111CoveredT1,T4,T5

 LINE       6831
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT251,T302,T305
111CoveredT1,T4,T5

 LINE       6836
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T4,T5
110CoveredT305,T307,T309
111CoveredT1,T4,T5

 LINE       6841
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT1,T5,T13
110CoveredT304,T310,T305
111CoveredT1,T2,T7

 LINE       6850
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T4,T5
101CoveredT13,T15,T3
110CoveredT302,T304,T306
111CoveredT3,T6,T8

 LINE       7105
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T4,T5
01Unreachable
10CoveredT1,T4,T5
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%