Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.60 100.00 94.41 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 98.60 100.00 94.40 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.60 100.00 94.40 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.07 99.38 97.02 100.00 98.94 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_auto_block_debounce_ctl_auto_block_enable 100.00 100.00 100.00 100.00
u_auto_block_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
u_auto_block_debounce_ctl_debounce_timer 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_cdc 99.17 100.00 96.67 100.00 100.00
u_auto_block_out_ctl_key0_out_sel 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key0_out_value 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key1_out_sel 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key1_out_value 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key2_out_sel 100.00 100.00 100.00 100.00
u_auto_block_out_ctl_key2_out_value 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_com_det_ctl_0 100.00 100.00 100.00 100.00
u_com_det_ctl_0_cdc 99.17 100.00 96.67 100.00 100.00
u_com_det_ctl_1 100.00 100.00 100.00 100.00
u_com_det_ctl_1_cdc 99.17 100.00 96.67 100.00 100.00
u_com_det_ctl_2 100.00 100.00 100.00 100.00
u_com_det_ctl_2_cdc 99.17 100.00 96.67 100.00 100.00
u_com_det_ctl_3 100.00 100.00 100.00 100.00
u_com_det_ctl_3_cdc 99.17 100.00 96.67 100.00 100.00
u_com_out_ctl_0_bat_disable_0 100.00 100.00 100.00 100.00
u_com_out_ctl_0_cdc 99.17 100.00 96.67 100.00 100.00
u_com_out_ctl_0_ec_rst_0 100.00 100.00 100.00 100.00
u_com_out_ctl_0_interrupt_0 100.00 100.00 100.00 100.00
u_com_out_ctl_0_rst_req_0 100.00 100.00 100.00 100.00
u_com_out_ctl_1_bat_disable_1 100.00 100.00 100.00 100.00
u_com_out_ctl_1_cdc 99.17 100.00 96.67 100.00 100.00
u_com_out_ctl_1_ec_rst_1 100.00 100.00 100.00 100.00
u_com_out_ctl_1_interrupt_1 100.00 100.00 100.00 100.00
u_com_out_ctl_1_rst_req_1 100.00 100.00 100.00 100.00
u_com_out_ctl_2_bat_disable_2 100.00 100.00 100.00 100.00
u_com_out_ctl_2_cdc 99.17 100.00 96.67 100.00 100.00
u_com_out_ctl_2_ec_rst_2 100.00 100.00 100.00 100.00
u_com_out_ctl_2_interrupt_2 100.00 100.00 100.00 100.00
u_com_out_ctl_2_rst_req_2 100.00 100.00 100.00 100.00
u_com_out_ctl_3_bat_disable_3 100.00 100.00 100.00 100.00
u_com_out_ctl_3_cdc 99.17 100.00 96.67 100.00 100.00
u_com_out_ctl_3_ec_rst_3 100.00 100.00 100.00 100.00
u_com_out_ctl_3_interrupt_3 100.00 100.00 100.00 100.00
u_com_out_ctl_3_rst_req_3 100.00 100.00 100.00 100.00
u_com_pre_det_ctl_0 100.00 100.00 100.00 100.00
u_com_pre_det_ctl_0_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_det_ctl_1 100.00 100.00 100.00 100.00
u_com_pre_det_ctl_1_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_det_ctl_2 100.00 100.00 100.00 100.00
u_com_pre_det_ctl_2_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_det_ctl_3 100.00 100.00 100.00 100.00
u_com_pre_det_ctl_3_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_sel_ctl_0_ac_present_sel_0 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_0_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_sel_ctl_0_key0_in_sel_0 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_0_key1_in_sel_0 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_0_key2_in_sel_0 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_0_pwrb_in_sel_0 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_1_ac_present_sel_1 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_1_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_sel_ctl_1_key0_in_sel_1 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_1_key1_in_sel_1 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_1_key2_in_sel_1 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_1_pwrb_in_sel_1 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_2_ac_present_sel_2 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_2_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_sel_ctl_2_key0_in_sel_2 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_2_key1_in_sel_2 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_2_key2_in_sel_2 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_2_pwrb_in_sel_2 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_3_ac_present_sel_3 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_3_cdc 99.17 100.00 96.67 100.00 100.00
u_com_pre_sel_ctl_3_key0_in_sel_3 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_3_key1_in_sel_3 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_3_key2_in_sel_3 100.00 100.00 100.00 100.00
u_com_pre_sel_ctl_3_pwrb_in_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_ac_present_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_cdc 99.17 100.00 96.67 100.00 100.00
u_com_sel_ctl_0_key0_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_key1_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_key2_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_0_pwrb_in_sel_0 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_ac_present_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_cdc 99.17 100.00 96.67 100.00 100.00
u_com_sel_ctl_1_key0_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_key1_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_key2_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_1_pwrb_in_sel_1 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_ac_present_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_cdc 99.17 100.00 96.67 100.00 100.00
u_com_sel_ctl_2_key0_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_key1_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_key2_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_2_pwrb_in_sel_2 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_ac_present_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_cdc 99.17 100.00 96.67 100.00 100.00
u_com_sel_ctl_3_key0_in_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_key1_in_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_key2_in_sel_3 100.00 100.00 100.00 100.00
u_com_sel_ctl_3_pwrb_in_sel_3 100.00 100.00 100.00 100.00
u_combo_intr_status_combo0_h2l 100.00 100.00 100.00 100.00
u_combo_intr_status_combo1_h2l 100.00 100.00 100.00 100.00
u_combo_intr_status_combo2_h2l 100.00 100.00 100.00 100.00
u_combo_intr_status_combo3_h2l 100.00 100.00 100.00 100.00
u_ec_rst_ctl 100.00 100.00 100.00 100.00
u_ec_rst_ctl_cdc 98.33 100.00 93.33 100.00 100.00
u_intr_enable 100.00 100.00 100.00 100.00
u_intr_state 62.59 77.78 50.00 60.00
u_intr_test 100.00 100.00
u_key_intr_ctl_ac_present_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_ac_present_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_cdc 99.17 100.00 96.67 100.00 100.00
u_key_intr_ctl_ec_rst_l_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_ec_rst_l_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_flash_wp_l_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_flash_wp_l_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_key0_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_key0_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_key1_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_key1_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_key2_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_key2_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_ctl_pwrb_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_ctl_pwrb_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_debounce_ctl 100.00 100.00 100.00 100.00
u_key_intr_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
u_key_intr_status_ac_present_h2l 100.00 100.00 100.00 100.00
u_key_intr_status_ac_present_l2h 100.00 100.00 100.00 100.00
u_key_intr_status_ec_rst_l_h2l 100.00 100.00 100.00 100.00
u_key_intr_status_ec_rst_l_l2h 100.00 100.00 100.00 100.00
u_key_intr_status_flash_wp_l_h2l 100.00 100.00 100.00 100.00
u_key_intr_status_flash_wp_l_l2h 100.00 100.00 100.00 100.00
u_key_intr_status_key0_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_status_key0_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_status_key1_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_status_key1_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_status_key2_in_h2l 100.00 100.00 100.00 100.00
u_key_intr_status_key2_in_l2h 100.00 100.00 100.00 100.00
u_key_intr_status_pwrb_h2l 100.00 100.00 100.00 100.00
u_key_intr_status_pwrb_l2h 100.00 100.00 100.00 100.00
u_key_invert_ctl_ac_present 100.00 100.00 100.00 100.00
u_key_invert_ctl_bat_disable 100.00 100.00 100.00 100.00
u_key_invert_ctl_cdc 99.17 100.00 96.67 100.00 100.00
u_key_invert_ctl_key0_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_key0_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_key1_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_key1_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_key2_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_key2_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_lid_open 100.00 100.00 100.00 100.00
u_key_invert_ctl_pwrb_in 100.00 100.00 100.00 100.00
u_key_invert_ctl_pwrb_out 100.00 100.00 100.00 100.00
u_key_invert_ctl_z3_wakeup 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_bat_disable_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_bat_disable_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_cdc 99.17 100.00 96.67 100.00 100.00
u_pin_allowed_ctl_ec_rst_l_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_ec_rst_l_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_flash_wp_l_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_flash_wp_l_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key0_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key0_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key1_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key1_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key2_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_key2_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_pwrb_out_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_pwrb_out_1 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_z3_wakeup_0 100.00 100.00 100.00 100.00
u_pin_allowed_ctl_z3_wakeup_1 100.00 100.00 100.00 100.00
u_pin_in_value_ac_present 62.59 77.78 50.00 60.00
u_pin_in_value_ec_rst_l 62.59 77.78 50.00 60.00
u_pin_in_value_flash_wp_l 62.59 77.78 50.00 60.00
u_pin_in_value_key0_in 62.59 77.78 50.00 60.00
u_pin_in_value_key1_in 62.59 77.78 50.00 60.00
u_pin_in_value_key2_in 62.59 77.78 50.00 60.00
u_pin_in_value_lid_open 62.59 77.78 50.00 60.00
u_pin_in_value_pwrb_in 62.59 77.78 50.00 60.00
u_pin_out_ctl_bat_disable 100.00 100.00 100.00 100.00
u_pin_out_ctl_cdc 99.17 100.00 96.67 100.00 100.00
u_pin_out_ctl_ec_rst_l 100.00 100.00 100.00 100.00
u_pin_out_ctl_flash_wp_l 100.00 100.00 100.00 100.00
u_pin_out_ctl_key0_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_key1_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_key2_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_pwrb_out 100.00 100.00 100.00 100.00
u_pin_out_ctl_z3_wakeup 100.00 100.00 100.00 100.00
u_pin_out_value_bat_disable 100.00 100.00 100.00 100.00
u_pin_out_value_cdc 99.17 100.00 96.67 100.00 100.00
u_pin_out_value_ec_rst_l 100.00 100.00 100.00 100.00
u_pin_out_value_flash_wp_l 100.00 100.00 100.00 100.00
u_pin_out_value_key0_out 100.00 100.00 100.00 100.00
u_pin_out_value_key1_out 100.00 100.00 100.00 100.00
u_pin_out_value_key2_out 100.00 100.00 100.00 100.00
u_pin_out_value_pwrb_out 100.00 100.00 100.00 100.00
u_pin_out_value_z3_wakeup 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.69 97.14 97.62 100.00 100.00
u_regwen 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_ulp_ac_debounce_ctl 100.00 100.00 100.00 100.00
u_ulp_ac_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
u_ulp_ctl 100.00 100.00 100.00 100.00
u_ulp_ctl_cdc 99.22 100.00 96.88 100.00 100.00
u_ulp_lid_debounce_ctl 100.00 100.00 100.00 100.00
u_ulp_lid_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
u_ulp_pwrb_debounce_ctl 100.00 100.00 100.00 100.00
u_ulp_pwrb_debounce_ctl_cdc 98.33 100.00 93.33 100.00 100.00
u_ulp_status 100.00 100.00 100.00 100.00
u_wkup_status 100.00 100.00 100.00 100.00
u_wkup_status_cdc 93.79 96.99 84.93 93.22 100.00

Line Coverage for Module : sysrst_ctrl_reg_top
Line No.TotalCoveredPercent
TOTAL512512100.00
ALWAYS7044100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
ALWAYS29922100.00
CONT_ASSIGN32711100.00
ALWAYS33822100.00
CONT_ASSIGN36611100.00
ALWAYS37722100.00
CONT_ASSIGN40511100.00
ALWAYS41622100.00
CONT_ASSIGN44411100.00
ALWAYS45422100.00
CONT_ASSIGN48211100.00
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CONT_ASSIGN52511100.00
ALWAYS5471313100.00
CONT_ASSIGN58611100.00
ALWAYS6121717100.00
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CONT_ASSIGN70711100.00
ALWAYS72499100.00
CONT_ASSIGN75911100.00
ALWAYS7831515100.00
CONT_ASSIGN82411100.00
ALWAYS83522100.00
CONT_ASSIGN86311100.00
ALWAYS87533100.00
CONT_ASSIGN90411100.00
ALWAYS92077100.00
CONT_ASSIGN95311100.00
ALWAYS96866100.00
CONT_ASSIGN100011100.00
ALWAYS101566100.00
CONT_ASSIGN104711100.00
ALWAYS106266100.00
CONT_ASSIGN109411100.00
ALWAYS110966100.00
CONT_ASSIGN114111100.00
ALWAYS115222100.00
CONT_ASSIGN118011100.00
ALWAYS119122100.00
CONT_ASSIGN121911100.00
ALWAYS123022100.00
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ALWAYS135966100.00
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ALWAYS157422100.00
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ALWAYS65584444100.00
CONT_ASSIGN660411100.00
ALWAYS660811100.00
CONT_ASSIGN665511100.00
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CONT_ASSIGN686611100.00
CONT_ASSIGN686811100.00
CONT_ASSIGN687011100.00
CONT_ASSIGN687211100.00
CONT_ASSIGN687411100.00
CONT_ASSIGN687611100.00
CONT_ASSIGN687811100.00
ALWAYS68824444100.00
ALWAYS69306868100.00
CONT_ASSIGN710511100.00
ALWAYS71073636100.00
CONT_ASSIGN722411100.00
CONT_ASSIGN722511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
79 1 1
91 1 1
92 1 1
120 1 1
121 1 1
299 1 1
300 1 1
327 1 1
338 1 1
339 1 1
366 1 1
377 1 1
378 1 1
405 1 1
416 1 1
417 1 1
444 1 1
454 1 1
455 1 1
482 1 1
495 1 1
496 1 1
497 1 1
498 1 1
525 1 1
547 1 1
548 1 1
549 1 1
550 1 1
551 1 1
552 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
586 1 1
612 1 1
613 1 1
614 1 1
615 1 1
616 1 1
617 1 1
618 1 1
619 1 1
620 1 1
621 1 1
622 1 1
623 1 1
624 1 1
625 1 1
626 1 1
627 1 1
628 1 1
655 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
678 1 1
679 1 1
680 1 1
707 1 1
724 1 1
725 1 1
726 1 1
727 1 1
728 1 1
729 1 1
730 1 1
731 1 1
732 1 1
759 1 1
783 1 1
784 1 1
785 1 1
786 1 1
787 1 1
788 1 1
789 1 1
790 1 1
791 1 1
792 1 1
793 1 1
794 1 1
795 1 1
796 1 1
797 1 1
824 1 1
835 1 1
836 1 1
863 1 1
875 1 1
876 1 1
877 1 1
904 1 1
920 1 1
921 1 1
922 1 1
923 1 1
924 1 1
925 1 1
926 1 1
953 1 1
968 1 1
969 1 1
970 1 1
971 1 1
972 1 1
973 1 1
1000 1 1
1015 1 1
1016 1 1
1017 1 1
1018 1 1
1019 1 1
1020 1 1
1047 1 1
1062 1 1
1063 1 1
1064 1 1
1065 1 1
1066 1 1
1067 1 1
1094 1 1
1109 1 1
1110 1 1
1111 1 1
1112 1 1
1113 1 1
1114 1 1
1141 1 1
1152 1 1
1153 1 1
1180 1 1
1191 1 1
1192 1 1
1219 1 1
1230 1 1
1231 1 1
1258 1 1
1269 1 1
1270 1 1
1297 1 1
1312 1 1
1313 1 1
1314 1 1
1315 1 1
1316 1 1
1317 1 1
1344 1 1
1359 1 1
1360 1 1
1361 1 1
1362 1 1
1363 1 1
1364 1 1
1391 1 1
1406 1 1
1407 1 1
1408 1 1
1409 1 1
1410 1 1
1411 1 1
1438 1 1
1453 1 1
1454 1 1
1455 1 1
1456 1 1
1457 1 1
1458 1 1
1485 1 1
1496 1 1
1497 1 1
1524 1 1
1535 1 1
1536 1 1
1563 1 1
1574 1 1
1575 1 1
1602 1 1
1613 1 1
1614 1 1
1641 1 1
1655 1 1
1656 1 1
1657 1 1
1658 1 1
1659 1 1
1686 1 1
1700 1 1
1701 1 1
1702 1 1
1703 1 1
1704 1 1
1731 1 1
1745 1 1
1746 1 1
1747 1 1
1748 1 1
1749 1 1
1776 1 1
1790 1 1
1791 1 1
1792 1 1
1793 1 1
1794 1 1
1821 1 1
1884 1 1
1898 1 1
1904 1 1
1918 1 1
1952 1 1
1983 1 1
2015 1 1
2047 1 1
2134 1 1
2165 1 1
2494 1 1
3585 1 1
3968 1 1
4000 1 1
4060 1 1
4229 1 1
4370 1 1
4511 1 1
4652 1 1
4793 1 1
4825 1 1
4857 1 1
4889 1 1
4921 1 1
5062 1 1
5203 1 1
5344 1 1
5485 1 1
5517 1 1
5549 1 1
5581 1 1
5613 1 1
5727 1 1
5841 1 1
5955 1 1
6558 1 1
6559 1 1
6560 1 1
6561 1 1
6562 1 1
6563 1 1
6564 1 1
6565 1 1
6566 1 1
6567 1 1
6568 1 1
6569 1 1
6570 1 1
6571 1 1
6572 1 1
6573 1 1
6574 1 1
6575 1 1
6576 1 1
6577 1 1
6578 1 1
6579 1 1
6580 1 1
6581 1 1
6582 1 1
6583 1 1
6584 1 1
6585 1 1
6586 1 1
6587 1 1
6588 1 1
6589 1 1
6590 1 1
6591 1 1
6592 1 1
6593 1 1
6594 1 1
6595 1 1
6596 1 1
6597 1 1
6598 1 1
6599 1 1
6600 1 1
6601 1 1
6604 1 1
6608 1 1
6655 1 1
6657 1 1
6658 1 1
6660 1 1
6661 1 1
6663 1 1
6664 1 1
6666 1 1
6667 1 1
6669 1 1
6671 1 1
6673 1 1
6675 1 1
6677 1 1
6679 1 1
6680 1 1
6682 1 1
6695 1 1
6712 1 1
6721 1 1
6730 1 1
6745 1 1
6747 1 1
6750 1 1
6757 1 1
6763 1 1
6769 1 1
6775 1 1
6781 1 1
6783 1 1
6785 1 1
6787 1 1
6789 1 1
6795 1 1
6801 1 1
6807 1 1
6813 1 1
6815 1 1
6817 1 1
6819 1 1
6821 1 1
6826 1 1
6831 1 1
6836 1 1
6841 1 1
6843 1 1
6845 1 1
6847 1 1
6849 1 1
6850 1 1
6852 1 1
6854 1 1
6856 1 1
6858 1 1
6860 1 1
6862 1 1
6864 1 1
6866 1 1
6868 1 1
6870 1 1
6872 1 1
6874 1 1
6876 1 1
6878 1 1
6882 1 1
6883 1 1
6884 1 1
6885 1 1
6886 1 1
6887 1 1
6888 1 1
6889 1 1
6890 1 1
6891 1 1
6892 1 1
6893 1 1
6894 1 1
6895 1 1
6896 1 1
6897 1 1
6898 1 1
6899 1 1
6900 1 1
6901 1 1
6902 1 1
6903 1 1
6904 1 1
6905 1 1
6906 1 1
6907 1 1
6908 1 1
6909 1 1
6910 1 1
6911 1 1
6912 1 1
6913 1 1
6914 1 1
6915 1 1
6916 1 1
6917 1 1
6918 1 1
6919 1 1
6920 1 1
6921 1 1
6922 1 1
6923 1 1
6924 1 1
6925 1 1
6930 1 1
6931 1 1
6933 1 1
6937 1 1
6941 1 1
6945 1 1
6949 1 1
6953 1 1
6956 1 1
6959 1 1
6962 1 1
6965 1 1
6968 1 1
6972 1 1
6975 1 1
6978 1 1
6981 1 1
6984 1 1
6987 1 1
6988 1 1
6989 1 1
6990 1 1
6991 1 1
6992 1 1
6993 1 1
6994 1 1
6998 1 1
7001 1 1
7004 1 1
7007 1 1
7010 1 1
7013 1 1
7016 1 1
7019 1 1
7022 1 1
7025 1 1
7028 1 1
7031 1 1
7034 1 1
7037 1 1
7040 1 1
7043 1 1
7046 1 1
7049 1 1
7052 1 1
7055 1 1
7058 1 1
7061 1 1
7064 1 1
7067 1 1
7070 1 1
7071 1 1
7072 1 1
7073 1 1
7077 1 1
7078 1 1
7079 1 1
7080 1 1
7081 1 1
7082 1 1
7083 1 1
7084 1 1
7085 1 1
7086 1 1
7087 1 1
7088 1 1
7089 1 1
7090 1 1
7105 1 1
7107 1 1
7108 1 1
7110 1 1
7113 1 1
7116 1 1
7119 1 1
7122 1 1
7125 1 1
7128 1 1
7131 1 1
7134 1 1
7137 1 1
7140 1 1
7143 1 1
7146 1 1
7149 1 1
7152 1 1
7155 1 1
7158 1 1
7161 1 1
7164 1 1
7167 1 1
7170 1 1
7173 1 1
7176 1 1
7179 1 1
7182 1 1
7185 1 1
7188 1 1
7191 1 1
7194 1 1
7197 1 1
7200 1 1
7203 1 1
7206 1 1
7209 1 1
7224 1 1
7225 1 1


Cond Coverage for Module : sysrst_ctrl_reg_top
TotalCoveredPercent
Conditions53750794.41
Logical53750794.41
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
60-667592.63
6677-7105100.00

Branch Coverage for Module : sysrst_ctrl_reg_top
Line No.TotalCoveredPercent
Branches 84 84 100.00
TERNARY 6604 2 2 100.00
IF 70 3 3 100.00
CASE 6931 44 44 100.00
CASE 7108 35 35 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 6604 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T295,T296,T297
0 0 Covered T1,T4,T5


LineNo. Expression -1-: 6931 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T4,T5
addr_hit[1] Covered T1,T4,T5
addr_hit[2] Covered T1,T4,T5
addr_hit[3] Covered T1,T4,T5
addr_hit[4] Covered T1,T4,T5
addr_hit[5] Covered T1,T4,T5
addr_hit[6] Covered T1,T4,T5
addr_hit[7] Covered T1,T4,T5
addr_hit[8] Covered T1,T4,T5
addr_hit[9] Covered T1,T4,T5
addr_hit[10] Covered T1,T4,T5
addr_hit[11] Covered T1,T4,T5
addr_hit[12] Covered T1,T4,T5
addr_hit[13] Covered T1,T4,T5
addr_hit[14] Covered T1,T4,T5
addr_hit[15] Covered T1,T4,T5
addr_hit[16] Covered T1,T4,T5
addr_hit[17] Covered T1,T4,T5
addr_hit[18] Covered T1,T4,T5
addr_hit[19] Covered T1,T4,T5
addr_hit[20] Covered T1,T4,T5
addr_hit[21] Covered T1,T4,T5
addr_hit[22] Covered T1,T4,T5
addr_hit[23] Covered T1,T4,T5
addr_hit[24] Covered T1,T4,T5
addr_hit[25] Covered T1,T4,T5
addr_hit[26] Covered T1,T4,T5
addr_hit[27] Covered T1,T4,T5
addr_hit[28] Covered T1,T4,T5
addr_hit[29] Covered T1,T4,T5
addr_hit[30] Covered T1,T4,T5
addr_hit[31] Covered T1,T4,T5
addr_hit[32] Covered T1,T4,T5
addr_hit[33] Covered T1,T4,T5
addr_hit[34] Covered T1,T4,T5
addr_hit[35] Covered T1,T4,T5
addr_hit[36] Covered T1,T4,T5
addr_hit[37] Covered T1,T4,T5
addr_hit[38] Covered T1,T4,T5
addr_hit[39] Covered T1,T4,T5
addr_hit[40] Covered T1,T4,T5
addr_hit[41] Covered T1,T4,T5
addr_hit[42] Covered T1,T4,T5
default Covered T1,T4,T5


LineNo. Expression -1-: 7108 case (1'b1)

Branches:
-1-StatusTests
addr_hit[5] Covered T1,T4,T5
addr_hit[6] Covered T1,T4,T5
addr_hit[7] Covered T1,T4,T5
addr_hit[8] Covered T1,T4,T5
addr_hit[9] Covered T1,T4,T5
addr_hit[11] Covered T1,T4,T5
addr_hit[12] Covered T1,T4,T5
addr_hit[13] Covered T1,T4,T5
addr_hit[14] Covered T1,T4,T5
addr_hit[15] Covered T1,T4,T5
addr_hit[17] Covered T1,T4,T5
addr_hit[18] Covered T1,T4,T5
addr_hit[19] Covered T1,T4,T5
addr_hit[20] Covered T1,T4,T5
addr_hit[21] Covered T1,T4,T5
addr_hit[22] Covered T1,T4,T5
addr_hit[23] Covered T1,T4,T5
addr_hit[24] Covered T1,T4,T5
addr_hit[25] Covered T1,T4,T5
addr_hit[26] Covered T1,T4,T5
addr_hit[27] Covered T1,T4,T5
addr_hit[28] Covered T1,T4,T5
addr_hit[29] Covered T1,T4,T5
addr_hit[30] Covered T1,T4,T5
addr_hit[31] Covered T1,T4,T5
addr_hit[32] Covered T1,T4,T5
addr_hit[33] Covered T1,T4,T5
addr_hit[34] Covered T1,T4,T5
addr_hit[35] Covered T1,T4,T5
addr_hit[36] Covered T1,T4,T5
addr_hit[37] Covered T1,T4,T5
addr_hit[38] Covered T1,T4,T5
addr_hit[39] Covered T1,T4,T5
addr_hit[40] Covered T1,T4,T5
default Covered T1,T4,T5


Assert Coverage for Module : sysrst_ctrl_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 1277240674 260738 0 0
reAfterRv 1277240674 260737 0 0
rePulse 1277240674 134064 0 0
wePulse 1277240674 126673 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 260738 0 0
T1 102256 545 0 0
T2 248674 545 0 0
T3 240086 11 0 0
T4 281603 427 0 0
T5 115176 511 0 0
T13 128064 426 0 0
T14 250527 63 0 0
T15 342330 15 0 0
T16 44781 8 0 0
T17 25470 122 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 260737 0 0
T1 102256 545 0 0
T2 248674 545 0 0
T3 240086 11 0 0
T4 281603 427 0 0
T5 115176 511 0 0
T13 128064 426 0 0
T14 250527 63 0 0
T15 342330 15 0 0
T16 44781 8 0 0
T17 25470 122 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 134064 0 0
T1 102256 404 0 0
T2 248674 404 0 0
T3 240086 6 0 0
T4 281603 3 0 0
T5 115176 390 0 0
T13 128064 3 0 0
T14 250527 2 0 0
T15 342330 8 0 0
T16 44781 2 0 0
T17 25470 62 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 126673 0 0
T1 102256 141 0 0
T2 248674 141 0 0
T3 240086 5 0 0
T4 281603 424 0 0
T5 115176 121 0 0
T13 128064 423 0 0
T14 250527 61 0 0
T15 342330 7 0 0
T16 44781 6 0 0
T17 25470 60 0 0

Line Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
TOTAL512512100.00
ALWAYS7044100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN12111100.00
ALWAYS29922100.00
CONT_ASSIGN32711100.00
ALWAYS33822100.00
CONT_ASSIGN36611100.00
ALWAYS37722100.00
CONT_ASSIGN40511100.00
ALWAYS41622100.00
CONT_ASSIGN44411100.00
ALWAYS45422100.00
CONT_ASSIGN48211100.00
ALWAYS49544100.00
CONT_ASSIGN52511100.00
ALWAYS5471313100.00
CONT_ASSIGN58611100.00
ALWAYS6121717100.00
CONT_ASSIGN65511100.00
ALWAYS67299100.00
CONT_ASSIGN70711100.00
ALWAYS72499100.00
CONT_ASSIGN75911100.00
ALWAYS7831515100.00
CONT_ASSIGN82411100.00
ALWAYS83522100.00
CONT_ASSIGN86311100.00
ALWAYS87533100.00
CONT_ASSIGN90411100.00
ALWAYS92077100.00
CONT_ASSIGN95311100.00
ALWAYS96866100.00
CONT_ASSIGN100011100.00
ALWAYS101566100.00
CONT_ASSIGN104711100.00
ALWAYS106266100.00
CONT_ASSIGN109411100.00
ALWAYS110966100.00
CONT_ASSIGN114111100.00
ALWAYS115222100.00
CONT_ASSIGN118011100.00
ALWAYS119122100.00
CONT_ASSIGN121911100.00
ALWAYS123022100.00
CONT_ASSIGN125811100.00
ALWAYS126922100.00
CONT_ASSIGN129711100.00
ALWAYS131266100.00
CONT_ASSIGN134411100.00
ALWAYS135966100.00
CONT_ASSIGN139111100.00
ALWAYS140666100.00
CONT_ASSIGN143811100.00
ALWAYS145366100.00
CONT_ASSIGN148511100.00
ALWAYS149622100.00
CONT_ASSIGN152411100.00
ALWAYS153522100.00
CONT_ASSIGN156311100.00
ALWAYS157422100.00
CONT_ASSIGN160211100.00
ALWAYS161322100.00
CONT_ASSIGN164111100.00
ALWAYS165555100.00
CONT_ASSIGN168611100.00
ALWAYS170055100.00
CONT_ASSIGN173111100.00
ALWAYS174555100.00
CONT_ASSIGN177611100.00
ALWAYS179055100.00
CONT_ASSIGN182111100.00
CONT_ASSIGN188411100.00
CONT_ASSIGN189811100.00
CONT_ASSIGN190411100.00
CONT_ASSIGN191811100.00
CONT_ASSIGN195211100.00
CONT_ASSIGN198311100.00
CONT_ASSIGN201511100.00
CONT_ASSIGN204711100.00
CONT_ASSIGN213411100.00
CONT_ASSIGN216511100.00
CONT_ASSIGN249411100.00
CONT_ASSIGN358511100.00
CONT_ASSIGN396811100.00
CONT_ASSIGN400011100.00
CONT_ASSIGN406011100.00
CONT_ASSIGN422911100.00
CONT_ASSIGN437011100.00
CONT_ASSIGN451111100.00
CONT_ASSIGN465211100.00
CONT_ASSIGN479311100.00
CONT_ASSIGN482511100.00
CONT_ASSIGN485711100.00
CONT_ASSIGN488911100.00
CONT_ASSIGN492111100.00
CONT_ASSIGN506211100.00
CONT_ASSIGN520311100.00
CONT_ASSIGN534411100.00
CONT_ASSIGN548511100.00
CONT_ASSIGN551711100.00
CONT_ASSIGN554911100.00
CONT_ASSIGN558111100.00
CONT_ASSIGN561311100.00
CONT_ASSIGN572711100.00
CONT_ASSIGN584111100.00
CONT_ASSIGN595511100.00
ALWAYS65584444100.00
CONT_ASSIGN660411100.00
ALWAYS660811100.00
CONT_ASSIGN665511100.00
CONT_ASSIGN665711100.00
CONT_ASSIGN665811100.00
CONT_ASSIGN666011100.00
CONT_ASSIGN666111100.00
CONT_ASSIGN666311100.00
CONT_ASSIGN666411100.00
CONT_ASSIGN666611100.00
CONT_ASSIGN666711100.00
CONT_ASSIGN666911100.00
CONT_ASSIGN667111100.00
CONT_ASSIGN667311100.00
CONT_ASSIGN667511100.00
CONT_ASSIGN667711100.00
CONT_ASSIGN667911100.00
CONT_ASSIGN668011100.00
CONT_ASSIGN668211100.00
CONT_ASSIGN669511100.00
CONT_ASSIGN671211100.00
CONT_ASSIGN672111100.00
CONT_ASSIGN673011100.00
CONT_ASSIGN674511100.00
CONT_ASSIGN674711100.00
CONT_ASSIGN675011100.00
CONT_ASSIGN675711100.00
CONT_ASSIGN676311100.00
CONT_ASSIGN676911100.00
CONT_ASSIGN677511100.00
CONT_ASSIGN678111100.00
CONT_ASSIGN678311100.00
CONT_ASSIGN678511100.00
CONT_ASSIGN678711100.00
CONT_ASSIGN678911100.00
CONT_ASSIGN679511100.00
CONT_ASSIGN680111100.00
CONT_ASSIGN680711100.00
CONT_ASSIGN681311100.00
CONT_ASSIGN681511100.00
CONT_ASSIGN681711100.00
CONT_ASSIGN681911100.00
CONT_ASSIGN682111100.00
CONT_ASSIGN682611100.00
CONT_ASSIGN683111100.00
CONT_ASSIGN683611100.00
CONT_ASSIGN684111100.00
CONT_ASSIGN684311100.00
CONT_ASSIGN684511100.00
CONT_ASSIGN684711100.00
CONT_ASSIGN684911100.00
CONT_ASSIGN685011100.00
CONT_ASSIGN685211100.00
CONT_ASSIGN685411100.00
CONT_ASSIGN685611100.00
CONT_ASSIGN685811100.00
CONT_ASSIGN686011100.00
CONT_ASSIGN686211100.00
CONT_ASSIGN686411100.00
CONT_ASSIGN686611100.00
CONT_ASSIGN686811100.00
CONT_ASSIGN687011100.00
CONT_ASSIGN687211100.00
CONT_ASSIGN687411100.00
CONT_ASSIGN687611100.00
CONT_ASSIGN687811100.00
ALWAYS68824444100.00
ALWAYS69306868100.00
CONT_ASSIGN710511100.00
ALWAYS71073636100.00
CONT_ASSIGN722411100.00
CONT_ASSIGN722511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
79 1 1
91 1 1
92 1 1
120 1 1
121 1 1
299 1 1
300 1 1
327 1 1
338 1 1
339 1 1
366 1 1
377 1 1
378 1 1
405 1 1
416 1 1
417 1 1
444 1 1
454 1 1
455 1 1
482 1 1
495 1 1
496 1 1
497 1 1
498 1 1
525 1 1
547 1 1
548 1 1
549 1 1
550 1 1
551 1 1
552 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
586 1 1
612 1 1
613 1 1
614 1 1
615 1 1
616 1 1
617 1 1
618 1 1
619 1 1
620 1 1
621 1 1
622 1 1
623 1 1
624 1 1
625 1 1
626 1 1
627 1 1
628 1 1
655 1 1
672 1 1
673 1 1
674 1 1
675 1 1
676 1 1
677 1 1
678 1 1
679 1 1
680 1 1
707 1 1
724 1 1
725 1 1
726 1 1
727 1 1
728 1 1
729 1 1
730 1 1
731 1 1
732 1 1
759 1 1
783 1 1
784 1 1
785 1 1
786 1 1
787 1 1
788 1 1
789 1 1
790 1 1
791 1 1
792 1 1
793 1 1
794 1 1
795 1 1
796 1 1
797 1 1
824 1 1
835 1 1
836 1 1
863 1 1
875 1 1
876 1 1
877 1 1
904 1 1
920 1 1
921 1 1
922 1 1
923 1 1
924 1 1
925 1 1
926 1 1
953 1 1
968 1 1
969 1 1
970 1 1
971 1 1
972 1 1
973 1 1
1000 1 1
1015 1 1
1016 1 1
1017 1 1
1018 1 1
1019 1 1
1020 1 1
1047 1 1
1062 1 1
1063 1 1
1064 1 1
1065 1 1
1066 1 1
1067 1 1
1094 1 1
1109 1 1
1110 1 1
1111 1 1
1112 1 1
1113 1 1
1114 1 1
1141 1 1
1152 1 1
1153 1 1
1180 1 1
1191 1 1
1192 1 1
1219 1 1
1230 1 1
1231 1 1
1258 1 1
1269 1 1
1270 1 1
1297 1 1
1312 1 1
1313 1 1
1314 1 1
1315 1 1
1316 1 1
1317 1 1
1344 1 1
1359 1 1
1360 1 1
1361 1 1
1362 1 1
1363 1 1
1364 1 1
1391 1 1
1406 1 1
1407 1 1
1408 1 1
1409 1 1
1410 1 1
1411 1 1
1438 1 1
1453 1 1
1454 1 1
1455 1 1
1456 1 1
1457 1 1
1458 1 1
1485 1 1
1496 1 1
1497 1 1
1524 1 1
1535 1 1
1536 1 1
1563 1 1
1574 1 1
1575 1 1
1602 1 1
1613 1 1
1614 1 1
1641 1 1
1655 1 1
1656 1 1
1657 1 1
1658 1 1
1659 1 1
1686 1 1
1700 1 1
1701 1 1
1702 1 1
1703 1 1
1704 1 1
1731 1 1
1745 1 1
1746 1 1
1747 1 1
1748 1 1
1749 1 1
1776 1 1
1790 1 1
1791 1 1
1792 1 1
1793 1 1
1794 1 1
1821 1 1
1884 1 1
1898 1 1
1904 1 1
1918 1 1
1952 1 1
1983 1 1
2015 1 1
2047 1 1
2134 1 1
2165 1 1
2494 1 1
3585 1 1
3968 1 1
4000 1 1
4060 1 1
4229 1 1
4370 1 1
4511 1 1
4652 1 1
4793 1 1
4825 1 1
4857 1 1
4889 1 1
4921 1 1
5062 1 1
5203 1 1
5344 1 1
5485 1 1
5517 1 1
5549 1 1
5581 1 1
5613 1 1
5727 1 1
5841 1 1
5955 1 1
6558 1 1
6559 1 1
6560 1 1
6561 1 1
6562 1 1
6563 1 1
6564 1 1
6565 1 1
6566 1 1
6567 1 1
6568 1 1
6569 1 1
6570 1 1
6571 1 1
6572 1 1
6573 1 1
6574 1 1
6575 1 1
6576 1 1
6577 1 1
6578 1 1
6579 1 1
6580 1 1
6581 1 1
6582 1 1
6583 1 1
6584 1 1
6585 1 1
6586 1 1
6587 1 1
6588 1 1
6589 1 1
6590 1 1
6591 1 1
6592 1 1
6593 1 1
6594 1 1
6595 1 1
6596 1 1
6597 1 1
6598 1 1
6599 1 1
6600 1 1
6601 1 1
6604 1 1
6608 1 1
6655 1 1
6657 1 1
6658 1 1
6660 1 1
6661 1 1
6663 1 1
6664 1 1
6666 1 1
6667 1 1
6669 1 1
6671 1 1
6673 1 1
6675 1 1
6677 1 1
6679 1 1
6680 1 1
6682 1 1
6695 1 1
6712 1 1
6721 1 1
6730 1 1
6745 1 1
6747 1 1
6750 1 1
6757 1 1
6763 1 1
6769 1 1
6775 1 1
6781 1 1
6783 1 1
6785 1 1
6787 1 1
6789 1 1
6795 1 1
6801 1 1
6807 1 1
6813 1 1
6815 1 1
6817 1 1
6819 1 1
6821 1 1
6826 1 1
6831 1 1
6836 1 1
6841 1 1
6843 1 1
6845 1 1
6847 1 1
6849 1 1
6850 1 1
6852 1 1
6854 1 1
6856 1 1
6858 1 1
6860 1 1
6862 1 1
6864 1 1
6866 1 1
6868 1 1
6870 1 1
6872 1 1
6874 1 1
6876 1 1
6878 1 1
6882 1 1
6883 1 1
6884 1 1
6885 1 1
6886 1 1
6887 1 1
6888 1 1
6889 1 1
6890 1 1
6891 1 1
6892 1 1
6893 1 1
6894 1 1
6895 1 1
6896 1 1
6897 1 1
6898 1 1
6899 1 1
6900 1 1
6901 1 1
6902 1 1
6903 1 1
6904 1 1
6905 1 1
6906 1 1
6907 1 1
6908 1 1
6909 1 1
6910 1 1
6911 1 1
6912 1 1
6913 1 1
6914 1 1
6915 1 1
6916 1 1
6917 1 1
6918 1 1
6919 1 1
6920 1 1
6921 1 1
6922 1 1
6923 1 1
6924 1 1
6925 1 1
6930 1 1
6931 1 1
6933 1 1
6937 1 1
6941 1 1
6945 1 1
6949 1 1
6953 1 1
6956 1 1
6959 1 1
6962 1 1
6965 1 1
6968 1 1
6972 1 1
6975 1 1
6978 1 1
6981 1 1
6984 1 1
6987 1 1
6988 1 1
6989 1 1
6990 1 1
6991 1 1
6992 1 1
6993 1 1
6994 1 1
6998 1 1
7001 1 1
7004 1 1
7007 1 1
7010 1 1
7013 1 1
7016 1 1
7019 1 1
7022 1 1
7025 1 1
7028 1 1
7031 1 1
7034 1 1
7037 1 1
7040 1 1
7043 1 1
7046 1 1
7049 1 1
7052 1 1
7055 1 1
7058 1 1
7061 1 1
7064 1 1
7067 1 1
7070 1 1
7071 1 1
7072 1 1
7073 1 1
7077 1 1
7078 1 1
7079 1 1
7080 1 1
7081 1 1
7082 1 1
7083 1 1
7084 1 1
7085 1 1
7086 1 1
7087 1 1
7088 1 1
7089 1 1
7090 1 1
7105 1 1
7107 1 1
7108 1 1
7110 1 1
7113 1 1
7116 1 1
7119 1 1
7122 1 1
7125 1 1
7128 1 1
7131 1 1
7134 1 1
7137 1 1
7140 1 1
7143 1 1
7146 1 1
7149 1 1
7152 1 1
7155 1 1
7158 1 1
7161 1 1
7164 1 1
7167 1 1
7170 1 1
7173 1 1
7176 1 1
7179 1 1
7182 1 1
7185 1 1
7188 1 1
7191 1 1
7194 1 1
7197 1 1
7200 1 1
7203 1 1
7206 1 1
7209 1 1
7224 1 1
7225 1 1


Cond Coverage for Instance : tb.dut.u_reg
TotalCoveredPercent
Conditions53650694.40
Logical53650694.40
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
60-667592.61
6677-7105100.00

Branch Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
Branches 84 84 100.00
TERNARY 6604 2 2 100.00
IF 70 3 3 100.00
CASE 6931 44 44 100.00
CASE 7108 35 35 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 6604 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T295,T296,T297
0 0 Covered T1,T4,T5


LineNo. Expression -1-: 6931 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T4,T5
addr_hit[1] Covered T1,T4,T5
addr_hit[2] Covered T1,T4,T5
addr_hit[3] Covered T1,T4,T5
addr_hit[4] Covered T1,T4,T5
addr_hit[5] Covered T1,T4,T5
addr_hit[6] Covered T1,T4,T5
addr_hit[7] Covered T1,T4,T5
addr_hit[8] Covered T1,T4,T5
addr_hit[9] Covered T1,T4,T5
addr_hit[10] Covered T1,T4,T5
addr_hit[11] Covered T1,T4,T5
addr_hit[12] Covered T1,T4,T5
addr_hit[13] Covered T1,T4,T5
addr_hit[14] Covered T1,T4,T5
addr_hit[15] Covered T1,T4,T5
addr_hit[16] Covered T1,T4,T5
addr_hit[17] Covered T1,T4,T5
addr_hit[18] Covered T1,T4,T5
addr_hit[19] Covered T1,T4,T5
addr_hit[20] Covered T1,T4,T5
addr_hit[21] Covered T1,T4,T5
addr_hit[22] Covered T1,T4,T5
addr_hit[23] Covered T1,T4,T5
addr_hit[24] Covered T1,T4,T5
addr_hit[25] Covered T1,T4,T5
addr_hit[26] Covered T1,T4,T5
addr_hit[27] Covered T1,T4,T5
addr_hit[28] Covered T1,T4,T5
addr_hit[29] Covered T1,T4,T5
addr_hit[30] Covered T1,T4,T5
addr_hit[31] Covered T1,T4,T5
addr_hit[32] Covered T1,T4,T5
addr_hit[33] Covered T1,T4,T5
addr_hit[34] Covered T1,T4,T5
addr_hit[35] Covered T1,T4,T5
addr_hit[36] Covered T1,T4,T5
addr_hit[37] Covered T1,T4,T5
addr_hit[38] Covered T1,T4,T5
addr_hit[39] Covered T1,T4,T5
addr_hit[40] Covered T1,T4,T5
addr_hit[41] Covered T1,T4,T5
addr_hit[42] Covered T1,T4,T5
default Covered T1,T4,T5


LineNo. Expression -1-: 7108 case (1'b1)

Branches:
-1-StatusTests
addr_hit[5] Covered T1,T4,T5
addr_hit[6] Covered T1,T4,T5
addr_hit[7] Covered T1,T4,T5
addr_hit[8] Covered T1,T4,T5
addr_hit[9] Covered T1,T4,T5
addr_hit[11] Covered T1,T4,T5
addr_hit[12] Covered T1,T4,T5
addr_hit[13] Covered T1,T4,T5
addr_hit[14] Covered T1,T4,T5
addr_hit[15] Covered T1,T4,T5
addr_hit[17] Covered T1,T4,T5
addr_hit[18] Covered T1,T4,T5
addr_hit[19] Covered T1,T4,T5
addr_hit[20] Covered T1,T4,T5
addr_hit[21] Covered T1,T4,T5
addr_hit[22] Covered T1,T4,T5
addr_hit[23] Covered T1,T4,T5
addr_hit[24] Covered T1,T4,T5
addr_hit[25] Covered T1,T4,T5
addr_hit[26] Covered T1,T4,T5
addr_hit[27] Covered T1,T4,T5
addr_hit[28] Covered T1,T4,T5
addr_hit[29] Covered T1,T4,T5
addr_hit[30] Covered T1,T4,T5
addr_hit[31] Covered T1,T4,T5
addr_hit[32] Covered T1,T4,T5
addr_hit[33] Covered T1,T4,T5
addr_hit[34] Covered T1,T4,T5
addr_hit[35] Covered T1,T4,T5
addr_hit[36] Covered T1,T4,T5
addr_hit[37] Covered T1,T4,T5
addr_hit[38] Covered T1,T4,T5
addr_hit[39] Covered T1,T4,T5
addr_hit[40] Covered T1,T4,T5
default Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 1277240674 260738 0 0
reAfterRv 1277240674 260737 0 0
rePulse 1277240674 134064 0 0
wePulse 1277240674 126673 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 260738 0 0
T1 102256 545 0 0
T2 248674 545 0 0
T3 240086 11 0 0
T4 281603 427 0 0
T5 115176 511 0 0
T13 128064 426 0 0
T14 250527 63 0 0
T15 342330 15 0 0
T16 44781 8 0 0
T17 25470 122 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 260737 0 0
T1 102256 545 0 0
T2 248674 545 0 0
T3 240086 11 0 0
T4 281603 427 0 0
T5 115176 511 0 0
T13 128064 426 0 0
T14 250527 63 0 0
T15 342330 15 0 0
T16 44781 8 0 0
T17 25470 122 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 134064 0 0
T1 102256 404 0 0
T2 248674 404 0 0
T3 240086 6 0 0
T4 281603 3 0 0
T5 115176 390 0 0
T13 128064 3 0 0
T14 250527 2 0 0
T15 342330 8 0 0
T16 44781 2 0 0
T17 25470 62 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 1277240674 126673 0 0
T1 102256 141 0 0
T2 248674 141 0 0
T3 240086 5 0 0
T4 281603 424 0 0
T5 115176 121 0 0
T13 128064 423 0 0
T14 250527 61 0 0
T15 342330 7 0 0
T16 44781 6 0 0
T17 25470 60 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%