Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1331

1

T1

10

T2

7

T3

4

auto[1]

1764

1

T1

11

T3

13

T7

12

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2642

1

T1

20

T2

7

T3

17

auto[1]

453

1

T1

1

T7

8

T8

2

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2895

1

T1

20

T2

6

T3

17

auto[1]

200

1

T1

1

T2

1

T24

6

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2964

1

T1

21

T2

7

T3

15

auto[1]

131

1

T3

2

T25

1

T26

1

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2965

1

T1

21

T2

7

T3

17

auto[1]

130

1

T27

5

T26

1

T28

2

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2099

1

T1

2

T2

7

T3

17

auto[1]

996

1

T1

19

T7

23

T8

20

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1240

1

T1

7

T2

7

T3

3

auto[1]

1855

1

T1

14

T3

14

T7

18

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1404

1

T1

10

T2

7

T3

16

auto[1]

1691

1

T1

11

T3

1

T7

15

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1241

1

T1

5

T2

3

T3

3

auto[1]

1854

1

T1

16

T2

4

T3

14

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1228

1

T1

9

T2

7

T3

3

auto[1]

1867

1

T1

12

T3

14

T7

15

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T2

3

T3

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T24

1

T138

1

T99

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T8

1

T75

1

T25

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T8

1

T313

1

T314

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T75

1

T27

1

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T8

2

T99

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

52

1

T20

1

T56

2

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

18

1

T1

2

T7

1

T316

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T2

4

T75

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T1

1

T7

1

T24

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T3

1

T75

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T7

1

T24

1

T238

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T56

1

T25

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T8

1

T46

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T20

2

T56

3

T75

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

25

1

T7

1

T8

1

T56

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T92

1

T238

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T8

1

T24

1

T316

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T75

1

T92

1

T95

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T8

1

T24

2

T315

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T3

1

T27

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T7

1

T138

1

T316

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T27

1

T98

1

T151

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T46

1

T317

1

T318

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T27

1

T92

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T1

1

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T75

2

T92

2

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T1

1

T46

1

T319

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

78

1

T75

2

T27

1

T92

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

43

1

T1

2

T8

3

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T75

1

T317

1

T246

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

23

1

T8

2

T317

2

T314

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T56

1

T43

1

T238

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T237

1

T316

1

T320

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T7

1

T75

1

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T8

2

T46

1

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

48

1

T3

1

T72

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T313

2

T314

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

58

1

T56

2

T43

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

34

1

T1

1

T43

6

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T3

1

T42

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T1

2

T46

1

T316

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T42

1

T73

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T1

1

T46

1

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T72

1

T27

1

T239

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T318

3

T314

1

T321

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

151

1

T3

12

T56

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

38

1

T1

2

T7

1

T56

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T27

1

T238

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T1

1

T7

2

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

30

1

T20

1

T46

1

T75

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T316

1

T313

1

T314

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T27

1

T237

1

T25

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T7

3

T8

1

T314

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

89

1

T237

2

T239

1

T95

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

56

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T20

1

T43

1

T92

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

44

1

T43

3

T238

7

T316

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

79

1

T1

1

T20

8

T42

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

36

1

T7

1

T316

1

T313

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

62

1

T75

1

T72

9

T92

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

52

1

T1

2

T213

6

T318

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

249

1

T1

1

T75

1

T24

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T1

1

T7

1

T46

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T315

2

T243

1

T319

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T138

1

T313

1

T321

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T285

1

T322

1

T323

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T318

1

T243

1

T322

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T46

1

T315

1

T285

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T46

1

T24

1

T319

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T313

1

T248

1

T285

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T46

1

T24

1

T102

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T315

1

T248

1

T285

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T313

1

T315

1

T324

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T46

1

T325

2

T323

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T24

1

T317

1

T285

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T250

1

T323

1

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T46

1

T313

1

T326

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T8

1

T327

2

T328

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T24

1

T138

1

T102

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T43

1

T237

1

T322

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

2

1

T46

1

T164

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T7

2

T46

1

T316

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T46

1

T24

1

T321

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T1

1

T7

1

T46

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T315

3

T329

1

T322

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T138

1

T316

1

T324

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T46

1

T56

3

T316

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T7

1

T315

1

T248

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T321

2

T248

1

T330

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T248

1

T331

4

T324

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T237

2

T313

1

T102

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T238

4

T313

1

T315

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T138

1

T313

1

T314

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T313

1

T320

1

T248

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

101

1

T7

4

T8

1

T46

10

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T2

3

T3

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T24

1

T138

1

T99

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T8

1

T75

1

T25

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T8

1

T138

1

T313

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T75

1

T27

1

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T8

2

T99

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T20

1

T56

2

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T1

2

T7

1

T316

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T2

3

T75

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T1

1

T7

1

T46

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T3

1

T75

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T7

1

T46

1

T24

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T56

1

T25

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T8

1

T46

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50

1

T20

2

T56

3

T75

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35

1

T7

1

T8

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T92

1

T238

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T8

1

T24

1

T316

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T75

1

T92

1

T95

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T8

1

T24

2

T313

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T3

1

T27

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T7

1

T46

1

T138

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T27

1

T95

1

T98

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T46

1

T24

1

T317

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T27

1

T92

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T1

1

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T75

2

T92

2

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T1

1

T46

2

T313

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

77

1

T75

2

T27

1

T92

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T1

2

T8

4

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T75

1

T27

1

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

30

1

T8

2

T24

1

T138

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T56

1

T43

1

T238

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T43

1

T237

2

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T7

1

T75

1

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T8

2

T46

2

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T3

1

T72

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T7

2

T46

1

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T56

2

T43

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

40

1

T1

1

T46

1

T43

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

61

1

T3

1

T42

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T1

3

T7

1

T46

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T42

1

T73

1

T27

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T1

1

T46

1

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T72

1

T27

2

T239

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T138

1

T316

1

T318

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

143

1

T3

12

T56

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

51

1

T1

2

T7

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T27

2

T238

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T1

1

T7

3

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T20

1

T46

1

T75

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T316

1

T313

1

T314

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32

1

T27

1

T237

1

T25

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T7

3

T8

1

T314

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

79

1

T237

2

T239

1

T95

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

62

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T20

1

T43

1

T92

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

55

1

T43

3

T238

11

T316

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

80

1

T1

1

T20

8

T42

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T7

1

T138

1

T316

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

68

1

T75

1

T72

9

T92

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T1

2

T213

6

T318

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

155

1

T75

1

T27

5

T95

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

104

1

T1

1

T7

5

T8

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T332

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T333

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T334

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T335

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T138

2

T151

1

T314

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	31	65	67.71	31
Automatically Generated Cross Bins	96	31	65	67.71	31
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T2

3

T3

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T24

1

T138

1

T99

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T8

1

T75

1

T25

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T8

1

T138

1

T313

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T75

1

T27

1

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T8

2

T99

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T20

1

T56

2

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T1

2

T7

1

T316

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T2

4

T75

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T1

1

T7

1

T46

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T3

1

T75

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T7

1

T46

1

T24

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T56

1

T25

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T8

1

T46

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T20

2

T56

3

T75

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35

1

T7

1

T8

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T92

1

T238

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T8

1

T24

1

T316

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T75

1

T92

1

T95

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T8

1

T24

2

T313

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T3

1

T27

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T7

1

T46

1

T138

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T27

1

T95

1

T98

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T46

1

T24

1

T317

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T27

1

T92

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T1

1

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T75

2

T92

2

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T1

1

T46

2

T313

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

80

1

T75

2

T27

1

T92

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T1

2

T8

4

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T75

1

T27

1

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

30

1

T8

2

T24

1

T138

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

60

1

T56

1

T43

1

T238

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T43

1

T237

2

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T7

1

T75

1

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T8

2

T46

2

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T3

1

T72

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T7

2

T46

1

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

60

1

T56

2

T43

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T1

1

T46

1

T43

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

59

1

T3

1

T42

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T1

3

T7

1

T46

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T42

1

T73

1

T27

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T1

1

T46

1

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T72

1

T27

2

T239

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T138

1

T316

1

T318

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

151

1

T3

10

T56

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

51

1

T1

2

T7

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T27

2

T238

1

T25

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T1

1

T7

3

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T20

1

T46

1

T75

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T316

1

T313

1

T314

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31

1

T27

1

T237

1

T25

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T7

3

T8

1

T314

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

96

1

T237

2

T239

1

T95

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

62

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T20

1

T43

1

T92

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

56

1

T43

3

T238

11

T316

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

80

1

T1

1

T20

8

T42

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T7

1

T138

1

T316

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T75

1

T72

9

T92

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T1

2

T213

6

T318

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

181

1

T1

1

T75

1

T24

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

102

1

T1

1

T7

5

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T315

3

T319

2

T285

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

62

1

T2

3

T3

1

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T24

1

T138

1

T99

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T8

1

T75

1

T25

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T8

1

T138

1

T313

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T75

1

T27

1

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T8

2

T99

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T20

1

T56

2

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T1

2

T7

1

T316

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T2

4

T75

1

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T1

1

T7

1

T46

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T3

1

T75

1

T72

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

21

1

T7

1

T46

1

T24

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T56

1

T25

2

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

14

1

T8

1

T46

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T20

2

T56

3

T75

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35

1

T7

1

T8

1

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T92

1

T238

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T8

1

T24

1

T316

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

43

1

T75

1

T92

1

T95

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T8

1

T24

2

T313

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T3

1

T27

2

T25

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T7

1

T46

1

T138

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T27

1

T95

1

T98

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T46

1

T24

1

T317

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T27

1

T92

1

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T1

1

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

54

1

T75

2

T92

2

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T1

1

T46

2

T313

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

74

1

T75

2

T27

1

T92

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T1

2

T8

4

T243

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

54

1

T75

1

T27

1

T239

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

30

1

T8

2

T24

1

T138

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

61

1

T56

1

T43

1

T238

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T43

1

T237

2

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T7

1

T75

1

T92

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T8

2

T46

2

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T3

1

T72

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T7

2

T46

1

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

60

1

T56

2

T43

1

T73

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T1

1

T46

1

T43

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

62

1

T3

1

T42

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T1

3

T7

1

T46

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T42

1

T73

1

T27

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T1

1

T46

1

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T72

1

T27

2

T239

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T138

1

T316

1

T318

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

157

1

T3

12

T56

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

51

1

T1

2

T7

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T27

2

T238

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

16

1

T1

1

T7

3

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T20

1

T46

1

T75

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T316

1

T313

1

T314

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T27

1

T237

1

T25

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T7

3

T8

1

T314

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

94

1

T237

2

T239

1

T95

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

62

1

T1

1

T7

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T20

1

T43

1

T92

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

56

1

T43

3

T238

11

T316

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

84

1

T1

1

T20

8

T42

9

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

40

1

T7

1

T138

1

T316

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

68

1

T75

1

T72

9

T92

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T1

2

T213

6

T318

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

172

1

T1

1

T75

1

T24

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

104

1

T1

1

T7

5

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T336

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T314

2

T102

2

T250

4

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded