Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T163 |
10 |
| auto[1] |
10 |
1 |
|
|
T163 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T163 |
12 |
| auto[1] |
8 |
1 |
|
|
T163 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
7 |
1 |
|
|
T163 |
7 |
| auto[1] |
13 |
1 |
|
|
T163 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T163 |
11 |
| auto[1] |
9 |
1 |
|
|
T163 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[1] |
15 |
1 |
|
|
T163 |
15 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T163 |
10 |
| auto[1] |
10 |
1 |
|
|
T163 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T163 |
10 |
| auto[1] |
10 |
1 |
|
|
T163 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T163 |
9 |
| auto[1] |
11 |
1 |
|
|
T163 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
8 |
1 |
|
|
T163 |
8 |
| auto[1] |
12 |
1 |
|
|
T163 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T163 |
9 |
| auto[1] |
11 |
1 |
|
|
T163 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
9 |
1 |
|
|
T163 |
9 |
| auto[1] |
11 |
1 |
|
|
T163 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T163 |
10 |
| auto[1] |
10 |
1 |
|
|
T163 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
15 |
1 |
|
|
T163 |
15 |
| auto[1] |
5 |
1 |
|
|
T163 |
5 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T163 |
12 |
| auto[1] |
8 |
1 |
|
|
T163 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T163 |
10 |
| auto[1] |
10 |
1 |
|
|
T163 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T163 |
14 |
| auto[1] |
6 |
1 |
|
|
T163 |
6 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T163 |
13 |
| auto[1] |
7 |
1 |
|
|
T163 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T163 |
14 |
| auto[1] |
6 |
1 |
|
|
T163 |
6 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T163 |
12 |
| auto[1] |
8 |
1 |
|
|
T163 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T163 |
13 |
| auto[1] |
7 |
1 |
|
|
T163 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
11 |
1 |
|
|
T163 |
11 |
| auto[1] |
9 |
1 |
|
|
T163 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
16 |
1 |
|
|
T163 |
16 |
| auto[1] |
4 |
1 |
|
|
T163 |
4 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T163 |
12 |
| auto[1] |
8 |
1 |
|
|
T163 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
10 |
1 |
|
|
T163 |
10 |
| auto[1] |
10 |
1 |
|
|
T163 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
2 |
1 |
|
|
T163 |
2 |
| auto[0] |
auto[1] |
8 |
1 |
|
|
T163 |
8 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[1] |
auto[1] |
5 |
1 |
|
|
T163 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
6 |
1 |
|
|
T163 |
6 |
| auto[0] |
auto[1] |
8 |
1 |
|
|
T163 |
8 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[1] |
auto[1] |
1 |
1 |
|
|
T163 |
1 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
1 |
3 |
75.00 |
1 |
Automatically Generated Cross Bins for key1_inXval
Uncovered bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[1]] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[0] |
auto[1] |
8 |
1 |
|
|
T163 |
8 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T163 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T163 |
8 |
| auto[0] |
auto[1] |
6 |
1 |
|
|
T163 |
6 |
| auto[1] |
auto[0] |
2 |
1 |
|
|
T163 |
2 |
| auto[1] |
auto[1] |
4 |
1 |
|
|
T163 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[0] |
auto[1] |
7 |
1 |
|
|
T163 |
7 |
| auto[1] |
auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[1] |
auto[1] |
3 |
1 |
|
|
T163 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[0] |
auto[1] |
8 |
1 |
|
|
T163 |
8 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T163 |
4 |
| auto[1] |
auto[1] |
3 |
1 |
|
|
T163 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
7 |
1 |
|
|
T163 |
7 |
| auto[0] |
auto[1] |
9 |
1 |
|
|
T163 |
9 |
| auto[1] |
auto[0] |
2 |
1 |
|
|
T163 |
2 |
| auto[1] |
auto[1] |
2 |
1 |
|
|
T163 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T163 |
5 |
| auto[0] |
auto[1] |
7 |
1 |
|
|
T163 |
7 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T163 |
4 |
| auto[1] |
auto[1] |
4 |
1 |
|
|
T163 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
7 |
1 |
|
|
T163 |
7 |
| auto[0] |
auto[1] |
8 |
1 |
|
|
T163 |
8 |
| auto[1] |
auto[0] |
3 |
1 |
|
|
T163 |
3 |
| auto[1] |
auto[1] |
2 |
1 |
|
|
T163 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
12 |
1 |
|
|
T163 |
12 |
| auto[1] |
auto[1] |
8 |
1 |
|
|
T163 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
4 |
1 |
|
|
T163 |
4 |
| auto[0] |
auto[1] |
7 |
1 |
|
|
T163 |
7 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T163 |
4 |
| auto[1] |
auto[1] |
5 |
1 |
|
|
T163 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT |
| auto[0] |
auto[0] |
10 |
1 |
|
|
T163 |
10 |
| auto[1] |
auto[1] |
10 |
1 |
|
|
T163 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
803 |
1 |
|
|
T4 |
8 |
|
T6 |
7 |
|
T17 |
9 |
| auto[1] |
837 |
1 |
|
|
T4 |
12 |
|
T6 |
13 |
|
T17 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T4 |
9 |
|
T6 |
8 |
|
T17 |
11 |
| auto[1] |
851 |
1 |
|
|
T4 |
11 |
|
T6 |
12 |
|
T17 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T4 |
9 |
|
T6 |
13 |
|
T17 |
14 |
| auto[1] |
843 |
1 |
|
|
T4 |
11 |
|
T6 |
7 |
|
T17 |
6 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T4 |
15 |
|
T6 |
6 |
|
T17 |
11 |
| auto[1] |
868 |
1 |
|
|
T4 |
5 |
|
T6 |
14 |
|
T17 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
822 |
1 |
|
|
T4 |
13 |
|
T6 |
11 |
|
T17 |
13 |
| auto[1] |
818 |
1 |
|
|
T4 |
7 |
|
T6 |
9 |
|
T17 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
792 |
1 |
|
|
T4 |
9 |
|
T6 |
7 |
|
T17 |
12 |
| auto[1] |
848 |
1 |
|
|
T4 |
11 |
|
T6 |
13 |
|
T17 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T4 |
16 |
|
T6 |
7 |
|
T17 |
11 |
| auto[1] |
792 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T17 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T4 |
7 |
|
T6 |
12 |
|
T17 |
15 |
| auto[1] |
811 |
1 |
|
|
T4 |
13 |
|
T6 |
8 |
|
T17 |
5 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T4 |
10 |
|
T6 |
10 |
|
T17 |
6 |
| auto[1] |
800 |
1 |
|
|
T4 |
10 |
|
T6 |
10 |
|
T17 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
846 |
1 |
|
|
T4 |
14 |
|
T6 |
13 |
|
T17 |
16 |
| auto[1] |
794 |
1 |
|
|
T4 |
6 |
|
T6 |
7 |
|
T17 |
4 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T4 |
10 |
|
T6 |
17 |
|
T17 |
9 |
| auto[1] |
790 |
1 |
|
|
T4 |
10 |
|
T6 |
3 |
|
T17 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T4 |
9 |
|
T6 |
10 |
|
T17 |
10 |
| auto[1] |
810 |
1 |
|
|
T4 |
11 |
|
T6 |
10 |
|
T17 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T4 |
5 |
|
T6 |
11 |
|
T17 |
10 |
| auto[1] |
776 |
1 |
|
|
T4 |
15 |
|
T6 |
9 |
|
T17 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T4 |
9 |
|
T6 |
8 |
|
T17 |
11 |
| auto[1] |
851 |
1 |
|
|
T4 |
11 |
|
T6 |
12 |
|
T17 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
827 |
1 |
|
|
T4 |
4 |
|
T6 |
13 |
|
T17 |
7 |
| auto[1] |
813 |
1 |
|
|
T4 |
16 |
|
T6 |
7 |
|
T17 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
786 |
1 |
|
|
T4 |
10 |
|
T6 |
8 |
|
T17 |
12 |
| auto[1] |
854 |
1 |
|
|
T4 |
10 |
|
T6 |
12 |
|
T17 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T4 |
7 |
|
T6 |
12 |
|
T17 |
11 |
| auto[1] |
801 |
1 |
|
|
T4 |
13 |
|
T6 |
8 |
|
T17 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T4 |
7 |
|
T6 |
8 |
|
T17 |
6 |
| auto[1] |
851 |
1 |
|
|
T4 |
13 |
|
T6 |
12 |
|
T17 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
807 |
1 |
|
|
T4 |
3 |
|
T6 |
13 |
|
T17 |
8 |
| auto[1] |
833 |
1 |
|
|
T4 |
17 |
|
T6 |
7 |
|
T17 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T4 |
12 |
|
T6 |
8 |
|
T17 |
12 |
| auto[1] |
834 |
1 |
|
|
T4 |
8 |
|
T6 |
12 |
|
T17 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
800 |
1 |
|
|
T4 |
11 |
|
T6 |
9 |
|
T17 |
11 |
| auto[1] |
840 |
1 |
|
|
T4 |
9 |
|
T6 |
11 |
|
T17 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
800 |
1 |
|
|
T4 |
10 |
|
T6 |
8 |
|
T17 |
10 |
| auto[1] |
840 |
1 |
|
|
T4 |
10 |
|
T6 |
12 |
|
T17 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T4 |
10 |
|
T6 |
10 |
|
T17 |
7 |
| auto[1] |
806 |
1 |
|
|
T4 |
10 |
|
T6 |
10 |
|
T17 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T4 |
9 |
|
T6 |
10 |
|
T17 |
10 |
| auto[1] |
810 |
1 |
|
|
T4 |
11 |
|
T6 |
10 |
|
T17 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
412 |
1 |
|
|
T4 |
2 |
|
T6 |
9 |
|
T17 |
6 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T4 |
2 |
|
T6 |
4 |
|
T17 |
1 |
| auto[1] |
auto[0] |
385 |
1 |
|
|
T4 |
7 |
|
T6 |
4 |
|
T17 |
8 |
| auto[1] |
auto[1] |
428 |
1 |
|
|
T4 |
9 |
|
T6 |
3 |
|
T17 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
379 |
1 |
|
|
T4 |
8 |
|
T6 |
3 |
|
T17 |
7 |
| auto[0] |
auto[1] |
407 |
1 |
|
|
T4 |
2 |
|
T6 |
5 |
|
T17 |
5 |
| auto[1] |
auto[0] |
393 |
1 |
|
|
T4 |
7 |
|
T6 |
3 |
|
T17 |
4 |
| auto[1] |
auto[1] |
461 |
1 |
|
|
T4 |
3 |
|
T6 |
9 |
|
T17 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
421 |
1 |
|
|
T4 |
6 |
|
T6 |
7 |
|
T17 |
7 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T4 |
1 |
|
T6 |
5 |
|
T17 |
4 |
| auto[1] |
auto[0] |
401 |
1 |
|
|
T4 |
7 |
|
T6 |
4 |
|
T17 |
6 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T4 |
6 |
|
T6 |
4 |
|
T17 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
381 |
1 |
|
|
T4 |
4 |
|
T6 |
3 |
|
T17 |
4 |
| auto[0] |
auto[1] |
408 |
1 |
|
|
T4 |
3 |
|
T6 |
5 |
|
T17 |
2 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T4 |
5 |
|
T6 |
4 |
|
T17 |
8 |
| auto[1] |
auto[1] |
440 |
1 |
|
|
T4 |
8 |
|
T6 |
8 |
|
T17 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
395 |
1 |
|
|
T4 |
3 |
|
T6 |
5 |
|
T17 |
5 |
| auto[0] |
auto[1] |
412 |
1 |
|
|
T6 |
8 |
|
T17 |
3 |
|
T38 |
3 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T4 |
13 |
|
T6 |
2 |
|
T17 |
6 |
| auto[1] |
auto[1] |
380 |
1 |
|
|
T4 |
4 |
|
T6 |
5 |
|
T17 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
385 |
1 |
|
|
T4 |
3 |
|
T6 |
5 |
|
T17 |
9 |
| auto[0] |
auto[1] |
421 |
1 |
|
|
T4 |
9 |
|
T6 |
3 |
|
T17 |
3 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T4 |
4 |
|
T6 |
7 |
|
T17 |
6 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T4 |
4 |
|
T6 |
5 |
|
T17 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
420 |
1 |
|
|
T4 |
6 |
|
T6 |
6 |
|
T17 |
9 |
| auto[0] |
auto[1] |
380 |
1 |
|
|
T4 |
4 |
|
T6 |
2 |
|
T17 |
1 |
| auto[1] |
auto[0] |
426 |
1 |
|
|
T4 |
8 |
|
T6 |
7 |
|
T17 |
7 |
| auto[1] |
auto[1] |
414 |
1 |
|
|
T4 |
2 |
|
T6 |
5 |
|
T17 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T4 |
4 |
|
T6 |
9 |
|
T17 |
4 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T4 |
6 |
|
T6 |
1 |
|
T17 |
3 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T4 |
6 |
|
T6 |
8 |
|
T17 |
5 |
| auto[1] |
auto[1] |
395 |
1 |
|
|
T4 |
4 |
|
T6 |
2 |
|
T17 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T4 |
1 |
|
T6 |
5 |
|
T17 |
4 |
| auto[0] |
auto[1] |
437 |
1 |
|
|
T4 |
4 |
|
T6 |
6 |
|
T17 |
6 |
| auto[1] |
auto[0] |
376 |
1 |
|
|
T4 |
7 |
|
T6 |
2 |
|
T17 |
5 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T4 |
8 |
|
T6 |
7 |
|
T17 |
5 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
789 |
1 |
|
|
T4 |
9 |
|
T6 |
8 |
|
T17 |
11 |
| auto[1] |
auto[1] |
851 |
1 |
|
|
T4 |
11 |
|
T6 |
12 |
|
T17 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
412 |
1 |
|
|
T4 |
6 |
|
T6 |
5 |
|
T17 |
4 |
| auto[0] |
auto[1] |
388 |
1 |
|
|
T4 |
5 |
|
T6 |
4 |
|
T17 |
7 |
| auto[1] |
auto[0] |
428 |
1 |
|
|
T4 |
4 |
|
T6 |
5 |
|
T17 |
2 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T4 |
5 |
|
T6 |
6 |
|
T17 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
830 |
1 |
|
|
T4 |
9 |
|
T6 |
10 |
|
T17 |
10 |
| auto[1] |
auto[1] |
810 |
1 |
|
|
T4 |
11 |
|
T6 |
10 |
|
T17 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T6 |
11 |
|
T49 |
12 |
|
T36 |
9 |
| auto[1] |
158 |
1 |
|
|
T6 |
9 |
|
T49 |
8 |
|
T36 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T6 |
9 |
|
T49 |
9 |
|
T36 |
9 |
| auto[1] |
167 |
1 |
|
|
T6 |
11 |
|
T49 |
11 |
|
T36 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T6 |
12 |
|
T49 |
10 |
|
T36 |
6 |
| auto[1] |
156 |
1 |
|
|
T6 |
8 |
|
T49 |
10 |
|
T36 |
14 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T6 |
10 |
|
T49 |
12 |
|
T36 |
10 |
| auto[1] |
162 |
1 |
|
|
T6 |
10 |
|
T49 |
8 |
|
T36 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
152 |
1 |
|
|
T6 |
11 |
|
T49 |
10 |
|
T36 |
10 |
| auto[1] |
168 |
1 |
|
|
T6 |
9 |
|
T49 |
10 |
|
T36 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T6 |
12 |
|
T49 |
14 |
|
T36 |
11 |
| auto[1] |
163 |
1 |
|
|
T6 |
8 |
|
T49 |
6 |
|
T36 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T6 |
13 |
|
T49 |
9 |
|
T36 |
10 |
| auto[1] |
159 |
1 |
|
|
T6 |
7 |
|
T49 |
11 |
|
T36 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T6 |
8 |
|
T49 |
8 |
|
T36 |
11 |
| auto[1] |
156 |
1 |
|
|
T6 |
12 |
|
T49 |
12 |
|
T36 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
152 |
1 |
|
|
T6 |
13 |
|
T49 |
10 |
|
T36 |
9 |
| auto[1] |
168 |
1 |
|
|
T6 |
7 |
|
T49 |
10 |
|
T36 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T6 |
13 |
|
T49 |
12 |
|
T36 |
10 |
| auto[1] |
155 |
1 |
|
|
T6 |
7 |
|
T49 |
8 |
|
T36 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T6 |
9 |
|
T49 |
11 |
|
T36 |
11 |
| auto[1] |
153 |
1 |
|
|
T6 |
11 |
|
T49 |
9 |
|
T36 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T6 |
13 |
|
T49 |
11 |
|
T36 |
7 |
| auto[1] |
172 |
1 |
|
|
T6 |
7 |
|
T49 |
9 |
|
T36 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T6 |
8 |
|
T49 |
8 |
|
T36 |
11 |
| auto[1] |
167 |
1 |
|
|
T6 |
12 |
|
T49 |
12 |
|
T36 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T6 |
9 |
|
T49 |
9 |
|
T36 |
9 |
| auto[1] |
167 |
1 |
|
|
T6 |
11 |
|
T49 |
11 |
|
T36 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T6 |
6 |
|
T49 |
10 |
|
T36 |
9 |
| auto[1] |
170 |
1 |
|
|
T6 |
14 |
|
T49 |
10 |
|
T36 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T6 |
10 |
|
T49 |
16 |
|
T36 |
13 |
| auto[1] |
162 |
1 |
|
|
T6 |
10 |
|
T49 |
4 |
|
T36 |
7 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
178 |
1 |
|
|
T6 |
11 |
|
T49 |
11 |
|
T36 |
17 |
| auto[1] |
142 |
1 |
|
|
T6 |
9 |
|
T49 |
9 |
|
T36 |
3 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T6 |
8 |
|
T49 |
9 |
|
T36 |
12 |
| auto[1] |
159 |
1 |
|
|
T6 |
12 |
|
T49 |
11 |
|
T36 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T6 |
13 |
|
T49 |
9 |
|
T36 |
5 |
| auto[1] |
162 |
1 |
|
|
T6 |
7 |
|
T49 |
11 |
|
T36 |
15 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
167 |
1 |
|
|
T6 |
8 |
|
T49 |
10 |
|
T36 |
10 |
| auto[1] |
153 |
1 |
|
|
T6 |
12 |
|
T49 |
10 |
|
T36 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T6 |
6 |
|
T49 |
7 |
|
T36 |
14 |
| auto[1] |
174 |
1 |
|
|
T6 |
14 |
|
T49 |
13 |
|
T36 |
6 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T6 |
8 |
|
T49 |
6 |
|
T36 |
7 |
| auto[1] |
166 |
1 |
|
|
T6 |
12 |
|
T49 |
14 |
|
T36 |
13 |