Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T6 |
10 |
|
T49 |
9 |
|
T36 |
8 |
| auto[1] |
174 |
1 |
|
|
T6 |
10 |
|
T49 |
11 |
|
T36 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T6 |
13 |
|
T49 |
11 |
|
T36 |
7 |
| auto[1] |
172 |
1 |
|
|
T6 |
7 |
|
T49 |
9 |
|
T36 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
82 |
1 |
|
|
T6 |
4 |
|
T49 |
6 |
|
T36 |
4 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T6 |
2 |
|
T49 |
4 |
|
T36 |
5 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T6 |
8 |
|
T49 |
4 |
|
T36 |
2 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T6 |
6 |
|
T49 |
6 |
|
T36 |
9 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T6 |
5 |
|
T49 |
10 |
|
T36 |
8 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T6 |
5 |
|
T49 |
6 |
|
T36 |
5 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T6 |
5 |
|
T49 |
2 |
|
T36 |
2 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T6 |
5 |
|
T49 |
2 |
|
T36 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
87 |
1 |
|
|
T6 |
7 |
|
T49 |
6 |
|
T36 |
9 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T6 |
4 |
|
T49 |
5 |
|
T36 |
8 |
| auto[1] |
auto[0] |
65 |
1 |
|
|
T6 |
4 |
|
T49 |
4 |
|
T36 |
1 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T6 |
5 |
|
T49 |
5 |
|
T36 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T6 |
6 |
|
T49 |
7 |
|
T36 |
7 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T6 |
2 |
|
T49 |
2 |
|
T36 |
5 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T6 |
6 |
|
T49 |
7 |
|
T36 |
4 |
| auto[1] |
auto[1] |
83 |
1 |
|
|
T6 |
6 |
|
T49 |
4 |
|
T36 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T6 |
10 |
|
T49 |
4 |
|
T36 |
2 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T6 |
3 |
|
T49 |
5 |
|
T36 |
3 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T6 |
3 |
|
T49 |
5 |
|
T36 |
8 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T6 |
4 |
|
T49 |
6 |
|
T36 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
87 |
1 |
|
|
T6 |
5 |
|
T49 |
4 |
|
T36 |
5 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T6 |
3 |
|
T49 |
6 |
|
T36 |
5 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T6 |
3 |
|
T49 |
4 |
|
T36 |
6 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T6 |
9 |
|
T49 |
6 |
|
T36 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T6 |
6 |
|
T49 |
4 |
|
T36 |
6 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T6 |
2 |
|
T49 |
2 |
|
T36 |
1 |
| auto[1] |
auto[0] |
81 |
1 |
|
|
T6 |
7 |
|
T49 |
8 |
|
T36 |
4 |
| auto[1] |
auto[1] |
85 |
1 |
|
|
T6 |
5 |
|
T49 |
6 |
|
T36 |
9 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
81 |
1 |
|
|
T6 |
5 |
|
T49 |
5 |
|
T36 |
7 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T6 |
5 |
|
T49 |
4 |
|
T36 |
1 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T6 |
4 |
|
T49 |
6 |
|
T36 |
4 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T6 |
6 |
|
T49 |
5 |
|
T36 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T6 |
4 |
|
T49 |
6 |
|
T36 |
6 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T6 |
4 |
|
T49 |
2 |
|
T36 |
5 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T6 |
7 |
|
T49 |
6 |
|
T36 |
3 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T6 |
5 |
|
T49 |
6 |
|
T36 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
153 |
1 |
|
|
T6 |
9 |
|
T49 |
9 |
|
T36 |
9 |
| auto[1] |
auto[1] |
167 |
1 |
|
|
T6 |
11 |
|
T49 |
11 |
|
T36 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T6 |
3 |
|
T49 |
5 |
|
T36 |
6 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T6 |
3 |
|
T49 |
2 |
|
T36 |
8 |
| auto[1] |
auto[0] |
87 |
1 |
|
|
T6 |
10 |
|
T49 |
5 |
|
T36 |
3 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T6 |
4 |
|
T49 |
8 |
|
T36 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
148 |
1 |
|
|
T6 |
13 |
|
T49 |
11 |
|
T36 |
7 |
| auto[1] |
auto[1] |
172 |
1 |
|
|
T6 |
7 |
|
T49 |
9 |
|
T36 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |