Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1503

1

T1

6

T6

24

T3

18

auto[1]

571

1

T1

8

T3

10

T7

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1476

1

T1

6

T6

24

T3

25

auto[1]

598

1

T1

8

T3

3

T7

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1543

1

T1

12

T6

24

T3

21

auto[1]

531

1

T1

2

T3

7

T7

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1559

1

T1

8

T6

12

T3

28

auto[1]

515

1

T1

6

T6

12

T7

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1941

1

T1

14

T6

18

T3

28

auto[1]

133

1

T6

6

T26

5

T46

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1952

1

T1

14

T6

12

T3

28

auto[1]

122

1

T6

12

T46

2

T34

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1938

1

T1

14

T6

21

T3

25

auto[1]

136

1

T6

3

T3

3

T34

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1828

1

T1

14

T6

24

T3

25

auto[1]

246

1

T3

3

T26

5

T46

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1886

1

T1

14

T6

12

T3

18

auto[1]

188

1

T6

12

T3

10

T46

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1535

1

T1

6

T6

24

T3

28

auto[1]

539

1

T1

8

T7

2

T9

11

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	854	1			T1	14		T7	6		T9	11
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	36	1			T26	5		T46	3		T88	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	61	1			T3	6		T46	2		T66	9
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	21	1			T248	1		T329	14		T344	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	124	1			T26	5		T345	1		T255	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	15	1			T67	1		T346	6		T347	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	15	1			T34	2		T254	1		T348	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	35	1			T247	8		T349	1		T350	8
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T34	3		T347	3		T351	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	20	1			T246	4		T248	1		T254	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T328	2		T346	3		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T34	1		T345	1		T350	7
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	7	1			T352	7		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	11	1			T3	2		T66	5		T346	4
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	3	1			T353	3		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	33	1			T67	3		T248	2		T344	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	10	1			T66	5		T354	4		T355	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	20	1			T6	6		T46	1		T326	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T6	3		T356	3		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	15	1			T46	1		T34	1		T86	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T85	4		T350	3		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	6	1			T346	3		T357	1		T358	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T345	1		T359	2		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T360	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T6	3		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T357	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

143

1

T46

1

T78

1

T255

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

76

1

T9

7

T46

1

T85

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T26

5

T34

1

T42

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

86

1

T6

12

T46

3

T247

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

45

1

T32

6

T254

3

T349

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

61

1

T1

6

T50

1

T66

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

19

1

T206

3

T257

1

T330

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T67

1

T248

1

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

48

1

T3

6

T7

3

T46

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

55

1

T34

1

T86

2

T350

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T33

2

T324

4

T183

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

49

1

T50

1

T248

2

T88

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T246

5

T252

1

T251

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

43

1

T9

4

T10

4

T249

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T42

1

T251

1

T361

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

115

1

T66

5

T329

7

T346

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T1

6

T3

2

T248

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T249

5

T345

1

T362

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T363

2

T170

4

T364

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T34

3

T114

4

T328

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T66

9

T42

1

T246

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T364

2

T365

5

T366

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T249

1

T250

2

T124

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

84

1

T26

5

T34

2

T106

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T7

2

T10

1

T206

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T251

1

T329

17

T213

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T1

2

T10

1

T256

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

12

1

T106

3

T328

3

T366

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T90

1

T347

2

T335

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

15

1

T7

1

T32

4

T106

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T91

1

T330

2

T367

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded