Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T22

9

T48

13

T55

13

auto[1]

1128

1

T22

11

T48

7

T55

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T22

6

T48

4

T55

4

from_0to1

552

1

T22

5

T48

5

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T22

10

T48

8

T55

9

auto[1]

1110

1

T22

10

T48

12

T55

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T22

13

T48

9

T55

9

auto[1]

1157

1

T22

7

T48

11

T55

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T55

2

T57

2

T107

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T48

1

T57

1

T107

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T22

1

T57

3

T107

3

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T55

1

T65

2

T102

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T22

2

T65

1

T102

1

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T22

1

T48

2

T55

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T22

1

T48

2

T55

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T57

1

T102

1

T42

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T22

3

T384

2

T42

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T48

2

T107

1

T297

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T22

1

T48

1

T384

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T22

1

T55

1

T65

3

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T55

1

T65

1

T107

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T65

1

T384

1

T42

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T48

1

T57

1

T65

2

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T22

1

T55

1

T107

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T22

5

T48

9

T55

10

auto[1]

1114

1

T22

15

T48

11

T55

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T22

5

T48

6

T55

5

from_0to1

548

1

T22

5

T48

6

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T22

10

T48

11

T55

12

auto[1]

1089

1

T22

10

T48

9

T55

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T22

12

T48

12

T55

11

auto[1]

1074

1

T22

8

T48

8

T55

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T57

1

T65

1

T42

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T22

1

T48

1

T107

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T22

2

T48

1

T55

1

auto[0]

from_1to0

auto[1]

auto[1]

46

1

T48

1

T55

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T55

1

T102

1

T42

2

auto[0]

from_0to1

auto[0]

auto[1]

85

1

T55

2

T57

1

T384

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T22

1

T65

1

T107

2

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T48

2

T57

2

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T55

1

T57

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T22

1

T48

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T22

1

T48

1

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T48

1

T55

1

T107

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T22

1

T48

2

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T48

2

T57

1

T65

2

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T22

2

T57

1

T102

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T22

1

T55

1

T107

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T22

8

T48

6

T55

8

auto[1]

1160

1

T22

12

T48

14

T55

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T22

6

T48

4

T55

6

from_0to1

530

1

T22

6

T48

4

T55

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T22

10

T48

12

T55

14

auto[1]

1118

1

T22

10

T48

8

T55

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T22

8

T48

14

T55

10

auto[1]

1090

1

T22

12

T48

6

T55

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T48

1

T107

1

T42

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T55

1

T107

1

T102

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T22

1

T65

2

T384

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T22

1

T55

1

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T55

1

T57

1

T65

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T22

3

T55

1

T102

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T22

1

T55

1

T57

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T107

2

T296

1

T385

2

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T22

1

T48

1

T55

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T55

1

T57

1

T65

2

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T22

1

T55

2

T107

2

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T22

2

T48

2

T57

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T48

1

T55

2

T107

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T22

1

T48

1

T55

2

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T22

1

T48

2

T102

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T65

1

T107

1

T297

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T22

13

T48

14

T55

10

auto[1]

1142

1

T22

7

T48

6

T55

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T22

3

T48

4

T55

5

from_0to1

538

1

T22

4

T48

3

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T22

11

T48

11

T55

10

auto[1]

1102

1

T22

9

T48

9

T55

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T22

12

T48

7

T55

7

auto[1]

1186

1

T22

8

T48

13

T55

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T48

1

T55

1

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T22

1

T48

1

T55

2

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T42

1

T297

1

T176

3

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T48

1

T55

1

T57

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T57

1

T65

2

T107

2

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T22

1

T48

1

T55

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T22

2

T57

1

T102

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T55

2

T57

2

T42

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T57

2

T42

2

T385

2

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T22

1

T57

1

T65

1

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T57

1

T107

1

T102

3

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T22

1

T48

1

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T57

1

T107

1

T42

1

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T48

1

T57

1

T107

2

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T22

1

T42

1

T296

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T48

1

T55

2

T102

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T22

10

T48

11

T55

9

auto[1]

1145

1

T22

10

T48

9

T55

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T22

5

T48

5

T55

5

from_0to1

545

1

T22

5

T48

5

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T22

12

T48

12

T55

9

auto[1]

1085

1

T22

8

T48

8

T55

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1091

1

T22

7

T48

10

T55

11

auto[1]

1149

1

T22

13

T48

10

T55

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T22

1

T48

1

T384

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T22

1

T48

1

T55

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T55

1

T65

2

T107

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T48

2

T57

2

T65

2

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T22

1

T102

2

T384

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T22

1

T57

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T22

2

T55

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T48

1

T55

1

T57

3

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T55

1

T107

1

T102

1

auto[1]

from_1to0

auto[0]

auto[1]

95

1

T22

1

T57

1

T102

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T22

1

T55

1

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T22

1

T48

1

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T48

3

T107

2

T102

2

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T48

1

T55

2

T65

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T384

1

T296

1

T386

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T22

1

T107

2

T42

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T22

15

T48

9

T55

12

auto[1]

1137

1

T22

5

T48

11

T55

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T22

4

T48

5

T55

5

from_0to1

560

1

T22

3

T48

5

T55

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117

1

T22

12

T48

8

T55

10

auto[1]

1123

1

T22

8

T48

12

T55

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T22

9

T48

15

T55

10

auto[1]

1154

1

T22

11

T48

5

T55

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T57

1

T65

1

T384

1

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T22

1

T55

2

T57

2

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T48

1

T107

2

T384

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T22

1

T48

1

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T48

1

T42

1

T385

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T22

1

T55

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T22

1

T48

1

T57

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T22

1

T48

1

T55

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T22

1

T48

1

T65

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T22

1

T55

1

T65

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T48

2

T55

2

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

87

1

T57

1

T42

1

T296

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T48

1

T55

1

T57

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T57

1

T65

2

T384

2

auto[1]

from_0to1

auto[1]

auto[0]

86

1

T48

1

T55

1

T107

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T57

1

T65

2

T107

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1104

1

T22

7

T48

11

T55

10

auto[1]

1136

1

T22

13

T48

9

T55

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

526

1

T22

4

T48

5

T55

4

from_0to1

527

1

T22

5

T48

6

T55

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T22

3

T48

13

T55

10

auto[1]

1156

1

T22

17

T48

7

T55

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T22

12

T48

11

T55

10

auto[1]

1112

1

T22

8

T48

9

T55

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T48

1

T55

1

T65

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T65

1

T102

2

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T22

1

T57

1

T65

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T22

1

T55

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T48

2

T55

1

T107

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T55

1

T57

1

T65

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T22

3

T48

1

T57

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T57

2

T102

1

T296

3

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T57

2

T107

1

T384

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T48

1

T107

2

T296

2

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T55

1

T384

2

T42

5

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T22

2

T48

3

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T48

1

T55

1

T65

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T48

2

T57

1

T107

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T22

2

T55

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T65

1

T107

1

T384

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T22

9

T48

8

T55

9

auto[1]

1114

1

T22

11

T48

12

T55

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

554

1

T22

6

T48

6

T55

3

from_0to1

540

1

T22

5

T48

5

T55

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T22

12

T48

9

T55

9

auto[1]

1125

1

T22

8

T48

11

T55

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T22

15

T48

14

T55

12

auto[1]

1146

1

T22

5

T48

6

T55

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T22

1

T48

2

T57

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T107

2

T102

1

T42

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T48

1

T57

1

T102

1

auto[0]

from_1to0

auto[1]

auto[1]

87

1

T22

1

T55

1

T57

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T22

1

T48

1

T42

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T22

1

T384

2

T297

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T48

1

T65

1

T102

3

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T48

1

T65

1

T42

2

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T22

1

T55

1

T107

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T42

1

T297

1

T386

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T22

2

T48

3

T57

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T22

1

T55

1

T65

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T22

2

T57

1

T65

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T22

1

T48

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T48

1

T55

1

T107

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T55

1

T57

2

T107

1