Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146647	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110378

1

T5

2

T1

288

T6

309

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	129482	1			T5	2		T1	406		T6	261
values[0x0]	63336	1			T5	6		T1	98		T6	260
values[0x1]	64207	1			T5	3		T1	101		T6	294

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	118737	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138288

1

T5

3

T1

351

T6

372

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	930	1			T6	6		T10	13		T48	5
valid_sources[0x01]	912	1			T6	3		T7	8		T9	2
valid_sources[0x02]	1044	1			T1	1		T6	3		T7	2
valid_sources[0x03]	1864	1			T1	1		T7	3		T21	1
valid_sources[0x04]	817	1			T1	1		T9	2		T48	4
valid_sources[0x05]	751	1			T6	5		T2	1		T7	6
valid_sources[0x06]	795	1			T6	3		T7	1		T9	1
valid_sources[0x07]	929	1			T1	1		T7	1		T9	22
valid_sources[0x08]	927	1			T7	2		T21	3		T9	2
valid_sources[0x09]	876	1			T6	1		T7	3		T10	6
valid_sources[0x0a]	921	1			T1	3		T6	1		T7	3
valid_sources[0x0b]	674	1			T7	4		T9	1		T10	2
valid_sources[0x0c]	1166	1			T1	1		T6	7		T21	3
valid_sources[0x0d]	1069	1			T1	4		T7	5		T10	4
valid_sources[0x0e]	1025	1			T1	1		T7	4		T48	2
valid_sources[0x0f]	924	1			T1	1		T7	1		T21	1
valid_sources[0x10]	814	1			T1	9		T2	5		T7	1
valid_sources[0x11]	752	1			T1	5		T6	7		T2	1
valid_sources[0x12]	700	1			T1	13		T6	4		T7	1
valid_sources[0x13]	878	1			T1	1		T2	3		T10	12
valid_sources[0x14]	787	1			T2	5		T7	1		T9	4
valid_sources[0x15]	878	1			T6	1		T7	3		T9	5
valid_sources[0x16]	978	1			T1	8		T6	3		T2	6
valid_sources[0x17]	697	1			T1	2		T7	5		T48	1
valid_sources[0x18]	794	1			T7	5		T48	2		T37	4
valid_sources[0x19]	666	1			T1	4		T6	3		T7	1
valid_sources[0x1a]	938	1			T1	3		T6	14		T2	3
valid_sources[0x1b]	854	1			T6	2		T2	3		T7	1
valid_sources[0x1c]	829	1			T1	4		T6	3		T7	2
valid_sources[0x1d]	872	1			T6	3		T2	7		T7	2
valid_sources[0x1e]	783	1			T6	8		T2	21		T7	1
valid_sources[0x1f]	1949	1			T1	6		T6	3		T48	2
valid_sources[0x20]	1098	1			T1	1		T6	2		T2	2
valid_sources[0x21]	902	1			T1	2		T2	3		T9	3
valid_sources[0x22]	859	1			T7	3		T9	1		T48	1
valid_sources[0x23]	821	1			T1	1		T7	3		T9	2
valid_sources[0x24]	698	1			T5	11		T6	6		T2	2
valid_sources[0x25]	1508	1			T1	11		T6	6		T2	5
valid_sources[0x26]	834	1			T2	8		T7	1		T9	7
valid_sources[0x27]	1037	1			T1	2		T6	3		T2	7
valid_sources[0x28]	806	1			T6	2		T2	4		T10	11
valid_sources[0x29]	1027	1			T1	3		T6	14		T2	4
valid_sources[0x2a]	863	1			T1	2		T9	10		T10	8
valid_sources[0x2b]	742	1			T1	9		T6	2		T48	4
valid_sources[0x2c]	760	1			T1	5		T48	2		T37	4
valid_sources[0x2d]	983	1			T1	1		T6	4		T48	1
valid_sources[0x2e]	1234	1			T6	7		T9	4		T10	10
valid_sources[0x2f]	856	1			T7	4		T9	3		T48	3
valid_sources[0x30]	767	1			T1	9		T6	3		T24	2
valid_sources[0x31]	1037	1			T1	3		T6	17		T14	2
valid_sources[0x32]	2163	1			T1	4		T6	1		T37	1
valid_sources[0x33]	946	1			T1	11		T6	3		T48	6
valid_sources[0x34]	832	1			T7	4		T48	1		T37	3
valid_sources[0x35]	976	1			T6	17		T2	2		T7	3
valid_sources[0x36]	815	1			T1	9		T2	5		T7	1
valid_sources[0x37]	1094	1			T1	8		T6	21		T2	2
valid_sources[0x38]	800	1			T6	2		T9	13		T48	4
valid_sources[0x39]	936	1			T1	5		T2	4		T7	2
valid_sources[0x3a]	740	1			T6	7		T48	6		T37	3
valid_sources[0x3b]	1139	1			T6	3		T7	1		T10	7
valid_sources[0x3c]	1968	1			T10	5		T48	4		T37	3
valid_sources[0x3d]	947	1			T1	1		T13	7		T9	5
valid_sources[0x3e]	826	1			T1	30		T7	6		T48	7
valid_sources[0x3f]	985	1			T7	4		T9	7		T10	2
valid_sources[0x40]	2619	1			T7	5		T10	13		T48	6
valid_sources[0x41]	887	1			T1	4		T6	1		T48	1
valid_sources[0x42]	779	1			T6	4		T7	3		T10	3
valid_sources[0x43]	737	1			T1	1		T7	1		T10	11
valid_sources[0x44]	843	1			T1	3		T6	10		T2	1
valid_sources[0x45]	1173	1			T1	3		T7	1		T10	9
valid_sources[0x46]	754	1			T6	11		T2	6		T7	2
valid_sources[0x47]	1600	1			T1	4		T6	2		T7	2
valid_sources[0x48]	784	1			T6	7		T48	2		T26	4
valid_sources[0x49]	1043	1			T7	5		T101	2		T48	1
valid_sources[0x4a]	977	1			T1	4		T2	1		T7	3
valid_sources[0x4b]	1147	1			T6	11		T7	1		T21	1
valid_sources[0x4c]	1772	1			T1	5		T7	6		T10	1
valid_sources[0x4d]	751	1			T2	6		T7	1		T9	5
valid_sources[0x4e]	820	1			T6	2		T25	5		T9	1
valid_sources[0x4f]	785	1			T1	2		T6	5		T7	2
valid_sources[0x50]	713	1			T6	12		T7	6		T9	4
valid_sources[0x51]	744	1			T1	4		T6	3		T48	1
valid_sources[0x52]	944	1			T6	9		T2	2		T7	1
valid_sources[0x53]	944	1			T6	19		T55	10		T37	2
valid_sources[0x54]	920	1			T1	5		T7	2		T48	2
valid_sources[0x55]	774	1			T1	2		T17	3		T7	2
valid_sources[0x56]	786	1			T7	4		T48	8		T11	1
valid_sources[0x57]	878	1			T6	12		T21	1		T10	1
valid_sources[0x58]	873	1			T1	21		T6	3		T9	2
valid_sources[0x59]	928	1			T7	2		T9	2		T48	3
valid_sources[0x5a]	730	1			T1	18		T6	7		T21	1
valid_sources[0x5b]	884	1			T1	3		T7	3		T48	1
valid_sources[0x5c]	1006	1			T7	4		T9	7		T48	5
valid_sources[0x5d]	894	1			T2	2		T7	1		T9	5
valid_sources[0x5e]	841	1			T6	1		T22	122		T48	5
valid_sources[0x5f]	728	1			T1	6		T6	5		T2	3
valid_sources[0x60]	985	1			T6	7		T9	1		T10	4
valid_sources[0x61]	968	1			T1	9		T21	2		T48	5
valid_sources[0x62]	1540	1			T1	3		T6	10		T9	6
valid_sources[0x63]	1442	1			T6	8		T10	4		T48	6
valid_sources[0x64]	882	1			T6	10		T7	10		T21	1
valid_sources[0x65]	954	1			T6	3		T21	4		T9	2
valid_sources[0x66]	805	1			T6	13		T7	1		T9	2
valid_sources[0x67]	2976	1			T6	1		T7	2		T37	1
valid_sources[0x68]	694	1			T1	12		T7	1		T9	2
valid_sources[0x69]	1001	1			T1	17		T7	1		T48	2
valid_sources[0x6a]	1406	1			T1	15		T6	1		T7	4
valid_sources[0x6b]	859	1			T1	2		T48	4		T55	29
valid_sources[0x6c]	1380	1			T7	1		T9	7		T10	5
valid_sources[0x6d]	880	1			T6	2		T7	9		T10	7
valid_sources[0x6e]	1986	1			T1	2		T6	1		T2	6
valid_sources[0x6f]	1451	1			T1	1		T7	2		T21	1
valid_sources[0x70]	877	1			T1	5		T2	2		T48	1
valid_sources[0x71]	2055	1			T6	5		T7	2		T9	1
valid_sources[0x72]	670	1			T6	7		T7	4		T21	1
valid_sources[0x73]	1319	1			T1	2		T6	10		T2	7
valid_sources[0x74]	830	1			T1	2		T13	8		T7	1
valid_sources[0x75]	801	1			T6	3		T2	1		T17	3
valid_sources[0x76]	1163	1			T1	1		T6	4		T7	4
valid_sources[0x77]	1048	1			T1	3		T7	2		T9	9
valid_sources[0x78]	1236	1			T7	1		T9	1		T48	6
valid_sources[0x79]	865	1			T6	1		T7	1		T10	1
valid_sources[0x7a]	825	1			T1	3		T7	1		T9	5
valid_sources[0x7b]	816	1			T1	12		T6	2		T48	3
valid_sources[0x7c]	1008	1			T1	8		T2	1		T7	1
valid_sources[0x7d]	792	1			T1	7		T48	3		T37	1
valid_sources[0x7e]	1821	1			T1	2		T6	3		T2	7
valid_sources[0x7f]	1079	1			T21	1		T48	3		T37	2
valid_sources[0x80]	822	1			T10	14		T48	7		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

58111

1

T5

1

T1

196

T6

137

values[0x0]

all_enables

biggest_size

30671

1

T5

1

T1

45

T6

96

values[0x1]

all_enables

biggest_size

21596

1

T1

47

T6

76

T13

3