Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

119 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108

1

T28

1

T277

2

T279

2

auto[1]

453

1

T13

3

T17

3

T25

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163

1

T27

1

T28

5

T277

5

auto[1]

845

1

T13

3

T17

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144

1

T28

2

T277

2

T279

1

auto[1]

542

1

T13

2

T17

1

T25

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151

1

T27

1

T28

3

T277

2

auto[1]

476

1

T13

1

T17

2

T10

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145

1

T28

3

T277

2

T303

5

auto[1]

442

1

T13

3

T25

2

T10

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151

1

T27

1

T28

5

T277

2

auto[1]

476

1

T13

3

T17

3

T25

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144

1

T27

1

T28

4

T277

1

auto[1]

415

1

T13

3

T17

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

154

1

T28

3

T277

1

T279

1

auto[1]

480

1

T13

3

T17

2

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229

1

T27

1

T28

8

T277

3

auto[1]

2722

1

T1

20

T6

14

T3

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

196

1

T27

1

T28

7

T277

4

auto[1]

2715

1

T1

20

T6

14

T3

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

211

1

T27

1

T28

5

T277

1

auto[1]

2768

1

T1

20

T6

14

T3

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203

1

T27

1

T28

7

T277

2

auto[1]

2815

1

T1

20

T6

14

T3

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

268

1

T28

2

T277

2

T279

1

auto[1]

1590

1

T6

14

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

207

1

T28

3

T277

3

T279

1

auto[1]

1330

1

T3

17

T50

1

T46

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

246

1

T28

1

T277

1

T279

1

auto[1]

1379

1

T7

20

T10

20

T46

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

190

1

T28

3

T277

1

T279

1

auto[1]

1381

1

T1

20

T6

14

T50

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141

1

T27

1

T28

4

T277

2

auto[1]

1291

1

T1

20

T3

17

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148

1

T27

2

T28

3

T369

1

auto[1]

1242

1

T6

14

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152

1

T27

2

T28

3

T277

3

auto[1]

1464

1

T3

17

T10

20

T46

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164

1

T27

2

T28

3

T277

1

auto[1]

1421

1

T6

14

T7

20

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144

1

T27

1

T28

5

T279

2

auto[1]

1499

1

T6

14

T3

17

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97

1

T28

4

T277

2

T279

1

auto[1]

1437

1

T26

20

T32

20

T34

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111

1

T27

1

T28

5

T279

1

auto[1]

1333

1

T1

20

T9

20

T50

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109

1

T27

1

T28

2

T277

1

auto[1]

1384

1

T1

20

T6

14

T34

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129

1

T27

1

T28

6

T277

1

auto[1]

1477

1

T1

20

T7

20

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118

1

T27

1

T28

4

T279

1

auto[1]

1306

1

T1

20

T6

14

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120

1

T28

4

T277

3

T370

2

auto[1]

1346

1

T9

20

T10

20

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108

1

T28

6

T277

2

T279

1

auto[1]

1422

1

T1

20

T6

14

T50

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

196

1

T27

1

T28

6

T277

3

auto[1]

399

1

T27

7

T28

12

T29

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

206

1

T27

1

T28

6

T277

3

auto[1]

382

1

T27

9

T28

12

T29

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

229

1

T27

1

T28

5

T277

3

auto[1]

369

1

T27

8

T28

12

T29

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

215

1

T28

4

T277

5

T279

4

auto[1]

410

1

T27

8

T28

14

T29

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96

1

T28

3

T277

1

T279

2

auto[1]

517

1

T26

20

T66

19

T248

15

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

159

1

T28

4

T277

3

T279

2

auto[1]

554

1

T6

14

T46

13

T66

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

137

1

T27

1

T28

4

T277

2

auto[1]

581

1

T3

17

T34

17

T68

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118

1

T28

2

T277

1

T279

1

auto[1]

704

1

T3

17

T34

17

T245

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120

1

T27

1

T28

3

T277

2

auto[1]

740

1

T6

14

T3

17

T46

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106

1

T28

2

T277

1

T279

2

auto[1]

484

1

T6

14

T66

19

T67

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127

1

T28

2

T277

2

T279

2

auto[1]

687

1

T6

14

T26

20

T46

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120

1

T28

3

T277

2

T279

2

auto[1]

463

1

T6

14

T158

19

T329

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129

1

T28

3

T277

1

T279

1

auto[1]

660

1

T46

13

T34

17

T66

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129

1

T28

4

T277

1

T279

3

auto[1]

626

1

T6

14

T3

17

T66

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151

1

T27

1

T28

2

T277

1

auto[1]

557

1

T6

14

T46

13

T67

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

153

1

T27

1

T28

4

T277

3

auto[1]

533

1

T6

14

T3

17

T245

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158

1

T27

1

T28

4

T277

3

auto[1]

515

1

T68

10

T245

10

T247

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172

1

T28

4

T277

1

T279

1

auto[1]

609

1

T26

20

T34

17

T67

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

177

1

T28

5

T279

1

T303

23

auto[1]

592

1

T6

14

T34

17

T66

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101

1

T28

4

T305

1

T371

1

auto[1]

571

1

T3

17

T34

17

T68

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128

1

T28

2

T277

4

T305

2

auto[1]

479

1

T67

14

T245

10

T158

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129

1

T27

1

T28

2

T277

1

auto[1]

594

1

T6

14

T34

17

T66

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

123

1

T27

1

T28

4

T277

3

auto[1]

615

1

T6

14

T26

20

T66

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112

1

T27

1

T28

3

T277

3

auto[1]

638

1

T6

14

T46

13

T66

19

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

153

1

T28

3

T277

1

T279

2

auto[1]

1227

1

T3

17

T7

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

154

1

T28

3

T277

2

T305

2

auto[1]

1209

1

T3

17

T10

20

T26

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152

1

T27

1

T28

2

T277

4

auto[1]

1442

1

T7

20

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156

1

T28

1

T277

1

T303

8

auto[1]

1254

1

T6

14

T9

20

T50

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170

1

T28

2

T277

1

T279

2

auto[1]

1196

1

T9

20

T32

20

T34

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131

1

T27

1

T28

4

T277

4

auto[1]

1197

1

T1

20

T3

17

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147

1

T27

1

T28

4

T277

5

auto[1]

1236

1

T1

20

T7

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135

1

T27

1

T28

1

T277

1

auto[1]

1312

1

T1

20

T3

17

T7

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145

1

T28

3

T277

4

T369

1

auto[1]

1261

1

T6

14

T50

1

T26

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130

1

T27

1

T28

2

T277

3

auto[1]

1364

1

T1

20

T50

1

T26

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100

1

T28

2

T277

2

T279

1

auto[1]

1452

1

T7

20

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

135

1

T277

1

T279

2

T370

4

auto[1]

1463

1

T7

20

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

127

1

T28

1

T277

1

T370

3

auto[1]

1194

1

T7

20

T10

20

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117

1

T28

4

T277

1

T305

1

auto[1]

1477

1

T1

20

T6

14

T3

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132

1

T28

3

T277

1

T370

3

auto[1]

1272

1

T1

20

T7

20

T9

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128

1

T27

1

T28

3

T277

1

auto[1]

1280

1

T1

20

T26

20

T46

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133

1

T27

1

T28

5

T277

2

auto[1]

1278

1

T1

20

T6

14

T3

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131

1

T27

2

T28

3

T277

3

auto[1]

1311

1

T7

20

T10

20

T46

13

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120

1

T27

1

T28

3

T277

2

auto[1]

1274

1

T3

17

T7

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

145

1

T27

1

T28

3

T277

4

auto[1]

1209

1

T7

20

T9

20

T10

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270

1

T27

1

T28

4

T277

4

auto[1]

469

1

T2

1

T16

1

T53

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136

1

T28

2

T277

2

T279

2

auto[1]

312

1

T11

1

T24

1

T40

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133

1

T28

2

T277

2

T279

2

auto[1]

234

1

T11

1

T12

1

T24

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134

1

T28

5

T277

2

T279

2

auto[1]

266

1

T11

1

T12

1

T37

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128

1

T28

4

T277

3

T279

2

auto[1]

226

1

T40

1

T43

1

T35

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

131

1

T28

3

T277

3

T279

1

auto[1]

281

1

T40

1

T35

1

T41

1