Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T13
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T13,T17,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T13,T17,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T13,T17,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T25
1	0	Covered	T1,T6,T2
1	1	Covered	T13,T17,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T25
0	1	Covered	T47,T70,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T25
0	1	Covered	T13,T17,T25
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T17,T25
1	-	Covered	T13,T17,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T17,T25
DetectSt	168	Covered	T13,T17,T25
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T13,T17,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T17,T25
DebounceSt->IdleSt	163	Covered	T13,T50,T42
DetectSt->IdleSt	186	Covered	T47,T70,T97
DetectSt->StableSt	191	Covered	T13,T17,T25
IdleSt->DebounceSt	148	Covered	T13,T17,T25
StableSt->IdleSt	206	Covered	T13,T17,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T17,T25
0	1	Covered	T13,T17,T25
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T17,T25
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T25
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T17,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T50,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T25
DetectSt	-	-	-	-	1	-	-	Covered	T47,T70,T97
DetectSt	-	-	-	-	0	1	-	Covered	T13,T17,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T17,T25
StableSt	-	-	-	-	-	-	0	Covered	T13,T17,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	361	0	0
CntIncr_A	8663532	151867	0	0
CntNoWrap_A	8663532	7982912	0	0
DetectStDropOut_A	8663532	5	0	0
DetectedOut_A	8663532	1117	0	0
DetectedPulseOut_A	8663532	160	0	0
DisabledIdleSt_A	8663532	7822710	0	0
DisabledNoDetection_A	8663532	7825019	0	0
EnterDebounceSt_A	8663532	201	0	0
EnterDetectSt_A	8663532	165	0	0
EnterStableSt_A	8663532	160	0	0
PulseIsPulse_A	8663532	160	0	0
StayInStableSt	8663532	957	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	7128	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	159	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	361	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	6	0	0
T13	711	5	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	2	0	0
T25	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	4	0	0
T53	558	0	0	0
T82	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	151867	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	165	0	0
T13	711	194	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	10	0	0
T25	0	80	0	0
T47	0	68	0	0
T48	0	96	0	0
T50	0	71	0	0
T51	0	49	0	0
T52	0	110	0	0
T53	558	0	0	0
T82	0	164	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7982912	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	305	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	5	0	0
T11	1622	0	0	0
T12	597	0	0	0
T24	901	0	0	0
T47	610	1	0	0
T48	14447	0	0	0
T49	747	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T70	0	1	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	427	0	0	0
T101	440	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1117	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	7	0	0
T13	711	18	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	9	0	0
T25	0	12	0	0
T42	0	36	0	0
T47	0	12	0	0
T48	0	10	0	0
T51	0	10	0	0
T52	0	20	0	0
T53	558	0	0	0
T82	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	160	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	3	0	0
T13	711	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	1	0	0
T25	0	1	0	0
T42	0	5	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	558	0	0	0
T82	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7822710	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	3	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7825019	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	3	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	201	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	3	0	0
T13	711	3	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	1	0	0
T25	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	558	0	0	0
T82	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	165	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	3	0	0
T13	711	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	1	0	0
T25	0	1	0	0
T42	0	5	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	558	0	0	0
T82	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	160	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	3	0	0
T13	711	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	1	0	0
T25	0	1	0	0
T42	0	5	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	558	0	0	0
T82	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	160	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	3	0	0
T13	711	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	1	0	0
T25	0	1	0	0
T42	0	5	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	558	0	0	0
T82	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	957	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	4	0	0
T13	711	16	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	8	0	0
T25	0	11	0	0
T42	0	31	0	0
T47	0	11	0	0
T48	0	9	0	0
T51	0	9	0	0
T52	0	18	0	0
T53	558	0	0	0
T82	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7128	0	0
T1	28754	10	0	0
T2	127882	22	0	0
T3	19948	22	0	0
T4	1680	7	0	0
T6	17174	25	0	0
T7	0	11	0	0
T13	711	3	0	0
T14	426	3	0	0
T15	421	3	0	0
T16	223329	0	0	0
T17	1471	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	159	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T10	0	3	0	0
T13	711	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	1	0	0
T25	0	1	0	0
T42	0	5	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	558	0	0	0
T82	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T13
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T4,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T4,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T6,T13
1	1	Covered	T2,T4,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T60
0	1	Covered	T8,T79,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T60
0	1	Unreachable
1	0	Covered	T2,T10,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T8
DetectSt	168	Covered	T2,T8,T10
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T10,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T10
DebounceSt->IdleSt	163	Covered	T4,T8,T50
DetectSt->IdleSt	186	Covered	T8,T79,T80
DetectSt->StableSt	191	Covered	T2,T10,T60
IdleSt->DebounceSt	148	Covered	T2,T4,T8
StableSt->IdleSt	206	Covered	T2,T10,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T8
0	1	Covered	T2,T4,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T10
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T8,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T79,T80
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T60
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	243	0	0
CntIncr_A	8663532	77583	0	0
CntNoWrap_A	8663532	7983030	0	0
DetectStDropOut_A	8663532	22	0	0
DetectedOut_A	8663532	439784	0	0
DetectedPulseOut_A	8663532	69	0	0
DisabledIdleSt_A	8663532	6283146	0	0
DisabledNoDetection_A	8663532	6285520	0	0
EnterDebounceSt_A	8663532	152	0	0
EnterDetectSt_A	8663532	91	0	0
EnterStableSt_A	8663532	69	0	0
PulseIsPulse_A	8663532	69	0	0
StayInStableSt	8663532	439715	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	7128	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_sticky_sva.StableStDropOut_A	8663532	398820	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	243	0	0
T2	127882	2	0	0
T3	19948	0	0	0
T4	1680	4	0	0
T7	11518	0	0	0
T8	1282	5	0	0
T10	0	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	3	0	0
T53	558	0	0	0
T60	0	2	0	0
T61	0	2	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	77583	0	0
T2	127882	16274	0	0
T3	19948	0	0	0
T4	1680	212	0	0
T7	11518	0	0	0
T8	1282	135	0	0
T10	0	13	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	66	0	0
T53	558	0	0	0
T60	0	80	0	0
T61	0	87	0	0
T70	0	19	0	0
T71	0	16	0	0
T72	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983030	0	0
T1	28754	28290	0	0
T2	127882	124055	0	0
T3	19948	19505	0	0
T4	1680	1275	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	22	0	0
T8	1282	2	0	0
T9	18971	0	0	0
T10	12041	0	0	0
T21	491	0	0	0
T22	504	0	0	0
T23	2201	0	0	0
T25	682	0	0	0
T44	0	1	0	0
T47	610	0	0	0
T79	0	2	0	0
T80	0	2	0	0
T111	422	0	0	0
T112	407	0	0	0
T116	0	2	0	0
T117	0	3	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	439784	0	0
T2	127882	107034	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	101	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T44	0	428	0	0
T53	558	0	0	0
T60	0	244	0	0
T61	0	520	0	0
T70	0	93	0	0
T72	0	183	0	0
T80	0	82	0	0
T114	0	403	0	0
T115	0	32	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	69	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T44	0	2	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T80	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6283146	0	0
T1	28754	28290	0	0
T2	127882	630	0	0
T3	19948	19505	0	0
T4	1680	562	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6285520	0	0
T1	28754	28302	0	0
T2	127882	639	0	0
T3	19948	19512	0	0
T4	1680	563	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	152	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	4	0	0
T7	11518	0	0	0
T8	1282	3	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	3	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	91	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	2	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T79	0	2	0	0
T80	0	3	0	0
T114	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	69	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T44	0	2	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T80	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	69	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T44	0	2	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T80	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	439715	0	0
T2	127882	107033	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	100	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T44	0	426	0	0
T53	558	0	0	0
T60	0	243	0	0
T61	0	519	0	0
T70	0	92	0	0
T72	0	182	0	0
T80	0	81	0	0
T114	0	401	0	0
T115	0	31	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7128	0	0
T1	28754	10	0	0
T2	127882	22	0	0
T3	19948	22	0	0
T4	1680	7	0	0
T6	17174	25	0	0
T7	0	11	0	0
T13	711	3	0	0
T14	426	3	0	0
T15	421	3	0	0
T16	223329	0	0	0
T17	1471	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	398820	0	0
T2	127882	99	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	707	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T44	0	621	0	0
T53	558	0	0	0
T60	0	74	0	0
T61	0	117	0	0
T70	0	289	0	0
T72	0	93	0	0
T80	0	111	0	0
T114	0	250	0	0
T115	0	62	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T2,T14,T15
1	1	Covered	T2,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T4,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T4,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T4,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T14,T15
1	1	Covered	T2,T4,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T4,T10,T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Unreachable
1	0	Covered	T2,T4,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T8
DetectSt	168	Covered	T2,T4,T8
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T4,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T8
DebounceSt->IdleSt	163	Covered	T4,T60,T71
DetectSt->IdleSt	186	Covered	T4,T10,T72
DetectSt->StableSt	191	Covered	T2,T4,T8
IdleSt->DebounceSt	148	Covered	T2,T4,T8
StableSt->IdleSt	206	Covered	T2,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T8
0	1	Covered	T2,T4,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T8
IdleSt	0	-	-	-	-	-	-	Covered	T2,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T60,T113
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	1	-	-	Covered	T4,T10,T72
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	262	0	0
CntIncr_A	8663532	536641	0	0
CntNoWrap_A	8663532	7983011	0	0
DetectStDropOut_A	8663532	30	0	0
DetectedOut_A	8663532	561913	0	0
DetectedPulseOut_A	8663532	70	0	0
DisabledIdleSt_A	8663532	6283146	0	0
DisabledNoDetection_A	8663532	6285520	0	0
EnterDebounceSt_A	8663532	162	0	0
EnterDetectSt_A	8663532	100	0	0
EnterStableSt_A	8663532	70	0	0
PulseIsPulse_A	8663532	70	0	0
StayInStableSt	8663532	561843	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_sticky_sva.StableStDropOut_A	8663532	464979	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	262	0	0
T2	127882	2	0	0
T3	19948	0	0	0
T4	1680	7	0	0
T7	11518	0	0	0
T8	1282	2	0	0
T10	0	4	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	2	0	0
T53	558	0	0	0
T60	0	4	0	0
T61	0	2	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	536641	0	0
T2	127882	37	0	0
T3	19948	0	0	0
T4	1680	316	0	0
T7	11518	0	0	0
T8	1282	94	0	0
T10	0	68	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	59	0	0
T53	558	0	0	0
T60	0	192	0	0
T61	0	54	0	0
T70	0	77	0	0
T71	0	16	0	0
T72	0	291	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983011	0	0
T1	28754	28290	0	0
T2	127882	124055	0	0
T3	19948	19505	0	0
T4	1680	1272	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	30	0	0
T4	1680	2	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	1	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T21	491	0	0	0
T22	504	0	0	0
T25	682	0	0	0
T53	558	0	0	0
T72	0	2	0	0
T112	407	0	0	0
T118	0	1	0	0
T119	0	6	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	0	3	0	0
T125	0	2	0	0
T126	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	561913	0	0
T2	127882	301	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	449	0	0
T10	0	107	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	253	0	0
T53	558	0	0	0
T61	0	377	0	0
T70	0	251	0	0
T72	0	1	0	0
T79	0	233654	0	0
T80	0	237	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	70	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6283146	0	0
T1	28754	28290	0	0
T2	127882	630	0	0
T3	19948	19505	0	0
T4	1680	562	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6285520	0	0
T1	28754	28302	0	0
T2	127882	639	0	0
T3	19948	19512	0	0
T4	1680	563	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	162	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	4	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T60	0	4	0	0
T61	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	100	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	3	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	3	0	0
T79	0	1	0	0
T80	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	70	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	70	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	561843	0	0
T2	127882	300	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	448	0	0
T10	0	106	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	252	0	0
T53	558	0	0	0
T61	0	376	0	0
T70	0	250	0	0
T79	0	233653	0	0
T80	0	236	0	0
T114	0	191	0	0
T115	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	464979	0	0
T2	127882	123068	0	0
T3	19948	0	0	0
T4	1680	93	0	0
T7	11518	0	0	0
T8	1282	73	0	0
T10	0	516	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	69	0	0
T53	558	0	0	0
T61	0	284	0	0
T70	0	63	0	0
T72	0	26	0	0
T79	0	63	0	0
T80	0	86	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T4,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T2,T4,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T2,T4,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T8
1	0	Covered	T1,T6,T2
1	1	Covered	T2,T4,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Covered	T76,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T8
0	1	Unreachable
1	0	Covered	T2,T4,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T4,T8
DetectSt	168	Covered	T2,T4,T8
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T2,T4,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T4,T8
DebounceSt->IdleSt	163	Covered	T71,T114,T44
DetectSt->IdleSt	186	Covered	T76,T77,T78
DetectSt->StableSt	191	Covered	T2,T4,T8
IdleSt->DebounceSt	148	Covered	T2,T4,T8
StableSt->IdleSt	206	Covered	T2,T4,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T4,T8
0	1	Covered	T2,T4,T8
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T8
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T4,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T4,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T114,T44,T127
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	1	-	-	Covered	T76,T77,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	254	0	0
CntIncr_A	8663532	124893	0	0
CntNoWrap_A	8663532	7983019	0	0
DetectStDropOut_A	8663532	26	0	0
DetectedOut_A	8663532	229526	0	0
DetectedPulseOut_A	8663532	66	0	0
DisabledIdleSt_A	8663532	6283146	0	0
DisabledNoDetection_A	8663532	6285520	0	0
EnterDebounceSt_A	8663532	162	0	0
EnterDetectSt_A	8663532	92	0	0
EnterStableSt_A	8663532	66	0	0
PulseIsPulse_A	8663532	66	0	0
StayInStableSt	8663532	229460	0	0
gen_high_event_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_sticky_sva.StableStDropOut_A	8663532	1174780	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	254	0	0
T2	127882	2	0	0
T3	19948	0	0	0
T4	1680	2	0	0
T7	11518	0	0	0
T8	1282	2	0	0
T10	0	2	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	2	0	0
T53	558	0	0	0
T60	0	2	0	0
T61	0	2	0	0
T70	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	124893	0	0
T2	127882	93	0	0
T3	19948	0	0	0
T4	1680	94	0	0
T7	11518	0	0	0
T8	1282	17	0	0
T10	0	93	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	11	0	0
T53	558	0	0	0
T60	0	62	0	0
T61	0	98	0	0
T70	0	61	0	0
T71	0	17	0	0
T72	0	28	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983019	0	0
T1	28754	28290	0	0
T2	127882	124055	0	0
T3	19948	19505	0	0
T4	1680	1277	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	26	0	0
T73	710	0	0	0
T76	1087	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T122	0	3	0	0
T128	0	2	0	0
T129	0	1	0	0
T130	0	3	0	0
T131	0	3	0	0
T132	0	2	0	0
T133	0	1	0	0
T134	613	0	0	0
T135	526	0	0	0
T136	426	0	0	0
T137	422	0	0	0
T138	522	0	0	0
T139	454	0	0	0
T140	782	0	0	0
T141	10559	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	229526	0	0
T2	127882	528	0	0
T3	19948	0	0	0
T4	1680	390	0	0
T7	11518	0	0	0
T8	1282	80	0	0
T10	0	682	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	53	0	0
T53	558	0	0	0
T60	0	284	0	0
T61	0	438	0	0
T70	0	292	0	0
T72	0	117	0	0
T113	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	66	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T113	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6283146	0	0
T1	28754	28290	0	0
T2	127882	630	0	0
T3	19948	19505	0	0
T4	1680	562	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6285520	0	0
T1	28754	28302	0	0
T2	127882	639	0	0
T3	19948	19512	0	0
T4	1680	563	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	162	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	92	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	66	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T113	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	66	0	0
T2	127882	1	0	0
T3	19948	0	0	0
T4	1680	1	0	0
T7	11518	0	0	0
T8	1282	1	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	1	0	0
T53	558	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T70	0	1	0	0
T72	0	1	0	0
T113	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	229460	0	0
T2	127882	527	0	0
T3	19948	0	0	0
T4	1680	389	0	0
T7	11518	0	0	0
T8	1282	79	0	0
T10	0	681	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	52	0	0
T53	558	0	0	0
T60	0	283	0	0
T61	0	437	0	0
T70	0	291	0	0
T72	0	116	0	0
T113	0	105	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1174780	0	0
T2	127882	122800	0	0
T3	19948	0	0	0
T4	1680	227	0	0
T7	11518	0	0	0
T8	1282	525	0	0
T10	0	48	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T50	0	334	0	0
T53	558	0	0	0
T60	0	58	0	0
T61	0	196	0	0
T70	0	51	0	0
T72	0	206	0	0
T113	0	120158	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T40,T35,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T40,T35,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T40,T35,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T40,T35
1	0	Covered	T5,T1,T6
1	1	Covered	T40,T35,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T35,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T35,T42
0	1	Covered	T142,T143,T144
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T35,T42
1	-	Covered	T142,T143,T144

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T35,T42
DetectSt	168	Covered	T40,T35,T42
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T40,T35,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T35,T42
DebounceSt->IdleSt	163	Covered	T71,T145
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T35,T42
IdleSt->DebounceSt	148	Covered	T40,T35,T42
StableSt->IdleSt	206	Covered	T42,T142,T146

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T35,T42
0	1	Covered	T40,T35,T42
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T35,T42
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T35,T42
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T35,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T145
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T35,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T35,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T142,T59,T143
StableSt	-	-	-	-	-	-	0	Covered	T40,T35,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	60	0	0
CntIncr_A	8663532	38493	0	0
CntNoWrap_A	8663532	7983213	0	0
DetectStDropOut_A	8663532	0	0	0
DetectedOut_A	8663532	54863	0	0
DetectedPulseOut_A	8663532	29	0	0
DisabledIdleSt_A	8663532	7835482	0	0
DisabledNoDetection_A	8663532	7837804	0	0
EnterDebounceSt_A	8663532	31	0	0
EnterDetectSt_A	8663532	29	0	0
EnterStableSt_A	8663532	29	0	0
PulseIsPulse_A	8663532	29	0	0
StayInStableSt	8663532	54817	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	60	0	0
T26	22383	0	0	0
T35	0	2	0	0
T39	0	2	0	0
T40	529	2	0	0
T42	0	2	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	2	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	1	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	38493	0	0
T26	22383	0	0	0
T35	0	85	0	0
T39	0	39	0	0
T40	529	44	0	0
T42	0	36930	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	31	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	27	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	65	0	0
T146	0	61	0	0
T147	0	90	0	0
T148	0	18	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983213	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	54863	0	0
T26	22383	0	0	0
T35	0	40	0	0
T39	0	101	0	0
T40	529	41	0	0
T42	0	53392	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	15	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	40	0	0
T146	0	16	0	0
T147	0	45	0	0
T148	0	39	0	0
T149	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	29	0	0
T26	22383	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	1	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7835482	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7837804	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	31	0	0
T26	22383	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	1	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	1	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	29	0	0
T26	22383	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	1	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	29	0	0
T26	22383	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	1	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	29	0	0
T26	22383	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	1	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	54817	0	0
T26	22383	0	0	0
T35	0	38	0	0
T39	0	99	0	0
T40	529	39	0	0
T42	0	53390	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T59	0	14	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	39	0	0
T146	0	14	0	0
T147	0	43	0	0
T148	0	37	0	0
T149	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	11	0	0
T36	3438	0	0	0
T81	8416	0	0	0
T142	1026	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	2	0	0
T157	422	0	0	0
T158	16950	0	0	0
T159	804	0	0	0
T160	414	0	0	0
T161	493	0	0	0
T162	646	0	0	0
T163	457	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T40,T35,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T40,T35,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T35,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T35,T41
1	0	Covered	T1,T6,T2
1	1	Covered	T40,T35,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T41,T42
0	1	Covered	T164,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T41,T42
0	1	Covered	T35,T42,T142
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T41,T42
1	-	Covered	T35,T42,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T35,T41
DetectSt	168	Covered	T35,T41,T42
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T35,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T41,T42
DebounceSt->IdleSt	163	Covered	T40,T71,T149
DetectSt->IdleSt	186	Covered	T164,T92
DetectSt->StableSt	191	Covered	T35,T41,T42
IdleSt->DebounceSt	148	Covered	T40,T35,T41
StableSt->IdleSt	206	Covered	T35,T42,T142

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T35,T41
0	1	Covered	T40,T35,T41
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T41,T42
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T35,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T149,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T35,T41
DetectSt	-	-	-	-	1	-	-	Covered	T164,T92
DetectSt	-	-	-	-	0	1	-	Covered	T35,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T42,T142
StableSt	-	-	-	-	-	-	0	Covered	T35,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	142	0	0
CntIncr_A	8663532	50105	0	0
CntNoWrap_A	8663532	7983131	0	0
DetectStDropOut_A	8663532	2	0	0
DetectedOut_A	8663532	11484	0	0
DetectedPulseOut_A	8663532	67	0	0
DisabledIdleSt_A	8663532	7808174	0	0
DisabledNoDetection_A	8663532	7810491	0	0
EnterDebounceSt_A	8663532	73	0	0
EnterDetectSt_A	8663532	69	0	0
EnterStableSt_A	8663532	67	0	0
PulseIsPulse_A	8663532	67	0	0
StayInStableSt	8663532	11382	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	2781	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	142	0	0
T26	22383	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T40	529	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T44	0	4	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	1	0	0
T73	0	4	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	4	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	50105	0	0
T26	22383	0	0	0
T35	0	85	0	0
T36	0	93	0	0
T40	529	44	0	0
T41	0	29	0	0
T42	0	36930	0	0
T44	0	44	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	27	0	0
T73	0	62	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	130	0	0
T166	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983131	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2	0	0
T92	0	1	0	0
T164	2327	1	0	0
T167	525	0	0	0
T168	489	0	0	0
T169	526	0	0	0
T170	16047	0	0	0
T171	18248	0	0	0
T172	497	0	0	0
T173	453	0	0	0
T174	38357	0	0	0
T175	778	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	11484	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	165	0	0
T36	0	523	0	0
T41	0	70	0	0
T42	0	1579	0	0
T44	0	81	0	0
T63	1419	0	0	0
T73	0	78	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T142	0	158	0	0
T148	0	17	0	0
T166	0	156	0	0
T176	0	48	0	0
T177	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	67	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T63	1419	0	0	0
T73	0	2	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T142	0	2	0	0
T148	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7808174	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7810491	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	73	0	0
T26	22383	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	529	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	1	0	0
T73	0	2	0	0
T83	438	0	0	0
T84	915	0	0	0
T142	0	2	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	69	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T63	1419	0	0	0
T73	0	2	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T142	0	2	0	0
T148	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	67	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T63	1419	0	0	0
T73	0	2	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T142	0	2	0	0
T148	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	67	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T63	1419	0	0	0
T73	0	2	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T142	0	2	0	0
T148	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T177	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	11382	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	164	0	0
T36	0	521	0	0
T41	0	68	0	0
T42	0	1578	0	0
T44	0	78	0	0
T63	1419	0	0	0
T73	0	75	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T142	0	155	0	0
T148	0	16	0	0
T166	0	154	0	0
T176	0	46	0	0
T177	422	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2781	0	0
T2	127882	20	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	7	0	0
T14	426	4	0	0
T15	421	3	0	0
T16	223329	0	0	0
T17	1471	4	0	0
T21	0	5	0	0
T22	0	4	0	0
T23	0	4	0	0
T53	558	0	0	0
T100	0	2	0	0
T111	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	31	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T63	1419	0	0	0
T73	0	1	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	1	0	0
T122	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T148	0	1	0	0
T177	422	0	0	0
T178	0	2	0	0