Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T43,T35,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T43,T35,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T43,T35,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T43,T35
1	0	Covered	T5,T1,T6
1	1	Covered	T43,T35,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T44
0	1	Covered	T43
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T44,T134
0	1	Covered	T35,T38,T44
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T44,T134
1	-	Covered	T35,T38,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T35,T38
DetectSt	168	Covered	T43,T35,T38
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T35,T38,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T35,T38
DebounceSt->IdleSt	163	Covered	T71,T179,T180
DetectSt->IdleSt	186	Covered	T43
DetectSt->StableSt	191	Covered	T35,T38,T44
IdleSt->DebounceSt	148	Covered	T43,T35,T38
StableSt->IdleSt	206	Covered	T35,T38,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T43,T35,T38
0	1	Covered	T43,T35,T38
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T35,T38
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T35,T38
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T35,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T179,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T35,T38
DetectSt	-	-	-	-	1	-	-	Covered	T43
DetectSt	-	-	-	-	0	1	-	Covered	T35,T38,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T38,T44
StableSt	-	-	-	-	-	-	0	Covered	T35,T44,T134
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	57	0	0
CntIncr_A	8663532	65787	0	0
CntNoWrap_A	8663532	7983216	0	0
DetectStDropOut_A	8663532	1	0	0
DetectedOut_A	8663532	2285	0	0
DetectedPulseOut_A	8663532	26	0	0
DisabledIdleSt_A	8663532	7737309	0	0
DisabledNoDetection_A	8663532	7739643	0	0
EnterDebounceSt_A	8663532	30	0	0
EnterDetectSt_A	8663532	27	0	0
EnterStableSt_A	8663532	26	0	0
PulseIsPulse_A	8663532	26	0	0
StayInStableSt	8663532	2243	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	57	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	4	0	0
T38	0	2	0	0
T43	1539	2	0	0
T44	0	2	0	0
T59	0	2	0	0
T63	1419	0	0	0
T71	0	1	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T134	0	2	0	0
T179	0	1	0	0
T181	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	65787	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	170	0	0
T38	0	53	0	0
T43	1539	55	0	0
T44	0	22	0	0
T59	0	31	0	0
T63	1419	0	0	0
T71	0	27	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T134	0	81	0	0
T179	0	79	0	0
T181	0	17	0	0
T182	0	64279	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983216	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	0	0	0
T43	1539	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2285	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	289	0	0
T38	0	1	0	0
T44	0	68	0	0
T59	0	16	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	53	0	0
T134	0	40	0	0
T177	422	0	0	0
T181	0	43	0	0
T182	0	46	0	0
T183	0	275	0	0
T184	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	26	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	1	0	0
T134	0	1	0	0
T177	422	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7737309	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7739643	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	30	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	2	0	0
T38	0	1	0	0
T43	1539	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T63	1419	0	0	0
T71	0	1	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T134	0	1	0	0
T179	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	27	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	2	0	0
T38	0	1	0	0
T43	1539	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T134	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	26	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	1	0	0
T134	0	1	0	0
T177	422	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	26	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T59	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	1	0	0
T134	0	1	0	0
T177	422	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2243	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	286	0	0
T44	0	67	0	0
T59	0	15	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	51	0	0
T134	0	38	0	0
T177	422	0	0	0
T181	0	41	0	0
T182	0	44	0	0
T183	0	273	0	0
T184	0	39	0	0
T185	0	61	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	9	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T38	0	1	0	0
T44	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T177	422	0	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T11,T12,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T37
1	0	Covered	T1,T6,T2
1	1	Covered	T11,T12,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T40
0	1	Covered	T73,T183
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T40
0	1	Covered	T12,T35,T42
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T40
1	-	Covered	T12,T35,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T40
DetectSt	168	Covered	T11,T12,T40
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T12,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T40
DebounceSt->IdleSt	163	Covered	T71,T144,T189
DetectSt->IdleSt	186	Covered	T73,T183
DetectSt->StableSt	191	Covered	T11,T12,T40
IdleSt->DebounceSt	148	Covered	T11,T12,T40
StableSt->IdleSt	206	Covered	T12,T35,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T40
0	1	Covered	T11,T12,T40
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T40
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T189,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T40
DetectSt	-	-	-	-	1	-	-	Covered	T73,T183
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T35,T42
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	125	0	0
CntIncr_A	8663532	77115	0	0
CntNoWrap_A	8663532	7983148	0	0
DetectStDropOut_A	8663532	2	0	0
DetectedOut_A	8663532	5854	0	0
DetectedPulseOut_A	8663532	58	0	0
DisabledIdleSt_A	8663532	7835440	0	0
DisabledNoDetection_A	8663532	7837762	0	0
EnterDebounceSt_A	8663532	65	0	0
EnterDetectSt_A	8663532	60	0	0
EnterStableSt_A	8663532	58	0	0
PulseIsPulse_A	8663532	58	0	0
StayInStableSt	8663532	5766	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	3224	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	125	0	0
T11	1622	2	0	0
T12	597	2	0	0
T24	901	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	4791	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	4	0	0
T44	0	4	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T142	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	77115	0	0
T11	1622	33	0	0
T12	597	70	0	0
T24	901	0	0	0
T35	0	170	0	0
T36	0	186	0	0
T37	4791	0	0	0
T39	0	39	0	0
T40	0	44	0	0
T42	0	73860	0	0
T44	0	44	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	27	0	0
T142	0	130	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983148	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2	0	0
T73	710	1	0	0
T127	1309	0	0	0
T141	10559	0	0	0
T183	0	1	0	0
T191	489	0	0	0
T192	409	0	0	0
T193	695	0	0	0
T194	402	0	0	0
T195	422	0	0	0
T196	407	0	0	0
T197	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	5854	0	0
T11	1622	284	0	0
T12	597	6	0	0
T24	901	0	0	0
T35	0	45	0	0
T36	0	404	0	0
T37	4791	0	0	0
T39	0	197	0	0
T40	0	41	0	0
T42	0	1624	0	0
T44	0	54	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	79	0	0
T198	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	58	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	2	0	0
T198	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7835440	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7837762	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	65	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T142	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	60	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	2	0	0
T198	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	58	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	2	0	0
T198	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	58	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	2	0	0
T198	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	5766	0	0
T11	1622	282	0	0
T12	597	5	0	0
T24	901	0	0	0
T35	0	43	0	0
T36	0	401	0	0
T37	4791	0	0	0
T39	0	196	0	0
T40	0	39	0	0
T42	0	1621	0	0
T44	0	51	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	77	0	0
T198	0	77	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3224	0	0
T2	127882	20	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T10	0	5	0	0
T14	426	2	0	0
T15	421	1	0	0
T16	223329	4	0	0
T17	1471	1	0	0
T21	0	6	0	0
T22	0	5	0	0
T23	0	5	0	0
T53	558	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	27	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	529	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T134	0	1	0	0
T142	0	2	0	0
T147	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T11,T12,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T24
1	0	Covered	T1,T6,T2
1	1	Covered	T11,T12,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T24
0	1	Covered	T35,T199
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T24
0	1	Covered	T11,T24,T43
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T24
1	-	Covered	T11,T24,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T24
DetectSt	168	Covered	T11,T12,T24
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T12,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T24
DebounceSt->IdleSt	163	Covered	T71,T144,T200
DetectSt->IdleSt	186	Covered	T35,T199
DetectSt->StableSt	191	Covered	T11,T12,T24
IdleSt->DebounceSt	148	Covered	T11,T12,T24
StableSt->IdleSt	206	Covered	T11,T24,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T24
0	1	Covered	T11,T12,T24
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T24
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T24
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T24
DetectSt	-	-	-	-	1	-	-	Covered	T35,T199
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T24,T43
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	108	0	0
CntIncr_A	8663532	109499	0	0
CntNoWrap_A	8663532	7983165	0	0
DetectStDropOut_A	8663532	2	0	0
DetectedOut_A	8663532	64121	0	0
DetectedPulseOut_A	8663532	50	0	0
DisabledIdleSt_A	8663532	7710588	0	0
DisabledNoDetection_A	8663532	7712914	0	0
EnterDebounceSt_A	8663532	56	0	0
EnterDetectSt_A	8663532	52	0	0
EnterStableSt_A	8663532	50	0	0
PulseIsPulse_A	8663532	50	0	0
StayInStableSt	8663532	64044	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	108	0	0
T11	1622	2	0	0
T12	597	2	0	0
T24	901	2	0	0
T35	0	4	0	0
T37	4791	0	0	0
T39	0	2	0	0
T43	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T142	0	4	0	0
T198	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	109499	0	0
T11	1622	33	0	0
T12	597	70	0	0
T24	901	77	0	0
T35	0	170	0	0
T37	4791	0	0	0
T39	0	39	0	0
T43	0	55	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	28	0	0
T142	0	130	0	0
T198	0	23	0	0
T201	0	41896	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983165	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T177	422	0	0	0
T199	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	64121	0	0
T11	1622	168	0	0
T12	597	117	0	0
T24	901	44	0	0
T35	0	161	0	0
T37	4791	0	0	0
T39	0	36	0	0
T43	0	19	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T134	0	122	0	0
T142	0	195	0	0
T198	0	68	0	0
T201	0	59854	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	50	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T134	0	1	0	0
T142	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7710588	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7712914	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	56	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	2	0	0
T37	4791	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T142	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	52	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	2	0	0
T37	4791	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T134	0	1	0	0
T142	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	50	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T134	0	1	0	0
T142	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	50	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T134	0	1	0	0
T142	0	2	0	0
T198	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	64044	0	0
T11	1622	167	0	0
T12	597	115	0	0
T24	901	43	0	0
T35	0	159	0	0
T37	4791	0	0	0
T39	0	35	0	0
T43	0	18	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T134	0	120	0	0
T142	0	193	0	0
T198	0	66	0	0
T201	0	59852	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	22	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T116	0	1	0	0
T142	0	2	0	0
T164	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T202	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T24,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T11,T24,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T24,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T24,T40
1	0	Covered	T1,T6,T2
1	1	Covered	T11,T24,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T24,T35
0	1	Covered	T35,T41,T178
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T24,T35
1	-	Covered	T35,T41,T178

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T24,T35
DetectSt	168	Covered	T11,T24,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T24,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T24,T35
DebounceSt->IdleSt	163	Covered	T71
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T24,T35
IdleSt->DebounceSt	148	Covered	T11,T24,T35
StableSt->IdleSt	206	Covered	T35,T41,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T24,T35
0	1	Covered	T11,T24,T35
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T24,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T24,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T24,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T24,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T24,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T41,T59
StableSt	-	-	-	-	-	-	0	Covered	T11,T24,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	47	0	0
CntIncr_A	8663532	1383	0	0
CntNoWrap_A	8663532	7983226	0	0
DetectStDropOut_A	8663532	0	0	0
DetectedOut_A	8663532	1815	0	0
DetectedPulseOut_A	8663532	23	0	0
DisabledIdleSt_A	8663532	7740402	0	0
DisabledNoDetection_A	8663532	7742733	0	0
EnterDebounceSt_A	8663532	24	0	0
EnterDetectSt_A	8663532	23	0	0
EnterStableSt_A	8663532	23	0	0
PulseIsPulse_A	8663532	23	0	0
StayInStableSt	8663532	1778	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	6868	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	47	0	0
T11	1622	2	0	0
T12	597	0	0	0
T24	901	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	4791	0	0	0
T41	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	2	0	0
T71	0	1	0	0
T78	0	2	0	0
T122	0	2	0	0
T149	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1383	0	0
T11	1622	33	0	0
T12	597	0	0	0
T24	901	77	0	0
T35	0	85	0	0
T36	0	93	0	0
T37	4791	0	0	0
T41	0	29	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	31	0	0
T71	0	26	0	0
T78	0	31	0	0
T122	0	75	0	0
T149	0	16	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983226	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1815	0	0
T11	1622	82	0	0
T12	597	0	0	0
T24	901	183	0	0
T35	0	44	0	0
T36	0	38	0	0
T37	4791	0	0	0
T41	0	41	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	16	0	0
T78	0	45	0	0
T122	0	158	0	0
T149	0	38	0	0
T178	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	23	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7740402	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7742733	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	24	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T71	0	1	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	23	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	23	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	23	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1778	0	0
T11	1622	80	0	0
T12	597	0	0	0
T24	901	181	0	0
T35	0	43	0	0
T36	0	36	0	0
T37	4791	0	0	0
T41	0	40	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	15	0	0
T78	0	43	0	0
T122	0	156	0	0
T149	0	36	0	0
T178	0	69	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6868	0	0
T1	28754	12	0	0
T2	127882	23	0	0
T3	19948	38	0	0
T4	1680	7	0	0
T6	17174	29	0	0
T7	0	10	0	0
T8	0	4	0	0
T13	711	0	0	0
T14	426	1	0	0
T15	421	3	0	0
T16	223329	0	0	0
T17	1471	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	8	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T41	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T121	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T177	422	0	0	0
T178	0	1	0	0
T187	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T12,T37,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T12,T37,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T12,T37,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T37,T40
1	0	Covered	T1,T6,T2
1	1	Covered	T12,T37,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T43
0	1	Covered	T38,T203,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T37,T43
0	1	Covered	T12,T146,T39
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T37,T43
1	-	Covered	T12,T146,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T37,T43
DetectSt	168	Covered	T12,T37,T43
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T12,T37,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T37,T43
DebounceSt->IdleSt	163	Covered	T38,T42,T71
DetectSt->IdleSt	186	Covered	T38,T203,T92
DetectSt->StableSt	191	Covered	T12,T37,T43
IdleSt->DebounceSt	148	Covered	T12,T37,T43
StableSt->IdleSt	206	Covered	T12,T37,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T37,T43
0	1	Covered	T12,T37,T43
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T37,T43
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T37,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T37,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T178,T164
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T37,T43
DetectSt	-	-	-	-	1	-	-	Covered	T38,T203,T92
DetectSt	-	-	-	-	0	1	-	Covered	T12,T37,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T146,T39
StableSt	-	-	-	-	-	-	0	Covered	T12,T37,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	118	0	0
CntIncr_A	8663532	82325	0	0
CntNoWrap_A	8663532	7983155	0	0
DetectStDropOut_A	8663532	4	0	0
DetectedOut_A	8663532	76585	0	0
DetectedPulseOut_A	8663532	52	0	0
DisabledIdleSt_A	8663532	7735263	0	0
DisabledNoDetection_A	8663532	7737581	0	0
EnterDebounceSt_A	8663532	63	0	0
EnterDetectSt_A	8663532	56	0	0
EnterStableSt_A	8663532	52	0	0
PulseIsPulse_A	8663532	52	0	0
StayInStableSt	8663532	76512	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	118	0	0
T12	597	2	0	0
T24	901	0	0	0
T35	0	2	0	0
T37	4791	2	0	0
T38	0	5	0	0
T40	529	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T71	0	1	0	0
T142	0	2	0	0
T146	0	2	0	0
T204	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	82325	0	0
T12	597	70	0	0
T24	901	0	0	0
T35	0	85	0	0
T37	4791	54	0	0
T38	0	159	0	0
T40	529	0	0	0
T42	0	37108	0	0
T43	0	55	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T71	0	27	0	0
T142	0	65	0	0
T146	0	61	0	0
T204	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983155	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	4	0	0
T38	852	2	0	0
T42	150679	0	0	0
T61	1329	0	0	0
T82	786	0	0	0
T92	0	1	0	0
T203	0	1	0	0
T204	477	0	0	0
T205	2253	0	0	0
T206	25691	0	0	0
T207	496	0	0	0
T208	448	0	0	0
T209	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	76585	0	0
T12	597	5	0	0
T24	901	0	0	0
T35	0	162	0	0
T37	4791	37	0	0
T39	0	88	0	0
T40	529	0	0	0
T42	0	53391	0	0
T43	0	270	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T142	0	552	0	0
T146	0	43	0	0
T201	0	17918	0	0
T204	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	52	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T37	4791	1	0	0
T39	0	1	0	0
T40	529	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7735263	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7737581	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	63	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T37	4791	1	0	0
T38	0	3	0	0
T40	529	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T71	0	1	0	0
T142	0	1	0	0
T146	0	1	0	0
T204	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	56	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T37	4791	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	529	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T204	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	52	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T37	4791	1	0	0
T39	0	1	0	0
T40	529	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	52	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T37	4791	1	0	0
T39	0	1	0	0
T40	529	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T142	0	1	0	0
T146	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	76512	0	0
T12	597	4	0	0
T24	901	0	0	0
T35	0	160	0	0
T37	4791	35	0	0
T39	0	87	0	0
T40	529	0	0	0
T42	0	53389	0	0
T43	0	268	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T142	0	550	0	0
T146	0	42	0	0
T201	0	17917	0	0
T204	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	30	0	0
T12	597	1	0	0
T24	901	0	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T60	1349	0	0	0
T146	0	1	0	0
T164	0	1	0	0
T166	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0
T201	0	1	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T12,T38,T71

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T12,T38,T71

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T12,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T40,T43
1	0	Covered	T1,T6,T2
1	1	Covered	T12,T38,T71

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T38,T39
0	1	Covered	T38,T178,T92
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T38,T39
1	-	Covered	T38,T178,T92

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T38,T71
DetectSt	168	Covered	T12,T38,T39
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T12,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T38,T39
DebounceSt->IdleSt	163	Covered	T71
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T38,T39
IdleSt->DebounceSt	148	Covered	T12,T38,T71
StableSt->IdleSt	206	Covered	T38,T39,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T38,T71
0	1	Covered	T12,T38,T71
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T38,T39
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T38,T71
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T38,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T38,T71
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T59,T178
StableSt	-	-	-	-	-	-	0	Covered	T12,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	75	0	0
CntIncr_A	8663532	2041	0	0
CntNoWrap_A	8663532	7983198	0	0
DetectStDropOut_A	8663532	0	0	0
DetectedOut_A	8663532	2840	0	0
DetectedPulseOut_A	8663532	37	0	0
DisabledIdleSt_A	8663532	7839190	0	0
DisabledNoDetection_A	8663532	7841512	0	0
EnterDebounceSt_A	8663532	38	0	0
EnterDetectSt_A	8663532	37	0	0
EnterStableSt_A	8663532	37	0	0
PulseIsPulse_A	8663532	37	0	0
StayInStableSt	8663532	2780	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	6370	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	75	0	0
T12	597	2	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	6	0	0
T39	0	2	0	0
T40	529	0	0	0
T44	0	2	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	2	0	0
T60	1349	0	0	0
T71	0	1	0	0
T122	0	2	0	0
T134	0	2	0	0
T147	0	2	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2041	0	0
T12	597	70	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	159	0	0
T39	0	39	0	0
T40	529	0	0	0
T44	0	22	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	31	0	0
T60	1349	0	0	0
T71	0	27	0	0
T122	0	75	0	0
T134	0	81	0	0
T147	0	90	0	0
T179	0	79	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983198	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2840	0	0
T12	597	41	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	122	0	0
T39	0	257	0	0
T40	529	0	0	0
T44	0	46	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	15	0	0
T60	1349	0	0	0
T122	0	274	0	0
T134	0	40	0	0
T147	0	45	0	0
T178	0	83	0	0
T179	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	37	0	0
T12	597	1	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	529	0	0	0
T44	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T122	0	1	0	0
T134	0	1	0	0
T147	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7839190	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7841512	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	38	0	0
T12	597	1	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	529	0	0	0
T44	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T71	0	1	0	0
T122	0	1	0	0
T134	0	1	0	0
T147	0	1	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	37	0	0
T12	597	1	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	529	0	0	0
T44	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T122	0	1	0	0
T134	0	1	0	0
T147	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	37	0	0
T12	597	1	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	529	0	0	0
T44	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T122	0	1	0	0
T134	0	1	0	0
T147	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	37	0	0
T12	597	1	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	529	0	0	0
T44	0	1	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T122	0	1	0	0
T134	0	1	0	0
T147	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2780	0	0
T12	597	39	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	118	0	0
T39	0	255	0	0
T40	529	0	0	0
T44	0	44	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	14	0	0
T60	1349	0	0	0
T122	0	272	0	0
T134	0	38	0	0
T147	0	43	0	0
T178	0	81	0	0
T179	0	60	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6370	0	0
T1	28754	10	0	0
T2	127882	19	0	0
T3	19948	29	0	0
T4	1680	0	0	0
T6	17174	34	0	0
T7	0	15	0	0
T13	711	0	0	0
T14	426	2	0	0
T15	421	5	0	0
T16	223329	0	0	0
T17	1471	3	0	0
T21	0	6	0	0
T22	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	13	0	0
T38	852	2	0	0
T42	150679	0	0	0
T61	1329	0	0	0
T82	786	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T143	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T178	0	2	0	0
T200	0	1	0	0
T204	477	0	0	0
T205	2253	0	0	0
T206	25691	0	0	0
T207	496	0	0	0
T208	448	0	0	0
T209	405	0	0	0
T211	0	1	0	0