Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T41,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T11,T41,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T41,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T41,T38
1	0	Covered	T1,T6,T2
1	1	Covered	T11,T41,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T41,T38
0	1	Covered	T185,T121
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T41,T38
0	1	Covered	T11,T41,T38
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T41,T38
1	-	Covered	T11,T41,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T41,T38
DetectSt	168	Covered	T11,T41,T38
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T41,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T41,T38
DebounceSt->IdleSt	163	Covered	T42,T71,T212
DetectSt->IdleSt	186	Covered	T185,T121
DetectSt->StableSt	191	Covered	T11,T41,T38
IdleSt->DebounceSt	148	Covered	T11,T41,T38
StableSt->IdleSt	206	Covered	T11,T41,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T41,T38
0	1	Covered	T11,T41,T38
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T41,T38
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T41,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T41,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T212,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T41,T38
DetectSt	-	-	-	-	1	-	-	Covered	T185,T121
DetectSt	-	-	-	-	0	1	-	Covered	T11,T41,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T41,T38
StableSt	-	-	-	-	-	-	0	Covered	T11,T41,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	91	0	0
CntIncr_A	8663532	5745	0	0
CntNoWrap_A	8663532	7983182	0	0
DetectStDropOut_A	8663532	2	0	0
DetectedOut_A	8663532	3621	0	0
DetectedPulseOut_A	8663532	42	0	0
DisabledIdleSt_A	8663532	7967172	0	0
DisabledNoDetection_A	8663532	7969505	0	0
EnterDebounceSt_A	8663532	49	0	0
EnterDetectSt_A	8663532	44	0	0
EnterStableSt_A	8663532	42	0	0
PulseIsPulse_A	8663532	42	0	0
StayInStableSt	8663532	3562	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	91	0	0
T11	1622	2	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	4	0	0
T39	0	2	0	0
T41	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	2	0	0
T71	0	1	0	0
T147	0	2	0	0
T148	0	2	0	0
T166	0	2	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	5745	0	0
T11	1622	33	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	106	0	0
T39	0	39	0	0
T41	0	29	0	0
T42	0	178	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	31	0	0
T71	0	27	0	0
T147	0	90	0	0
T148	0	18	0	0
T166	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983182	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2	0	0
T93	16990	0	0	0
T121	0	1	0	0
T185	9498	1	0	0
T212	11735	0	0	0
T213	30423	0	0	0
T214	842	0	0	0
T215	492	0	0	0
T216	850	0	0	0
T217	505	0	0	0
T218	439	0	0	0
T219	418	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3621	0	0
T11	1622	44	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	93	0	0
T39	0	97	0	0
T41	0	70	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	15	0	0
T147	0	147	0	0
T148	0	39	0	0
T149	0	48	0	0
T166	0	157	0	0
T210	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	42	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7967172	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7969505	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	49	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T71	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	44	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	42	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	42	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T166	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3562	0	0
T11	1622	43	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	91	0	0
T39	0	96	0	0
T41	0	69	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	14	0	0
T147	0	145	0	0
T148	0	37	0	0
T149	0	46	0	0
T166	0	156	0	0
T210	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	24	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T164	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T184	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T11,T12,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T24
1	0	Covered	T1,T6,T2
1	1	Covered	T11,T12,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T24
0	1	Covered	T38,T142,T36
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T24
1	-	Covered	T38,T142,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T24
DetectSt	168	Covered	T11,T12,T24
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T12,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T24
DebounceSt->IdleSt	163	Covered	T71
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T12,T24
IdleSt->DebounceSt	148	Covered	T11,T12,T24
StableSt->IdleSt	206	Covered	T38,T142,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T24
0	1	Covered	T11,T12,T24
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T24
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T24
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T24
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T24
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T142,T36
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	61	0	0
CntIncr_A	8663532	6505	0	0
CntNoWrap_A	8663532	7983212	0	0
DetectStDropOut_A	8663532	0	0	0
DetectedOut_A	8663532	14304	0	0
DetectedPulseOut_A	8663532	30	0	0
DisabledIdleSt_A	8663532	7705857	0	0
DisabledNoDetection_A	8663532	7708177	0	0
EnterDebounceSt_A	8663532	31	0	0
EnterDetectSt_A	8663532	30	0	0
EnterStableSt_A	8663532	30	0	0
PulseIsPulse_A	8663532	30	0	0
StayInStableSt	8663532	14256	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	6335	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	61	0	0
T11	1622	2	0	0
T12	597	2	0	0
T24	901	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	4791	0	0	0
T38	0	4	0	0
T41	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T142	0	2	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6505	0	0
T11	1622	33	0	0
T12	597	70	0	0
T24	901	77	0	0
T35	0	85	0	0
T36	0	93	0	0
T37	4791	0	0	0
T38	0	106	0	0
T41	0	29	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	27	0	0
T142	0	65	0	0
T146	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983212	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	14304	0	0
T11	1622	82	0	0
T12	597	41	0	0
T24	901	183	0	0
T35	0	40	0	0
T36	0	1	0	0
T37	4791	0	0	0
T38	0	135	0	0
T39	0	43	0	0
T41	0	71	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	40	0	0
T146	0	17	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	30	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7705857	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7708177	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	31	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T142	0	1	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	30	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	1	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	30	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	30	0	0
T11	1622	1	0	0
T12	597	1	0	0
T24	901	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T142	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	14256	0	0
T11	1622	80	0	0
T12	597	39	0	0
T24	901	181	0	0
T35	0	38	0	0
T37	4791	0	0	0
T38	0	132	0	0
T39	0	41	0	0
T41	0	69	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T116	0	43	0	0
T142	0	39	0	0
T146	0	16	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6335	0	0
T1	28754	14	0	0
T2	127882	21	0	0
T3	19948	32	0	0
T4	1680	0	0	0
T6	17174	24	0	0
T7	0	11	0	0
T13	711	0	0	0
T14	426	3	0	0
T15	421	1	0	0
T16	223329	0	0	0
T17	1471	2	0	0
T21	0	7	0	0
T22	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	11	0	0
T36	0	1	0	0
T38	852	1	0	0
T42	150679	0	0	0
T61	1329	0	0	0
T82	786	0	0	0
T93	0	1	0	0
T118	0	1	0	0
T142	0	1	0	0
T146	0	1	0	0
T154	0	1	0	0
T184	0	1	0	0
T204	477	0	0	0
T205	2253	0	0	0
T206	25691	0	0	0
T207	496	0	0	0
T208	448	0	0	0
T209	405	0	0	0
T212	0	1	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T40,T43,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T40,T43,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T40,T43,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T43,T35
1	0	Covered	T1,T6,T2
1	1	Covered	T40,T43,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T43,T35
0	1	Covered	T36,T178,T223
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T43,T35
0	1	Covered	T43,T35,T36
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T43,T35
1	-	Covered	T43,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T43,T35
DetectSt	168	Covered	T40,T43,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T40,T43,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T43,T35
DebounceSt->IdleSt	163	Covered	T38,T42,T71
DetectSt->IdleSt	186	Covered	T36,T178,T223
DetectSt->StableSt	191	Covered	T40,T43,T35
IdleSt->DebounceSt	148	Covered	T40,T43,T35
StableSt->IdleSt	206	Covered	T43,T35,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T43,T35
0	1	Covered	T40,T43,T35
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T43,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T43,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T43,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T93,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T43,T35
DetectSt	-	-	-	-	1	-	-	Covered	T36,T178,T223
DetectSt	-	-	-	-	0	1	-	Covered	T40,T43,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T40,T43,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	125	0	0
CntIncr_A	8663532	87127	0	0
CntNoWrap_A	8663532	7983148	0	0
DetectStDropOut_A	8663532	3	0	0
DetectedOut_A	8663532	101598	0	0
DetectedPulseOut_A	8663532	57	0	0
DisabledIdleSt_A	8663532	7578432	0	0
DisabledNoDetection_A	8663532	7580748	0	0
EnterDebounceSt_A	8663532	67	0	0
EnterDetectSt_A	8663532	60	0	0
EnterStableSt_A	8663532	56	0	0
PulseIsPulse_A	8663532	56	0	0
StayInStableSt	8663532	101507	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	125	0	0
T26	22383	0	0	0
T35	0	4	0	0
T36	0	4	0	0
T38	0	3	0	0
T39	0	2	0	0
T40	529	2	0	0
T42	0	2	0	0
T43	0	4	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	1	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	87127	0	0
T26	22383	0	0	0
T35	0	170	0	0
T36	0	186	0	0
T38	0	106	0	0
T39	0	39	0	0
T40	529	44	0	0
T42	0	37107	0	0
T43	0	110	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	27	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	61	0	0
T201	0	41896	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983148	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3	0	0
T36	3438	1	0	0
T81	8416	0	0	0
T157	422	0	0	0
T158	16950	0	0	0
T159	804	0	0	0
T160	414	0	0	0
T161	493	0	0	0
T162	646	0	0	0
T163	457	0	0	0
T178	0	1	0	0
T223	0	1	0	0
T224	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	101598	0	0
T26	22383	0	0	0
T35	0	291	0	0
T36	0	65	0	0
T38	0	244	0	0
T39	0	17	0	0
T40	529	41	0	0
T42	0	90365	0	0
T43	0	115	0	0
T44	0	85	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	100	0	0
T201	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	57	0	0
T26	22383	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7578432	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7580748	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	67	0	0
T26	22383	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T71	0	1	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	60	0	0
T26	22383	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	56	0	0
T26	22383	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	56	0	0
T26	22383	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	529	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	101507	0	0
T26	22383	0	0	0
T35	0	288	0	0
T36	0	64	0	0
T38	0	242	0	0
T39	0	16	0	0
T40	529	39	0	0
T42	0	90363	0	0
T43	0	112	0	0
T44	0	82	0	0
T45	11270	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T146	0	99	0	0
T201	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	21	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T43	1539	1	0	0
T44	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	2	0	0
T146	0	1	0	0
T176	0	1	0	0
T185	0	2	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T2
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T2
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T37,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T11,T37,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T37,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T37,T35
1	0	Covered	T1,T6,T2
1	1	Covered	T11,T37,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T35
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T37,T35
0	1	Covered	T11,T35,T36
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T37,T35
1	-	Covered	T11,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T37,T35
DetectSt	168	Covered	T11,T37,T35
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T37,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T37,T35
DebounceSt->IdleSt	163	Covered	T71,T180
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T11,T37,T35
IdleSt->DebounceSt	148	Covered	T11,T37,T35
StableSt->IdleSt	206	Covered	T11,T37,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T37,T35
0	1	Covered	T11,T37,T35
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T37,T35
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T37,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T37,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T180
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T37,T35
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T11,T37,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T11,T37,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	68	0	0
CntIncr_A	8663532	2107	0	0
CntNoWrap_A	8663532	7983205	0	0
DetectStDropOut_A	8663532	1	0	0
DetectedOut_A	8663532	2562	0	0
DetectedPulseOut_A	8663532	32	0	0
DisabledIdleSt_A	8663532	7811421	0	0
DisabledNoDetection_A	8663532	7813745	0	0
EnterDebounceSt_A	8663532	35	0	0
EnterDetectSt_A	8663532	33	0	0
EnterStableSt_A	8663532	32	0	0
PulseIsPulse_A	8663532	32	0	0
StayInStableSt	8663532	2513	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	6328	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	68	0	0
T11	1622	4	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T37	4791	2	0	0
T39	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T116	0	2	0	0
T146	0	2	0	0
T176	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2107	0	0
T11	1622	66	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	85	0	0
T36	0	186	0	0
T37	4791	54	0	0
T39	0	39	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	28	0	0
T116	0	67	0	0
T146	0	61	0	0
T176	0	22	0	0
T202	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983205	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1	0	0
T154	13802	1	0	0
T225	404	0	0	0
T226	502	0	0	0
T227	13801	0	0	0
T228	3396	0	0	0
T229	845	0	0	0
T230	568	0	0	0
T231	435	0	0	0
T232	5479	0	0	0
T233	432	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2562	0	0
T11	1622	127	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	43	0	0
T36	0	81	0	0
T37	4791	37	0	0
T39	0	43	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	17	0	0
T116	0	153	0	0
T146	0	95	0	0
T176	0	48	0	0
T202	0	186	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	32	0	0
T11	1622	2	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	4791	1	0	0
T39	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T116	0	1	0	0
T146	0	1	0	0
T176	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7811421	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7813745	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	35	0	0
T11	1622	2	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	4791	1	0	0
T39	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T116	0	1	0	0
T146	0	1	0	0
T176	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	33	0	0
T11	1622	2	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	4791	1	0	0
T39	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T116	0	1	0	0
T146	0	1	0	0
T176	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	32	0	0
T11	1622	2	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	4791	1	0	0
T39	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T116	0	1	0	0
T146	0	1	0	0
T176	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	32	0	0
T11	1622	2	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	4791	1	0	0
T39	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T116	0	1	0	0
T146	0	1	0	0
T176	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2513	0	0
T11	1622	124	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	42	0	0
T36	0	78	0	0
T37	4791	35	0	0
T39	0	41	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	16	0	0
T116	0	151	0	0
T146	0	93	0	0
T176	0	46	0	0
T202	0	184	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	6328	0	0
T1	28754	12	0	0
T2	127882	16	0	0
T3	19948	26	0	0
T4	1680	0	0	0
T6	17174	21	0	0
T7	0	12	0	0
T13	711	0	0	0
T14	426	4	0	0
T15	421	2	0	0
T16	223329	0	0	0
T17	1471	2	0	0
T21	0	9	0	0
T22	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	14	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T122	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T150	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T6
1	0	Covered	T1,T6,T13
1	1	Covered	T1,T6,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T11,T12,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T11,T12,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T40
1	0	Covered	T1,T6,T13
1	1	Covered	T11,T12,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T40
0	1	Covered	T35,T73,T223
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T40
0	1	Covered	T11,T43,T35
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T40
1	-	Covered	T11,T43,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T40
DetectSt	168	Covered	T11,T12,T40
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T11,T12,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T40
DebounceSt->IdleSt	163	Covered	T42,T71,T164
DetectSt->IdleSt	186	Covered	T35,T73,T223
DetectSt->StableSt	191	Covered	T11,T12,T40
IdleSt->DebounceSt	148	Covered	T11,T12,T40
StableSt->IdleSt	206	Covered	T11,T43,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T40
0	1	Covered	T11,T12,T40
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T40
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T6,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T164,T234
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T40
DetectSt	-	-	-	-	1	-	-	Covered	T35,T73,T223
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T43,T35
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	115	0	0
CntIncr_A	8663532	118707	0	0
CntNoWrap_A	8663532	7983158	0	0
DetectStDropOut_A	8663532	3	0	0
DetectedOut_A	8663532	21937	0	0
DetectedPulseOut_A	8663532	52	0	0
DisabledIdleSt_A	8663532	7733408	0	0
DisabledNoDetection_A	8663532	7735728	0	0
EnterDebounceSt_A	8663532	60	0	0
EnterDetectSt_A	8663532	55	0	0
EnterStableSt_A	8663532	52	0	0
PulseIsPulse_A	8663532	52	0	0
StayInStableSt	8663532	21860	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	115	0	0
T11	1622	4	0	0
T12	597	2	0	0
T24	901	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	4791	0	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	3	0	0
T43	0	2	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	118707	0	0
T11	1622	66	0	0
T12	597	70	0	0
T24	901	0	0	0
T35	0	170	0	0
T36	0	93	0	0
T37	4791	0	0	0
T40	0	44	0	0
T41	0	58	0	0
T42	0	73860	0	0
T43	0	55	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	26	0	0
T201	0	41896	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983158	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T63	1419	0	0	0
T73	0	1	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T177	422	0	0	0
T223	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	21937	0	0
T11	1622	92	0	0
T12	597	41	0	0
T24	901	0	0	0
T35	0	43	0	0
T36	0	65	0	0
T37	4791	0	0	0
T40	0	76	0	0
T41	0	108	0	0
T42	0	43	0	0
T43	0	174	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T73	0	49	0	0
T201	0	17918	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	52	0	0
T11	1622	2	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T73	0	1	0	0
T201	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7733408	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7735728	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	60	0	0
T11	1622	2	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T71	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	55	0	0
T11	1622	2	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T73	0	2	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	52	0	0
T11	1622	2	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T73	0	1	0	0
T201	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	52	0	0
T11	1622	2	0	0
T12	597	1	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T73	0	1	0	0
T201	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	21860	0	0
T11	1622	89	0	0
T12	597	39	0	0
T24	901	0	0	0
T35	0	42	0	0
T36	0	64	0	0
T37	4791	0	0	0
T40	0	74	0	0
T41	0	105	0	0
T42	0	41	0	0
T43	0	173	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T73	0	48	0	0
T201	0	17917	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	26	0	0
T11	1622	1	0	0
T12	597	0	0	0
T24	901	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	4791	0	0	0
T41	0	1	0	0
T43	0	1	0	0
T50	11510	0	0	0
T54	490	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T73	0	1	0	0
T179	0	1	0	0
T201	0	1	0	0
T202	0	1	0	0
T222	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T13
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T24,T35,T71

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T24,T35,T71

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T24,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T24,T40
1	0	Covered	T1,T6,T13
1	1	Covered	T24,T35,T71

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T35,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T35,T36
0	1	Covered	T35,T39,T202
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T35,T36
1	-	Covered	T35,T39,T202

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T35,T71
DetectSt	168	Covered	T24,T35,T36
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T24,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T35,T36
DebounceSt->IdleSt	163	Covered	T71,T145
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T24,T35,T36
IdleSt->DebounceSt	148	Covered	T24,T35,T71
StableSt->IdleSt	206	Covered	T35,T36,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T35,T71
0	1	Covered	T24,T35,T71
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T35,T36
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T35,T71
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T35,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T35,T71
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T24,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T39,T202
StableSt	-	-	-	-	-	-	0	Covered	T24,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	65	0	0
CntIncr_A	8663532	2024	0	0
CntNoWrap_A	8663532	7983208	0	0
DetectStDropOut_A	8663532	0	0	0
DetectedOut_A	8663532	3266	0	0
DetectedPulseOut_A	8663532	32	0	0
DisabledIdleSt_A	8663532	7811310	0	0
DisabledNoDetection_A	8663532	7813637	0	0
EnterDebounceSt_A	8663532	34	0	0
EnterDetectSt_A	8663532	32	0	0
EnterStableSt_A	8663532	32	0	0
PulseIsPulse_A	8663532	32	0	0
StayInStableSt	8663532	3218	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8663532	7128	0	0
gen_low_level_sva.LowLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	65	0	0
T24	901	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T37	4791	0	0	0
T39	0	2	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	2	0	0
T60	1349	0	0	0
T64	522	0	0	0
T71	0	1	0	0
T122	0	2	0	0
T145	0	2	0	0
T183	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2024	0	0
T24	901	77	0	0
T35	0	170	0	0
T36	0	93	0	0
T37	4791	0	0	0
T39	0	39	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	31	0	0
T60	1349	0	0	0
T64	522	0	0	0
T71	0	27	0	0
T122	0	75	0	0
T145	0	59	0	0
T183	0	71	0	0
T202	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7983208	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3266	0	0
T24	901	305	0	0
T35	0	290	0	0
T36	0	269	0	0
T37	4791	0	0	0
T39	0	98	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	15	0	0
T60	1349	0	0	0
T64	522	0	0	0
T122	0	39	0	0
T145	0	76	0	0
T164	0	91	0	0
T183	0	50	0	0
T202	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	32	0	0
T24	901	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T64	522	0	0	0
T122	0	1	0	0
T145	0	1	0	0
T164	0	1	0	0
T183	0	1	0	0
T202	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7811310	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7813637	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	34	0	0
T24	901	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T64	522	0	0	0
T71	0	1	0	0
T122	0	1	0	0
T145	0	2	0	0
T183	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	32	0	0
T24	901	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T64	522	0	0	0
T122	0	1	0	0
T145	0	1	0	0
T164	0	1	0	0
T183	0	1	0	0
T202	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	32	0	0
T24	901	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T64	522	0	0	0
T122	0	1	0	0
T145	0	1	0	0
T164	0	1	0	0
T183	0	1	0	0
T202	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	32	0	0
T24	901	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	4791	0	0	0
T39	0	1	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T64	522	0	0	0
T122	0	1	0	0
T145	0	1	0	0
T164	0	1	0	0
T183	0	1	0	0
T202	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3218	0	0
T24	901	303	0	0
T35	0	287	0	0
T36	0	267	0	0
T37	4791	0	0	0
T39	0	97	0	0
T40	529	0	0	0
T50	11510	0	0	0
T55	503	0	0	0
T56	490	0	0	0
T57	507	0	0	0
T58	491	0	0	0
T59	0	14	0	0
T60	1349	0	0	0
T64	522	0	0	0
T122	0	38	0	0
T145	0	75	0	0
T164	0	89	0	0
T183	0	49	0	0
T202	0	129	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7128	0	0
T1	28754	10	0	0
T2	127882	22	0	0
T3	19948	22	0	0
T4	1680	7	0	0
T6	17174	25	0	0
T7	0	11	0	0
T13	711	3	0	0
T14	426	3	0	0
T15	421	3	0	0
T16	223329	0	0	0
T17	1471	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	15	0	0
T31	512	0	0	0
T34	19996	0	0	0
T35	1086	1	0	0
T39	0	1	0	0
T63	1419	0	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0
T106	12387	0	0	0
T118	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T177	422	0	0	0
T183	0	1	0	0
T184	0	1	0	0
T202	0	1	0	0