Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T3,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T26
0	1	Covered	T67,T69,T85
1	0	Covered	T67,T85,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T26
0	1	Covered	T6,T3,T26
1	0	Covered	T235

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T3,T26
1	-	Covered	T6,T3,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T3,T26
DetectSt	168	Covered	T6,T3,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T6,T3,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T3,T26
DebounceSt->IdleSt	163	Covered	T45,T71,T81
DetectSt->IdleSt	186	Covered	T67,T69,T85
DetectSt->StableSt	191	Covered	T6,T3,T26
IdleSt->DebounceSt	148	Covered	T6,T3,T26
StableSt->IdleSt	206	Covered	T6,T3,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T3,T26
0	1	Covered	T6,T3,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T3,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T3,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T3,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T3,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T71,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T3,T26
DetectSt	-	-	-	-	1	-	-	Covered	T67,T69,T85
DetectSt	-	-	-	-	0	1	-	Covered	T6,T3,T26
DetectSt	-	-	-	-	0	0	-	Covered	T6,T3,T26
StableSt	-	-	-	-	-	-	1	Covered	T6,T3,T26
StableSt	-	-	-	-	-	-	0	Covered	T6,T3,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	3081	0	0
CntIncr_A	8663532	124950	0	0
CntNoWrap_A	8663532	7980192	0	0
DetectStDropOut_A	8663532	427	0	0
DetectedOut_A	8663532	76969	0	0
DetectedPulseOut_A	8663532	887	0	0
DisabledIdleSt_A	8663532	7461477	0	0
DisabledNoDetection_A	8663532	7463665	0	0
EnterDebounceSt_A	8663532	1567	0	0
EnterDetectSt_A	8663532	1514	0	0
EnterStableSt_A	8663532	887	0	0
PulseIsPulse_A	8663532	887	0	0
StayInStableSt	8663532	75987	0	0
gen_high_event_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	779	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	3081	0	0
T2	127882	0	0	0
T3	19948	16	0	0
T4	1680	0	0	0
T6	17174	16	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	44	0	0
T31	0	2	0	0
T34	0	26	0	0
T45	0	15	0	0
T46	0	16	0	0
T66	0	32	0	0
T67	0	52	0	0
T68	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	124950	0	0
T2	127882	0	0	0
T3	19948	424	0	0
T4	1680	0	0	0
T6	17174	472	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1474	0	0
T31	0	21	0	0
T34	0	832	0	0
T45	0	1955	0	0
T46	0	464	0	0
T66	0	1424	0	0
T67	0	2126	0	0
T68	0	6370	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7980192	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19489	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16736	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	427	0	0
T41	609	0	0	0
T67	14533	9	0	0
T68	18647	0	0	0
T69	5321	30	0	0
T71	0	1	0	0
T85	0	10	0	0
T86	0	15	0	0
T87	0	8	0	0
T88	0	10	0	0
T236	0	23	0	0
T237	0	28	0	0
T238	0	6	0	0
T239	402	0	0	0
T240	425	0	0	0
T241	493	0	0	0
T242	497	0	0	0
T243	522	0	0	0
T244	33784	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	76969	0	0
T2	127882	0	0	0
T3	19948	478	0	0
T4	1680	0	0	0
T6	17174	1500	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1665	0	0
T31	0	86	0	0
T34	0	602	0	0
T45	0	696	0	0
T46	0	699	0	0
T66	0	1142	0	0
T68	0	3578	0	0
T245	0	1493	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	887	0	0
T2	127882	0	0	0
T3	19948	8	0	0
T4	1680	0	0	0
T6	17174	8	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	22	0	0
T31	0	1	0	0
T34	0	13	0	0
T45	0	5	0	0
T46	0	8	0	0
T66	0	16	0	0
T68	0	26	0	0
T245	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7461477	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	15851	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	10072	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7463665	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	15855	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	10072	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1567	0	0
T2	127882	0	0	0
T3	19948	8	0	0
T4	1680	0	0	0
T6	17174	8	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	22	0	0
T31	0	1	0	0
T34	0	13	0	0
T45	0	10	0	0
T46	0	8	0	0
T66	0	16	0	0
T67	0	26	0	0
T68	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1514	0	0
T2	127882	0	0	0
T3	19948	8	0	0
T4	1680	0	0	0
T6	17174	8	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	22	0	0
T31	0	1	0	0
T34	0	13	0	0
T45	0	5	0	0
T46	0	8	0	0
T66	0	16	0	0
T67	0	26	0	0
T68	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	887	0	0
T2	127882	0	0	0
T3	19948	8	0	0
T4	1680	0	0	0
T6	17174	8	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	22	0	0
T31	0	1	0	0
T34	0	13	0	0
T45	0	5	0	0
T46	0	8	0	0
T66	0	16	0	0
T68	0	26	0	0
T245	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	887	0	0
T2	127882	0	0	0
T3	19948	8	0	0
T4	1680	0	0	0
T6	17174	8	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	22	0	0
T31	0	1	0	0
T34	0	13	0	0
T45	0	5	0	0
T46	0	8	0	0
T66	0	16	0	0
T68	0	26	0	0
T245	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	75987	0	0
T2	127882	0	0	0
T3	19948	468	0	0
T4	1680	0	0	0
T6	17174	1488	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1638	0	0
T31	0	84	0	0
T34	0	588	0	0
T45	0	691	0	0
T46	0	690	0	0
T66	0	1124	0	0
T68	0	3552	0	0
T245	0	1469	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	779	0	0
T2	127882	0	0	0
T3	19948	6	0	0
T4	1680	0	0	0
T6	17174	4	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	17	0	0
T34	0	12	0	0
T45	0	5	0	0
T46	0	7	0	0
T66	0	14	0	0
T68	0	26	0	0
T245	0	24	0	0
T246	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T2,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T6,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T2,T3
1	0	Covered	T1,T6,T2
1	1	Covered	T6,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T7
0	1	Covered	T32,T89,T90
1	0	Covered	T71,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T7
0	1	Covered	T3,T7,T9
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T3,T7
1	-	Covered	T3,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T2,T3
DetectSt	168	Covered	T6,T3,T7
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T6,T3,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T3,T7
DebounceSt->IdleSt	163	Covered	T2,T7,T10
DetectSt->IdleSt	186	Covered	T32,T71,T89
DetectSt->StableSt	191	Covered	T6,T3,T7
IdleSt->DebounceSt	148	Covered	T6,T2,T3
StableSt->IdleSt	206	Covered	T6,T3,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T2,T3
0	1	Covered	T6,T2,T3
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T3,T7
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T7,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T32,T71,T89
DetectSt	-	-	-	-	0	1	-	Covered	T6,T3,T7
DetectSt	-	-	-	-	0	0	-	Covered	T6,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T6,T3,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	775	0	0
CntIncr_A	8663532	39457	0	0
CntNoWrap_A	8663532	7982498	0	0
DetectStDropOut_A	8663532	46	0	0
DetectedOut_A	8663532	11492	0	0
DetectedPulseOut_A	8663532	298	0	0
DisabledIdleSt_A	8663532	7639735	0	0
DisabledNoDetection_A	8663532	7641424	0	0
EnterDebounceSt_A	8663532	428	0	0
EnterDetectSt_A	8663532	349	0	0
EnterStableSt_A	8663532	298	0	0
PulseIsPulse_A	8663532	298	0	0
StayInStableSt	8663532	11172	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	273	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	775	0	0
T2	127882	1	0	0
T3	19948	2	0	0
T4	1680	0	0	0
T6	17174	8	0	0
T7	11518	8	0	0
T9	0	8	0	0
T10	0	3	0	0
T11	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	5	0	0
T48	0	1	0	0
T50	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	39457	0	0
T2	127882	20	0	0
T3	19948	50	0	0
T4	1680	0	0	0
T6	17174	280	0	0
T7	11518	600	0	0
T9	0	304	0	0
T10	0	185	0	0
T11	0	20	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T37	0	18	0	0
T48	0	20	0	0
T50	0	147	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7982498	0	0
T1	28754	28290	0	0
T2	127882	124056	0	0
T3	19948	19503	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16744	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	46	0	0
T31	512	0	0	0
T32	16177	4	0	0
T34	19996	0	0	0
T35	1086	0	0	0
T43	1539	0	0	0
T63	1419	0	0	0
T89	0	3	0	0
T90	0	4	0	0
T91	0	4	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	7	0	0
T96	0	2	0	0
T98	0	3	0	0
T102	501	0	0	0
T103	428	0	0	0
T104	537	0	0	0
T105	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	11492	0	0
T2	127882	0	0	0
T3	19948	77	0	0
T4	1680	0	0	0
T6	17174	146	0	0
T7	11518	137	0	0
T9	0	62	0	0
T10	0	5	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	114	0	0
T31	0	3	0	0
T34	0	44	0	0
T50	0	5	0	0
T106	0	182	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	298	0	0
T2	127882	0	0	0
T3	19948	1	0	0
T4	1680	0	0	0
T6	17174	4	0	0
T7	11518	3	0	0
T9	0	4	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	2	0	0
T31	0	1	0	0
T34	0	1	0	0
T50	0	1	0	0
T106	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7639735	0	0
T1	28754	28290	0	0
T2	127882	124025	0	0
T3	19948	19029	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	15256	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7641424	0	0
T1	28754	28302	0	0
T2	127882	124033	0	0
T3	19948	19034	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	15257	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	428	0	0
T2	127882	1	0	0
T3	19948	1	0	0
T4	1680	0	0	0
T6	17174	4	0	0
T7	11518	5	0	0
T9	0	4	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T37	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	349	0	0
T2	127882	0	0	0
T3	19948	1	0	0
T4	1680	0	0	0
T6	17174	4	0	0
T7	11518	3	0	0
T9	0	4	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	2	0	0
T31	0	1	0	0
T32	0	4	0	0
T34	0	1	0	0
T50	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	298	0	0
T2	127882	0	0	0
T3	19948	1	0	0
T4	1680	0	0	0
T6	17174	4	0	0
T7	11518	3	0	0
T9	0	4	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	2	0	0
T31	0	1	0	0
T34	0	1	0	0
T50	0	1	0	0
T106	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	298	0	0
T2	127882	0	0	0
T3	19948	1	0	0
T4	1680	0	0	0
T6	17174	4	0	0
T7	11518	3	0	0
T9	0	4	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	2	0	0
T31	0	1	0	0
T34	0	1	0	0
T50	0	1	0	0
T106	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	11172	0	0
T2	127882	0	0	0
T3	19948	76	0	0
T4	1680	0	0	0
T6	17174	138	0	0
T7	11518	134	0	0
T9	0	58	0	0
T10	0	4	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	110	0	0
T31	0	2	0	0
T34	0	42	0	0
T50	0	4	0	0
T106	0	179	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	273	0	0
T3	19948	1	0	0
T4	1680	0	0	0
T7	11518	3	0	0
T8	1282	0	0	0
T9	0	4	0	0
T10	0	1	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T31	0	1	0	0
T42	0	3	0	0
T50	0	1	0	0
T53	558	0	0	0
T66	0	3	0	0
T68	0	1	0	0
T106	0	3	0	0
T112	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T3,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T26
0	1	Covered	T26,T67,T69
1	0	Covered	T26,T67,T245

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T45
0	1	Covered	T6,T3,T45
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T3,T45
1	-	Covered	T6,T3,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T3,T26
DetectSt	168	Covered	T6,T3,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T6,T3,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T3,T26
DebounceSt->IdleSt	163	Covered	T45,T71,T81
DetectSt->IdleSt	186	Covered	T26,T67,T69
DetectSt->StableSt	191	Covered	T6,T3,T45
IdleSt->DebounceSt	148	Covered	T6,T3,T26
StableSt->IdleSt	206	Covered	T6,T3,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T3,T26
0	1	Covered	T6,T3,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T3,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T3,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T3,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T3,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T71,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T3,T26
DetectSt	-	-	-	-	1	-	-	Covered	T26,T67,T69
DetectSt	-	-	-	-	0	1	-	Covered	T6,T3,T45
DetectSt	-	-	-	-	0	0	-	Covered	T6,T3,T26
StableSt	-	-	-	-	-	-	1	Covered	T6,T3,T45
StableSt	-	-	-	-	-	-	0	Covered	T6,T3,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	2913	0	0
CntIncr_A	8663532	119605	0	0
CntNoWrap_A	8663532	7980360	0	0
DetectStDropOut_A	8663532	420	0	0
DetectedOut_A	8663532	74341	0	0
DetectedPulseOut_A	8663532	730	0	0
DisabledIdleSt_A	8663532	7466540	0	0
DisabledNoDetection_A	8663532	7468751	0	0
EnterDebounceSt_A	8663532	1488	0	0
EnterDetectSt_A	8663532	1427	0	0
EnterStableSt_A	8663532	730	0	0
PulseIsPulse_A	8663532	730	0	0
StayInStableSt	8663532	73537	0	0
gen_high_event_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	652	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2913	0	0
T2	127882	0	0	0
T3	19948	44	0	0
T4	1680	0	0	0
T6	17174	4	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	56	0	0
T34	0	30	0	0
T45	0	22	0	0
T46	0	24	0	0
T66	0	10	0	0
T67	0	46	0	0
T68	0	34	0	0
T69	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	119605	0	0
T2	127882	0	0	0
T3	19948	1254	0	0
T4	1680	0	0	0
T6	17174	140	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1923	0	0
T34	0	1320	0	0
T45	0	2694	0	0
T46	0	708	0	0
T66	0	305	0	0
T67	0	1881	0	0
T68	0	3757	0	0
T69	0	1297	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7980360	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19461	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16748	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	420	0	0
T26	22383	6	0	0
T45	11270	0	0	0
T46	16107	0	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T65	503	0	0	0
T67	0	3	0	0
T69	0	24	0	0
T71	0	1	0	0
T85	0	10	0	0
T87	0	11	0	0
T107	505	0	0	0
T108	3053	0	0	0
T109	421	0	0	0
T158	0	7	0	0
T245	0	12	0	0
T246	0	17	0	0
T247	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	74341	0	0
T2	127882	0	0	0
T3	19948	2252	0	0
T4	1680	0	0	0
T6	17174	296	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T34	0	1244	0	0
T45	0	1195	0	0
T46	0	920	0	0
T66	0	196	0	0
T68	0	533	0	0
T71	0	367	0	0
T86	0	422	0	0
T248	0	164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	730	0	0
T2	127882	0	0	0
T3	19948	22	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T34	0	15	0	0
T45	0	8	0	0
T46	0	12	0	0
T66	0	5	0	0
T68	0	17	0	0
T71	0	5	0	0
T86	0	10	0	0
T248	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7466540	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	14102	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	10959	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7468751	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	14102	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	10962	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1488	0	0
T2	127882	0	0	0
T3	19948	22	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	28	0	0
T34	0	15	0	0
T45	0	14	0	0
T46	0	12	0	0
T66	0	5	0	0
T67	0	23	0	0
T68	0	17	0	0
T69	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1427	0	0
T2	127882	0	0	0
T3	19948	22	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	28	0	0
T34	0	15	0	0
T45	0	8	0	0
T46	0	12	0	0
T66	0	5	0	0
T67	0	23	0	0
T68	0	17	0	0
T69	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	730	0	0
T2	127882	0	0	0
T3	19948	22	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T34	0	15	0	0
T45	0	8	0	0
T46	0	12	0	0
T66	0	5	0	0
T68	0	17	0	0
T71	0	5	0	0
T86	0	10	0	0
T248	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	730	0	0
T2	127882	0	0	0
T3	19948	22	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T34	0	15	0	0
T45	0	8	0	0
T46	0	12	0	0
T66	0	5	0	0
T68	0	17	0	0
T71	0	5	0	0
T86	0	10	0	0
T248	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	73537	0	0
T2	127882	0	0	0
T3	19948	2224	0	0
T4	1680	0	0	0
T6	17174	293	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T34	0	1228	0	0
T45	0	1187	0	0
T46	0	907	0	0
T66	0	191	0	0
T68	0	516	0	0
T71	0	362	0	0
T86	0	412	0	0
T248	0	158	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	652	0	0
T2	127882	0	0	0
T3	19948	16	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T34	0	14	0	0
T45	0	8	0	0
T46	0	11	0	0
T66	0	5	0	0
T68	0	17	0	0
T71	0	5	0	0
T86	0	10	0	0
T248	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T6,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T3
0	1	Covered	T9,T10,T50
1	0	Covered	T71,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T3
0	1	Covered	T1,T3,T7
1	0	Covered	T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T3
1	-	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T3
DetectSt	168	Covered	T1,T6,T3
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T6,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T3
DebounceSt->IdleSt	163	Covered	T10,T32,T206
DetectSt->IdleSt	186	Covered	T9,T10,T50
DetectSt->StableSt	191	Covered	T1,T6,T3
IdleSt->DebounceSt	148	Covered	T1,T6,T3
StableSt->IdleSt	206	Covered	T1,T6,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T3
0	1	Covered	T1,T6,T3
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T3
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T3
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T32,T206
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T3
DetectSt	-	-	-	-	1	-	-	Covered	T9,T10,T50
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	828	0	0
CntIncr_A	8663532	47793	0	0
CntNoWrap_A	8663532	7982445	0	0
DetectStDropOut_A	8663532	88	0	0
DetectedOut_A	8663532	14432	0	0
DetectedPulseOut_A	8663532	297	0	0
DisabledIdleSt_A	8663532	7641778	0	0
DisabledNoDetection_A	8663532	7643534	0	0
EnterDebounceSt_A	8663532	439	0	0
EnterDetectSt_A	8663532	391	0	0
EnterStableSt_A	8663532	297	0	0
PulseIsPulse_A	8663532	297	0	0
StayInStableSt	8663532	14103	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	263	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	828	0	0
T1	28754	4	0	0
T2	127882	0	0	0
T3	19948	12	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	0	4	0	0
T9	0	16	0	0
T10	0	3	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	14	0	0
T34	0	4	0	0
T50	0	2	0	0
T106	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	47793	0	0
T1	28754	124	0	0
T2	127882	0	0	0
T3	19948	378	0	0
T4	1680	0	0	0
T6	17174	45	0	0
T7	0	350	0	0
T9	0	740	0	0
T10	0	190	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	264	0	0
T34	0	164	0	0
T50	0	152	0	0
T106	0	300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7982445	0	0
T1	28754	28286	0	0
T2	127882	124057	0	0
T3	19948	19493	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16750	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	88	0	0
T9	18971	8	0	0
T10	12041	1	0	0
T11	1622	0	0	0
T12	597	0	0	0
T42	0	2	0	0
T47	610	0	0	0
T48	14447	0	0	0
T49	747	0	0	0
T50	0	1	0	0
T54	490	0	0	0
T89	0	3	0	0
T100	427	0	0	0
T101	440	0	0	0
T114	0	6	0	0
T206	0	8	0	0
T249	0	11	0	0
T250	0	7	0	0
T251	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	14432	0	0
T1	28754	119	0	0
T2	127882	0	0	0
T3	19948	383	0	0
T4	1680	0	0	0
T6	17174	61	0	0
T7	0	24	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	63	0	0
T34	0	137	0	0
T71	0	93	0	0
T106	0	129	0	0
T252	0	90	0	0
T253	0	168	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	297	0	0
T1	28754	2	0	0
T2	127882	0	0	0
T3	19948	6	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	2	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	6	0	0
T34	0	2	0	0
T71	0	1	0	0
T106	0	3	0	0
T252	0	5	0	0
T253	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7641778	0	0
T1	28754	24173	0	0
T2	127882	124057	0	0
T3	19948	17259	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16457	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7643534	0	0
T1	28754	24173	0	0
T2	127882	124066	0	0
T3	19948	17260	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16461	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	439	0	0
T1	28754	2	0	0
T2	127882	0	0	0
T3	19948	6	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	2	0	0
T9	0	8	0	0
T10	0	2	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	8	0	0
T34	0	2	0	0
T50	0	1	0	0
T106	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	391	0	0
T1	28754	2	0	0
T2	127882	0	0	0
T3	19948	6	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	2	0	0
T9	0	8	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	6	0	0
T34	0	2	0	0
T50	0	1	0	0
T106	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	297	0	0
T1	28754	2	0	0
T2	127882	0	0	0
T3	19948	6	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	2	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	6	0	0
T34	0	2	0	0
T71	0	1	0	0
T106	0	3	0	0
T252	0	5	0	0
T253	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	297	0	0
T1	28754	2	0	0
T2	127882	0	0	0
T3	19948	6	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	2	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	6	0	0
T34	0	2	0	0
T71	0	1	0	0
T106	0	3	0	0
T252	0	5	0	0
T253	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	14103	0	0
T1	28754	117	0	0
T2	127882	0	0	0
T3	19948	377	0	0
T4	1680	0	0	0
T6	17174	59	0	0
T7	0	22	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	57	0	0
T34	0	134	0	0
T71	0	92	0	0
T106	0	126	0	0
T252	0	85	0	0
T253	0	164	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	263	0	0
T1	28754	2	0	0
T2	127882	0	0	0
T3	19948	6	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	2	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	6	0	0
T33	0	9	0	0
T34	0	1	0	0
T106	0	3	0	0
T252	0	5	0	0
T253	0	4	0	0
T254	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T3,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T26
0	1	Covered	T3,T69,T245
1	0	Covered	T3,T68,T245

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T26,T45
0	1	Covered	T6,T26,T45
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T26,T45
1	-	Covered	T6,T26,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T3,T26
DetectSt	168	Covered	T6,T3,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T6,T26,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T3,T26
DebounceSt->IdleSt	163	Covered	T45,T71,T81
DetectSt->IdleSt	186	Covered	T3,T68,T69
DetectSt->StableSt	191	Covered	T6,T26,T45
IdleSt->DebounceSt	148	Covered	T6,T3,T26
StableSt->IdleSt	206	Covered	T6,T26,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T3,T26
0	1	Covered	T6,T3,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T3,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T3,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T3,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T3,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T71,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T3,T26
DetectSt	-	-	-	-	1	-	-	Covered	T3,T68,T69
DetectSt	-	-	-	-	0	1	-	Covered	T6,T26,T45
DetectSt	-	-	-	-	0	0	-	Covered	T6,T3,T26
StableSt	-	-	-	-	-	-	1	Covered	T6,T26,T45
StableSt	-	-	-	-	-	-	0	Covered	T6,T26,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	2917	0	0
CntIncr_A	8663532	111017	0	0
CntNoWrap_A	8663532	7980356	0	0
DetectStDropOut_A	8663532	322	0	0
DetectedOut_A	8663532	84105	0	0
DetectedPulseOut_A	8663532	948	0	0
DisabledIdleSt_A	8663532	7459725	0	0
DisabledNoDetection_A	8663532	7461927	0	0
EnterDebounceSt_A	8663532	1491	0	0
EnterDetectSt_A	8663532	1427	0	0
EnterStableSt_A	8663532	948	0	0
PulseIsPulse_A	8663532	948	0	0
StayInStableSt	8663532	83075	0	0
gen_high_event_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	864	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2917	0	0
T2	127882	0	0	0
T3	19948	46	0	0
T4	1680	0	0	0
T6	17174	6	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	48	0	0
T34	0	32	0	0
T45	0	22	0	0
T46	0	48	0	0
T66	0	44	0	0
T67	0	32	0	0
T68	0	12	0	0
T69	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	111017	0	0
T2	127882	0	0	0
T3	19948	1391	0	0
T4	1680	0	0	0
T6	17174	165	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1464	0	0
T34	0	1408	0	0
T45	0	2798	0	0
T46	0	2040	0	0
T66	0	1650	0	0
T67	0	880	0	0
T68	0	1502	0	0
T69	0	372	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7980356	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19459	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16746	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	322	0	0
T3	19948	14	0	0
T4	1680	0	0	0
T7	11518	0	0	0
T8	1282	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T53	558	0	0	0
T59	0	1	0	0
T69	0	7	0	0
T71	0	1	0	0
T87	0	9	0	0
T112	407	0	0	0
T236	0	19	0	0
T237	0	15	0	0
T238	0	6	0	0
T245	0	8	0	0
T255	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	84105	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	381	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1360	0	0
T34	0	493	0	0
T45	0	1091	0	0
T46	0	1692	0	0
T66	0	2036	0	0
T67	0	584	0	0
T85	0	1164	0	0
T246	0	1739	0	0
T248	0	1996	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	948	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	3	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	24	0	0
T34	0	16	0	0
T45	0	8	0	0
T46	0	24	0	0
T66	0	22	0	0
T67	0	16	0	0
T85	0	8	0	0
T246	0	20	0	0
T248	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7459725	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	16278	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	10958	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7461927	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	16284	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	10961	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1491	0	0
T2	127882	0	0	0
T3	19948	23	0	0
T4	1680	0	0	0
T6	17174	3	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	24	0	0
T34	0	16	0	0
T45	0	14	0	0
T46	0	24	0	0
T66	0	22	0	0
T67	0	16	0	0
T68	0	6	0	0
T69	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1427	0	0
T2	127882	0	0	0
T3	19948	23	0	0
T4	1680	0	0	0
T6	17174	3	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	24	0	0
T34	0	16	0	0
T45	0	8	0	0
T46	0	24	0	0
T66	0	22	0	0
T67	0	16	0	0
T68	0	6	0	0
T69	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	948	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	3	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	24	0	0
T34	0	16	0	0
T45	0	8	0	0
T46	0	24	0	0
T66	0	22	0	0
T67	0	16	0	0
T85	0	8	0	0
T246	0	20	0	0
T248	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	948	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	3	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	24	0	0
T34	0	16	0	0
T45	0	8	0	0
T46	0	24	0	0
T66	0	22	0	0
T67	0	16	0	0
T85	0	8	0	0
T246	0	20	0	0
T248	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	83075	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	377	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1331	0	0
T34	0	475	0	0
T45	0	1083	0	0
T46	0	1665	0	0
T66	0	2011	0	0
T67	0	567	0	0
T85	0	1152	0	0
T246	0	1715	0	0
T248	0	1967	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	864	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	19	0	0
T34	0	14	0	0
T45	0	8	0	0
T46	0	21	0	0
T66	0	19	0	0
T67	0	15	0	0
T85	0	4	0	0
T246	0	16	0	0
T248	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T50,T32,T106
1	0	Covered	T71,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T7,T10
1	0	Covered	T71,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T7
1	-	Covered	T1,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T7
DetectSt	168	Covered	T1,T6,T7
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T7
DebounceSt->IdleSt	163	Covered	T32,T42,T252
DetectSt->IdleSt	186	Covered	T50,T32,T106
DetectSt->StableSt	191	Covered	T1,T6,T7
IdleSt->DebounceSt	148	Covered	T1,T6,T7
StableSt->IdleSt	206	Covered	T1,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T32,T42,T252
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T50,T32,T106
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	740	0	0
CntIncr_A	8663532	42766	0	0
CntNoWrap_A	8663532	7982533	0	0
DetectStDropOut_A	8663532	59	0	0
DetectedOut_A	8663532	14207	0	0
DetectedPulseOut_A	8663532	288	0	0
DisabledIdleSt_A	8663532	7616553	0	0
DisabledNoDetection_A	8663532	7618275	0	0
EnterDebounceSt_A	8663532	391	0	0
EnterDetectSt_A	8663532	351	0	0
EnterStableSt_A	8663532	288	0	0
PulseIsPulse_A	8663532	288	0	0
StayInStableSt	8663532	13891	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	256	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	740	0	0
T1	28754	12	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	0	2	0	0
T10	0	2	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	10	0	0
T32	0	15	0	0
T34	0	4	0	0
T46	0	4	0	0
T50	0	2	0	0
T106	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	42766	0	0
T1	28754	702	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	77	0	0
T7	0	100	0	0
T10	0	110	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	330	0	0
T32	0	358	0	0
T34	0	144	0	0
T46	0	150	0	0
T50	0	152	0	0
T106	0	286	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7982533	0	0
T1	28754	28278	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16750	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	59	0	0
T26	22383	0	0	0
T32	0	7	0	0
T37	4791	0	0	0
T40	529	0	0	0
T50	11510	1	0	0
T58	491	0	0	0
T59	0	1	0	0
T60	1349	0	0	0
T64	522	0	0	0
T65	503	0	0	0
T83	438	0	0	0
T84	915	0	0	0
T94	0	11	0	0
T96	0	1	0	0
T106	0	2	0	0
T114	0	3	0	0
T256	0	3	0	0
T257	0	1	0	0
T258	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	14207	0	0
T1	28754	25	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	29	0	0
T7	0	87	0	0
T10	0	33	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	254	0	0
T34	0	159	0	0
T46	0	68	0	0
T66	0	254	0	0
T206	0	54	0	0
T246	0	100	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	288	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	1	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	5	0	0
T34	0	2	0	0
T46	0	2	0	0
T66	0	3	0	0
T206	0	3	0	0
T246	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7616553	0	0
T1	28754	24173	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16372	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7618275	0	0
T1	28754	24173	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16376	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	391	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	1	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	5	0	0
T32	0	8	0	0
T34	0	2	0	0
T46	0	2	0	0
T50	0	1	0	0
T106	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	351	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	1	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	5	0	0
T32	0	7	0	0
T34	0	2	0	0
T46	0	2	0	0
T50	0	1	0	0
T106	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	288	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	1	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	5	0	0
T34	0	2	0	0
T46	0	2	0	0
T66	0	3	0	0
T206	0	3	0	0
T246	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	288	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	1	0	0
T7	0	1	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	5	0	0
T34	0	2	0	0
T46	0	2	0	0
T66	0	3	0	0
T206	0	3	0	0
T246	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	13891	0	0
T1	28754	19	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	27	0	0
T7	0	86	0	0
T10	0	32	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	249	0	0
T34	0	157	0	0
T46	0	64	0	0
T66	0	251	0	0
T206	0	51	0	0
T246	0	94	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	256	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	1	0	0
T10	0	1	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	5	0	0
T34	0	2	0	0
T66	0	3	0	0
T85	0	4	0	0
T206	0	3	0	0
T248	0	2	0	0
T249	0	1	0	0