Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T3,T26
1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T6,T3,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T26
0	1	Covered	T6,T3,T69
1	0	Covered	T6,T3,T26

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T34
0	1	Covered	T45,T46,T34
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T34
1	-	Covered	T45,T46,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T3,T26
DetectSt	168	Covered	T6,T3,T26
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T45,T46,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T3,T26
DebounceSt->IdleSt	163	Covered	T45,T71,T81
DetectSt->IdleSt	186	Covered	T6,T3,T26
DetectSt->StableSt	191	Covered	T45,T46,T34
IdleSt->DebounceSt	148	Covered	T6,T3,T26
StableSt->IdleSt	206	Covered	T45,T46,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T3,T26
0	1	Covered	T6,T3,T26
0	0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T3,T26
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T3,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T3,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T3,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T71,T81
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T3,T26
DetectSt	-	-	-	-	1	-	-	Covered	T6,T3,T26
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T34
DetectSt	-	-	-	-	0	0	-	Covered	T6,T3,T26
StableSt	-	-	-	-	-	-	1	Covered	T45,T46,T34
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	2936	0	0
CntIncr_A	8663532	115583	0	0
CntNoWrap_A	8663532	7980337	0	0
DetectStDropOut_A	8663532	445	0	0
DetectedOut_A	8663532	74445	0	0
DetectedPulseOut_A	8663532	753	0	0
DisabledIdleSt_A	8663532	7465398	0	0
DisabledNoDetection_A	8663532	7467603	0	0
EnterDebounceSt_A	8663532	1492	0	0
EnterDetectSt_A	8663532	1444	0	0
EnterStableSt_A	8663532	753	0	0
PulseIsPulse_A	8663532	753	0	0
StayInStableSt	8663532	73614	0	0
gen_high_event_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	674	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	2936	0	0
T2	127882	0	0	0
T3	19948	56	0	0
T4	1680	0	0	0
T6	17174	10	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	48	0	0
T34	0	30	0	0
T45	0	10	0	0
T46	0	48	0	0
T66	0	22	0	0
T67	0	54	0	0
T68	0	34	0	0
T69	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	115583	0	0
T2	127882	0	0	0
T3	19948	1688	0	0
T4	1680	0	0	0
T6	17174	534	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	1652	0	0
T34	0	1230	0	0
T45	0	1478	0	0
T46	0	1416	0	0
T66	0	935	0	0
T67	0	1242	0	0
T68	0	4182	0	0
T69	0	159	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7980337	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	19449	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16742	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	445	0	0
T2	127882	0	0	0
T3	19948	18	0	0
T4	1680	0	0	0
T6	17174	2	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T69	0	3	0	0
T71	0	1	0	0
T85	0	6	0	0
T86	0	3	0	0
T87	0	15	0	0
T88	0	13	0	0
T158	0	1	0	0
T247	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	74445	0	0
T34	0	1324	0	0
T45	11270	307	0	0
T46	16107	2322	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T66	0	1304	0	0
T67	0	2710	0	0
T68	0	109	0	0
T71	0	406	0	0
T81	0	482	0	0
T107	505	0	0	0
T108	3053	0	0	0
T109	421	0	0	0
T110	522	0	0	0
T248	0	942	0	0
T259	0	1725	0	0
T260	622	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	753	0	0
T34	0	15	0	0
T45	11270	2	0	0
T46	16107	24	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T66	0	11	0	0
T67	0	27	0	0
T68	0	17	0	0
T71	0	5	0	0
T81	0	8	0	0
T107	505	0	0	0
T108	3053	0	0	0
T109	421	0	0	0
T110	522	0	0	0
T248	0	10	0	0
T259	0	25	0	0
T260	622	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7465398	0	0
T1	28754	28290	0	0
T2	127882	124057	0	0
T3	19948	16278	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	11182	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7467603	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	16284	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	11186	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1492	0	0
T2	127882	0	0	0
T3	19948	28	0	0
T4	1680	0	0	0
T6	17174	5	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	24	0	0
T34	0	15	0	0
T45	0	8	0	0
T46	0	24	0	0
T66	0	11	0	0
T67	0	27	0	0
T68	0	17	0	0
T69	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	1444	0	0
T2	127882	0	0	0
T3	19948	28	0	0
T4	1680	0	0	0
T6	17174	5	0	0
T7	11518	0	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T26	0	24	0	0
T34	0	15	0	0
T45	0	2	0	0
T46	0	24	0	0
T66	0	11	0	0
T67	0	27	0	0
T68	0	17	0	0
T69	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	753	0	0
T34	0	15	0	0
T45	11270	2	0	0
T46	16107	24	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T66	0	11	0	0
T67	0	27	0	0
T68	0	17	0	0
T71	0	5	0	0
T81	0	8	0	0
T107	505	0	0	0
T108	3053	0	0	0
T109	421	0	0	0
T110	522	0	0	0
T248	0	10	0	0
T259	0	25	0	0
T260	622	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	753	0	0
T34	0	15	0	0
T45	11270	2	0	0
T46	16107	24	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T66	0	11	0	0
T67	0	27	0	0
T68	0	17	0	0
T71	0	5	0	0
T81	0	8	0	0
T107	505	0	0	0
T108	3053	0	0	0
T109	421	0	0	0
T110	522	0	0	0
T248	0	10	0	0
T259	0	25	0	0
T260	622	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	73614	0	0
T34	0	1306	0	0
T45	11270	305	0	0
T46	16107	2296	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T66	0	1292	0	0
T67	0	2680	0	0
T68	0	92	0	0
T71	0	401	0	0
T81	0	474	0	0
T107	505	0	0	0
T108	3053	0	0	0
T109	421	0	0	0
T110	522	0	0	0
T248	0	932	0	0
T259	0	1700	0	0
T260	622	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	674	0	0
T34	0	12	0	0
T45	11270	2	0	0
T46	16107	22	0	0
T51	19953	0	0	0
T52	719	0	0	0
T62	494	0	0	0
T66	0	10	0	0
T67	0	24	0	0
T68	0	17	0	0
T71	0	5	0	0
T81	0	8	0	0
T107	505	0	0	0
T108	3053	0	0	0
T109	421	0	0	0
T110	522	0	0	0
T248	0	10	0	0
T259	0	25	0	0
T260	622	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T6,T3
1	Covered	T5,T1,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T3
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T1,T6	VC_COV_UNR
1	Covered	T1,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T1,T6
1	Covered	T1,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T9
1	0	Covered	T1,T6,T2
1	1	Covered	T1,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T89,T251,T170
1	0	Covered	T71,T59

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
1	0	Covered	T71,T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T9
1	-	Covered	T1,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T9
DetectSt	168	Covered	T1,T7,T9
IdleSt	163	Covered	T5,T1,T6
StableSt	191	Covered	T1,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T9
DebounceSt->IdleSt	163	Covered	T42,T252,T71
DetectSt->IdleSt	186	Covered	T71,T89,T251
DetectSt->StableSt	191	Covered	T1,T7,T9
IdleSt->DebounceSt	148	Covered	T1,T7,T9
StableSt->IdleSt	206	Covered	T1,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T9
0	1	Covered	T1,T7,T9
0	0	Excluded	T5,T1,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T9
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T71,T59
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T252,T250
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T71,T89,T251
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8663532	835	0	0
CntIncr_A	8663532	48363	0	0
CntNoWrap_A	8663532	7982438	0	0
DetectStDropOut_A	8663532	51	0	0
DetectedOut_A	8663532	13798	0	0
DetectedPulseOut_A	8663532	331	0	0
DisabledIdleSt_A	8663532	7630492	0	0
DisabledNoDetection_A	8663532	7632230	0	0
EnterDebounceSt_A	8663532	449	0	0
EnterDetectSt_A	8663532	388	0	0
EnterStableSt_A	8663532	331	0	0
PulseIsPulse_A	8663532	331	0	0
StayInStableSt	8663532	13436	0	0
gen_high_level_sva.HighLevelEvent_A	8663532	7985649	0	0
gen_not_sticky_sva.StableStDropOut_A	8663532	296	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	835	0	0
T1	28754	12	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	2	0	0
T9	0	14	0	0
T10	0	8	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	8	0	0
T34	0	4	0	0
T46	0	2	0	0
T50	0	2	0	0
T66	0	8	0	0
T106	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	48363	0	0
T1	28754	678	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	134	0	0
T9	0	609	0	0
T10	0	352	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	148	0	0
T34	0	160	0	0
T46	0	57	0	0
T50	0	137	0	0
T66	0	272	0	0
T106	0	136	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7982438	0	0
T1	28754	28278	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	51	0	0
T33	37430	0	0	0
T89	4806	9	0	0
T147	646	0	0	0
T170	0	1	0	0
T251	0	3	0	0
T254	13807	0	0	0
T261	0	11	0	0
T262	0	9	0	0
T263	0	5	0	0
T264	0	10	0	0
T265	0	3	0	0
T266	422	0	0	0
T267	522	0	0	0
T268	506	0	0	0
T269	404	0	0	0
T270	588	0	0	0
T271	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	13798	0	0
T1	28754	51	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	53	0	0
T9	0	36	0	0
T10	0	217	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	46	0	0
T34	0	141	0	0
T46	0	53	0	0
T50	0	16	0	0
T66	0	337	0	0
T106	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	331	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	1	0	0
T9	0	7	0	0
T10	0	4	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	4	0	0
T34	0	2	0	0
T46	0	1	0	0
T50	0	1	0	0
T66	0	4	0	0
T106	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7630492	0	0
T1	28754	24173	0	0
T2	127882	124057	0	0
T3	19948	19505	0	0
T4	1680	1279	0	0
T5	421	20	0	0
T6	17174	16752	0	0
T13	711	310	0	0
T14	426	25	0	0
T15	421	20	0	0
T16	223329	222928	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7632230	0	0
T1	28754	24173	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	449	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	1	0	0
T9	0	7	0	0
T10	0	4	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	4	0	0
T34	0	2	0	0
T46	0	1	0	0
T50	0	1	0	0
T66	0	4	0	0
T106	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	388	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	1	0	0
T9	0	7	0	0
T10	0	4	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	4	0	0
T34	0	2	0	0
T46	0	1	0	0
T50	0	1	0	0
T66	0	4	0	0
T106	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	331	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	1	0	0
T9	0	7	0	0
T10	0	4	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	4	0	0
T34	0	2	0	0
T46	0	1	0	0
T50	0	1	0	0
T66	0	4	0	0
T106	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	331	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	1	0	0
T9	0	7	0	0
T10	0	4	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	4	0	0
T34	0	2	0	0
T46	0	1	0	0
T50	0	1	0	0
T66	0	4	0	0
T106	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	13436	0	0
T1	28754	45	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	52	0	0
T9	0	29	0	0
T10	0	213	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	42	0	0
T34	0	137	0	0
T46	0	51	0	0
T50	0	15	0	0
T66	0	333	0	0
T106	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	7985649	0	0
T1	28754	28302	0	0
T2	127882	124066	0	0
T3	19948	19512	0	0
T4	1680	1280	0	0
T5	421	21	0	0
T6	17174	16757	0	0
T13	711	311	0	0
T14	426	26	0	0
T15	421	21	0	0
T16	223329	222929	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8663532	296	0	0
T1	28754	6	0	0
T2	127882	0	0	0
T3	19948	0	0	0
T4	1680	0	0	0
T6	17174	0	0	0
T7	0	1	0	0
T9	0	7	0	0
T10	0	4	0	0
T13	711	0	0	0
T14	426	0	0	0
T15	421	0	0	0
T16	223329	0	0	0
T17	1471	0	0	0
T32	0	4	0	0
T42	0	1	0	0
T50	0	1	0	0
T66	0	4	0	0
T106	0	1	0	0
T206	0	6	0	0