Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1245272608	9490	0	0
auto_block_debounce_ctl_rd_A	1245272608	1946	0	0
auto_block_out_ctl_rd_A	1245272608	3180	0	0
com_det_ctl_0_rd_A	1245272608	3445	0	0
com_det_ctl_1_rd_A	1245272608	3622	0	0
com_det_ctl_2_rd_A	1245272608	3694	0	0
com_det_ctl_3_rd_A	1245272608	3653	0	0
com_out_ctl_0_rd_A	1245272608	4192	0	0
com_out_ctl_1_rd_A	1245272608	4213	0	0
com_out_ctl_2_rd_A	1245272608	4436	0	0
com_out_ctl_3_rd_A	1245272608	4227	0	0
com_pre_det_ctl_0_rd_A	1245272608	1649	0	0
com_pre_det_ctl_1_rd_A	1245272608	1544	0	0
com_pre_det_ctl_2_rd_A	1245272608	1373	0	0
com_pre_det_ctl_3_rd_A	1245272608	1382	0	0
com_pre_sel_ctl_0_rd_A	1245272608	4532	0	0
com_pre_sel_ctl_1_rd_A	1245272608	4619	0	0
com_pre_sel_ctl_2_rd_A	1245272608	4728	0	0
com_pre_sel_ctl_3_rd_A	1245272608	4737	0	0
com_sel_ctl_0_rd_A	1245272608	4719	0	0
com_sel_ctl_1_rd_A	1245272608	4639	0	0
com_sel_ctl_2_rd_A	1245272608	4672	0	0
com_sel_ctl_3_rd_A	1245272608	4692	0	0
ec_rst_ctl_rd_A	1245272608	2423	0	0
intr_enable_rd_A	1245272608	2068	0	0
key_intr_ctl_rd_A	1245272608	5029	0	0
key_intr_debounce_ctl_rd_A	1245272608	1390	0	0
key_invert_ctl_rd_A	1245272608	7337	0	0
pin_allowed_ctl_rd_A	1245272608	8169	0	0
pin_out_ctl_rd_A	1245272608	5561	0	0
pin_out_value_rd_A	1245272608	5542	0	0
regwen_rd_A	1245272608	1500	0	0
ulp_ac_debounce_ctl_rd_A	1245272608	1724	0	0
ulp_ctl_rd_A	1245272608	1694	0	0
ulp_lid_debounce_ctl_rd_A	1245272608	1734	0	0
ulp_pwrb_debounce_ctl_rd_A	1245272608	1507	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	9490	0	0
T2	176965	6	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T37	0	13	0	0
T42	0	17	0	0
T48	0	10	0	0
T50	0	9	0	0
T53	67054	0	0	0
T108	0	7	0	0
T114	0	5	0	0
T146	0	23	0	0
T205	0	5	0	0
T289	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1946	0	0
T2	176965	15	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T13	355540	10	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	13	0	0
T47	0	14	0	0
T48	0	26	0	0
T50	0	16	0	0
T53	67054	0	0	0
T108	0	10	0	0
T289	0	11	0	0
T290	0	10	0	0
T291	0	6	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	3180	0	0
T2	176965	5	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T13	355540	11	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	7	0	0
T47	0	12	0	0
T48	0	25	0	0
T50	0	26	0	0
T53	67054	0	0	0
T108	0	14	0	0
T289	0	13	0	0
T290	0	6	0	0
T291	0	18	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	3445	0	0
T2	176965	6	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	73	0	0
T46	0	31	0	0
T48	0	28	0	0
T50	0	27	0	0
T53	67054	0	0	0
T66	0	72	0	0
T86	0	28	0	0
T108	0	15	0	0
T248	0	23	0	0
T289	0	10	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	3622	0	0
T2	176965	10	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	56	0	0
T46	0	30	0	0
T48	0	33	0	0
T50	0	18	0	0
T53	67054	0	0	0
T66	0	66	0	0
T86	0	26	0	0
T108	0	17	0	0
T248	0	53	0	0
T289	0	19	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	3694	0	0
T2	176965	12	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	60	0	0
T46	0	36	0	0
T48	0	44	0	0
T50	0	6	0	0
T53	67054	0	0	0
T66	0	79	0	0
T86	0	35	0	0
T108	0	10	0	0
T248	0	52	0	0
T289	0	11	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	3653	0	0
T2	176965	13	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	59	0	0
T46	0	19	0	0
T48	0	30	0	0
T50	0	11	0	0
T53	67054	0	0	0
T66	0	58	0	0
T86	0	33	0	0
T108	0	17	0	0
T248	0	24	0	0
T289	0	20	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4192	0	0
T2	176965	18	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	52	0	0
T46	0	11	0	0
T48	0	15	0	0
T50	0	18	0	0
T53	67054	0	0	0
T66	0	77	0	0
T86	0	19	0	0
T108	0	23	0	0
T248	0	41	0	0
T289	0	14	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4213	0	0
T2	176965	14	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	59	0	0
T46	0	36	0	0
T48	0	28	0	0
T50	0	15	0	0
T53	67054	0	0	0
T66	0	69	0	0
T86	0	22	0	0
T108	0	17	0	0
T248	0	19	0	0
T289	0	18	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4436	0	0
T2	176965	8	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	76	0	0
T46	0	36	0	0
T48	0	31	0	0
T50	0	20	0	0
T53	67054	0	0	0
T66	0	49	0	0
T86	0	24	0	0
T108	0	11	0	0
T248	0	34	0	0
T289	0	16	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4227	0	0
T2	176965	17	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	59	0	0
T46	0	32	0	0
T48	0	21	0	0
T50	0	19	0	0
T53	67054	0	0	0
T66	0	57	0	0
T86	0	9	0	0
T108	0	18	0	0
T248	0	27	0	0
T289	0	14	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1649	0	0
T2	176965	16	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	35	0	0
T50	0	18	0	0
T53	67054	0	0	0
T108	0	23	0	0
T114	0	4	0	0
T131	0	12	0	0
T145	0	37	0	0
T289	0	13	0	0
T292	0	19	0	0
T293	0	21	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1544	0	0
T2	176965	6	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	37	0	0
T50	0	17	0	0
T53	67054	0	0	0
T108	0	19	0	0
T114	0	5	0	0
T131	0	9	0	0
T145	0	26	0	0
T289	0	17	0	0
T292	0	21	0	0
T293	0	24	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1373	0	0
T2	176965	12	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	27	0	0
T50	0	24	0	0
T53	67054	0	0	0
T108	0	19	0	0
T114	0	6	0	0
T131	0	9	0	0
T145	0	30	0	0
T289	0	9	0	0
T292	0	9	0	0
T293	0	13	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1382	0	0
T2	176965	12	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	23	0	0
T50	0	25	0	0
T53	67054	0	0	0
T108	0	17	0	0
T114	0	5	0	0
T131	0	19	0	0
T145	0	34	0	0
T289	0	6	0	0
T292	0	18	0	0
T293	0	15	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4532	0	0
T2	176965	9	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	57	0	0
T46	0	30	0	0
T48	0	21	0	0
T50	0	14	0	0
T53	67054	0	0	0
T66	0	53	0	0
T86	0	32	0	0
T108	0	19	0	0
T248	0	20	0	0
T289	0	15	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4619	0	0
T2	176965	17	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	33	0	0
T46	0	25	0	0
T48	0	28	0	0
T50	0	21	0	0
T53	67054	0	0	0
T66	0	74	0	0
T86	0	23	0	0
T108	0	15	0	0
T248	0	56	0	0
T289	0	2	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4728	0	0
T2	176965	12	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	56	0	0
T46	0	53	0	0
T48	0	21	0	0
T50	0	27	0	0
T53	67054	0	0	0
T66	0	51	0	0
T86	0	18	0	0
T108	0	18	0	0
T248	0	35	0	0
T289	0	18	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4737	0	0
T2	176965	3	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	60	0	0
T46	0	17	0	0
T48	0	32	0	0
T50	0	20	0	0
T53	67054	0	0	0
T66	0	47	0	0
T86	0	37	0	0
T108	0	20	0	0
T248	0	28	0	0
T289	0	21	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4719	0	0
T2	176965	9	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	61	0	0
T46	0	27	0	0
T48	0	23	0	0
T50	0	9	0	0
T53	67054	0	0	0
T66	0	78	0	0
T86	0	31	0	0
T108	0	15	0	0
T248	0	25	0	0
T289	0	17	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4639	0	0
T2	176965	14	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	44	0	0
T46	0	11	0	0
T48	0	26	0	0
T50	0	12	0	0
T53	67054	0	0	0
T66	0	57	0	0
T86	0	23	0	0
T108	0	20	0	0
T248	0	37	0	0
T289	0	15	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4672	0	0
T2	176965	7	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	79	0	0
T46	0	27	0	0
T48	0	18	0	0
T50	0	28	0	0
T53	67054	0	0	0
T66	0	53	0	0
T86	0	34	0	0
T108	0	17	0	0
T248	0	31	0	0
T289	0	19	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	4692	0	0
T2	176965	8	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	63	0	0
T46	0	29	0	0
T48	0	15	0	0
T50	0	19	0	0
T53	67054	0	0	0
T66	0	70	0	0
T86	0	26	0	0
T108	0	24	0	0
T248	0	28	0	0
T289	0	28	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	2423	0	0
T2	176965	19	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T34	0	14	0	0
T46	0	5	0	0
T48	0	59	0	0
T50	0	30	0	0
T53	67054	0	0	0
T66	0	10	0	0
T84	0	9	0	0
T108	0	29	0	0
T248	0	15	0	0
T294	0	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	2068	0	0
T2	176965	13	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T43	0	10	0	0
T48	0	30	0	0
T50	0	12	0	0
T53	67054	0	0	0
T108	0	2	0	0
T114	0	28	0	0
T131	0	20	0	0
T145	0	35	0	0
T289	0	25	0	0
T292	0	22	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	5029	0	0
T2	176965	10	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T24	0	4	0	0
T48	0	41	0	0
T50	0	9	0	0
T53	67054	0	0	0
T108	0	16	0	0
T114	0	1	0	0
T166	0	4	0	0
T201	0	2	0	0
T210	0	3	0	0
T289	0	15	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1390	0	0
T2	176965	15	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	22	0	0
T50	0	21	0	0
T53	67054	0	0	0
T108	0	19	0	0
T114	0	8	0	0
T131	0	25	0	0
T145	0	38	0	0
T289	0	10	0	0
T292	0	13	0	0
T293	0	17	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	7337	0	0
T2	176965	77	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T21	0	59	0	0
T48	0	201	0	0
T50	0	12	0	0
T53	67054	0	0	0
T56	0	46	0	0
T58	0	67	0	0
T62	0	35	0	0
T108	0	19	0	0
T207	0	70	0	0
T295	0	35	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	8169	0	0
T2	176965	9	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	105	0	0
T50	0	24	0	0
T53	67054	0	0	0
T57	0	40	0	0
T65	0	72	0	0
T108	0	33	0	0
T114	0	76	0	0
T289	0	23	0	0
T296	0	74	0	0
T297	0	49	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	5561	0	0
T2	176965	15	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	79	0	0
T50	0	13	0	0
T53	67054	0	0	0
T57	0	59	0	0
T65	0	51	0	0
T108	0	23	0	0
T114	0	45	0	0
T289	0	13	0	0
T296	0	83	0	0
T297	0	11	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	5542	0	0
T2	176965	6	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	99	0	0
T50	0	14	0	0
T53	67054	0	0	0
T57	0	33	0	0
T65	0	63	0	0
T108	0	7	0	0
T114	0	72	0	0
T289	0	17	0	0
T296	0	74	0	0
T297	0	44	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1500	0	0
T2	176965	5	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	0	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	29	0	0
T50	0	15	0	0
T53	67054	0	0	0
T108	0	14	0	0
T114	0	9	0	0
T131	0	13	0	0
T145	0	32	0	0
T289	0	17	0	0
T292	0	11	0	0
T293	0	25	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1724	0	0
T2	176965	10	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	4	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	41	0	0
T50	0	28	0	0
T53	67054	0	0	0
T60	0	8	0	0
T76	0	8	0	0
T108	0	25	0	0
T114	0	15	0	0
T289	0	6	0	0
T298	0	1	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1694	0	0
T2	176965	14	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	2	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	32	0	0
T50	0	21	0	0
T53	67054	0	0	0
T60	0	14	0	0
T108	0	25	0	0
T114	0	18	0	0
T289	0	17	0	0
T298	0	1	0	0
T299	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1734	0	0
T2	176965	10	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	8	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	14	0	0
T50	0	23	0	0
T53	67054	0	0	0
T60	0	15	0	0
T108	0	11	0	0
T114	0	29	0	0
T289	0	21	0	0
T298	0	2	0	0
T299	0	9	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1245272608	1507	0	0
T2	176965	11	0	0
T3	498715	0	0	0
T4	115890	0	0	0
T7	143974	0	0	0
T8	55893	5	0	0
T14	36259	0	0	0
T15	210782	0	0	0
T16	267993	0	0	0
T17	176548	0	0	0
T48	0	23	0	0
T50	0	27	0	0
T53	67054	0	0	0
T60	0	8	0	0
T76	0	11	0	0
T108	0	12	0	0
T114	0	12	0	0
T128	0	2	0	0
T289	0	12	0	0