Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T2,T4,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T2,T4,T8
1	1	Covered	T1,T6,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	217574	0	0
SrcPulseCheck_M	2147483647	220114	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	217574
T1	2149433	192
T2	7011481	4
T3	11929249	119
T4	2704110	0
T6	3786888	85
T7	1554920	48
T9	0	128
T10	0	46
T11	170832	4
T12	71642	0
T13	8193773	14
T14	843755	0
T15	4857669	0
T16	11300406	0
T17	4094437	16
T24	33749	0
T25	0	16
T26	0	104
T34	0	6
T45	0	13
T46	0	52
T47	0	16
T48	0	20
T49	0	16
T50	141964	36
T51	0	14
T52	0	14
T53	135224	0
T54	238286	0
T55	121007	0
T56	238095	0
T57	65948	0
T58	216321	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	220114
T1	2149433	192
T2	7011481	4
T3	11929249	119
T4	2704110	0
T6	3786888	85
T7	1554920	48
T9	0	128
T10	0	46
T11	1622	4
T12	597	0
T13	8193773	14
T14	843755	0
T15	4857669	0
T16	11300406	0
T17	4094437	16
T24	901	0
T25	0	16
T26	0	104
T34	0	6
T45	0	13
T46	0	52
T47	0	16
T48	0	20
T49	0	16
T50	11510	36
T51	0	14
T52	0	14
T53	135224	0
T54	490	0
T55	503	0
T56	490	0
T57	507	0
T58	491	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T18,T19,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T18,T19,T20
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1696	0	0
SrcPulseCheck_M	1245272608	1772	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1696
T1	28754	12
T2	127882	2
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	1
T17	1471	0
T48	0	3
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1772
T1	136587	12
T2	176965	2
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	1
T17	176548	0
T48	0	3
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T18,T19,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T18,T19,T20
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1759	0	0
SrcPulseCheck_M	8903055	1759	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1759
T1	136587	12
T2	176965	2
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	1
T17	176548	0
T48	0	3
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1759
T1	28754	12
T2	127882	2
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	1
T17	1471	0
T48	0	3
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T4,T8,T60

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T4,T8,T60
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	869	0	0
SrcPulseCheck_M	1245272608	940	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	869
T2	127882	1
T3	19948	0
T4	1680	3
T7	11518	0
T8	1282	2
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	558	0
T60	0	3
T61	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	940
T2	176965	1
T3	498715	0
T4	115890	3
T7	143974	0
T8	55893	2
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	67054	0
T60	0	3
T61	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T4,T8,T60

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T4,T8,T60
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	926	0	0
SrcPulseCheck_M	8903055	926	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	926
T2	176965	1
T3	498715	0
T4	115890	3
T7	143974	0
T8	55893	2
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	67054	0
T60	0	3
T61	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	926
T2	127882	1
T3	19948	0
T4	1680	3
T7	11518	0
T8	1282	2
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	558	0
T60	0	3
T61	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T4,T8,T60

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T4,T8,T60
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	852	0	0
SrcPulseCheck_M	1245272608	924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	852
T2	127882	1
T3	19948	0
T4	1680	3
T7	11518	0
T8	1282	2
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	558	0
T60	0	3
T61	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	924
T2	176965	1
T3	498715	0
T4	115890	3
T7	143974	0
T8	55893	2
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	67054	0
T60	0	3
T61	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T4,T8,T60

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T4,T8,T60
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	911	0	0
SrcPulseCheck_M	8903055	911	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	911
T2	176965	1
T3	498715	0
T4	115890	3
T7	143974	0
T8	55893	2
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	67054	0
T60	0	3
T61	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	911
T2	127882	1
T3	19948	0
T4	1680	3
T7	11518	0
T8	1282	2
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	558	0
T60	0	3
T61	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T4,T8,T60

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T4,T8,T60
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	849	0	0
SrcPulseCheck_M	1245272608	921	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	849
T2	127882	1
T3	19948	0
T4	1680	3
T7	11518	0
T8	1282	2
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	558	0
T60	0	3
T61	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	921
T2	176965	1
T3	498715	0
T4	115890	3
T7	143974	0
T8	55893	2
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	67054	0
T60	0	3
T61	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T4,T8,T60

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T4,T8,T60
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	907	0	0
SrcPulseCheck_M	8903055	907	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	907
T2	176965	1
T3	498715	0
T4	115890	3
T7	143974	0
T8	55893	2
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	67054	0
T60	0	3
T61	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	907
T2	127882	1
T3	19948	0
T4	1680	3
T7	11518	0
T8	1282	2
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T23	0	1
T42	0	1
T48	0	1
T50	0	2
T53	558	0
T60	0	3
T61	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T2,T4,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	857	0	0
SrcPulseCheck_M	1245272608	935	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	857
T2	127882	2
T3	19948	0
T4	1680	2
T7	11518	0
T8	1282	2
T10	0	2
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T50	0	2
T53	558	0
T60	0	2
T61	0	2
T70	0	2
T71	0	4
T72	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	935
T2	176965	2
T3	498715	0
T4	115890	2
T7	143974	0
T8	55893	2
T10	0	2
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T50	0	2
T53	67054	0
T60	0	2
T61	0	2
T70	0	2
T71	0	4
T72	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T2,T4,T8

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T4,T8
1	0	Covered	T2,T4,T8
1	1	Covered	T2,T4,T8

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	923	0	0
SrcPulseCheck_M	8903055	923	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	923
T2	176965	2
T3	498715	0
T4	115890	2
T7	143974	0
T8	55893	2
T10	0	2
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T50	0	2
T53	67054	0
T60	0	2
T61	0	2
T70	0	2
T71	0	4
T72	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	923
T2	127882	2
T3	19948	0
T4	1680	2
T7	11518	0
T8	1282	2
T10	0	2
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T50	0	2
T53	558	0
T60	0	2
T61	0	2
T70	0	2
T71	0	4
T72	0	2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T10,T66

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T10,T66
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1083	0	0
SrcPulseCheck_M	1245272608	1156	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1083
T1	28754	6
T2	127882	1
T3	19948	6
T4	1680	1
T6	17174	0
T7	0	3
T8	0	1
T9	0	7
T10	0	6
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T50	0	1
T60	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1156
T1	136587	6
T2	176965	1
T3	498715	6
T4	115890	1
T6	163154	0
T7	0	3
T8	0	1
T9	0	7
T10	0	6
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T50	0	1
T60	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T10
1	0	Covered	T2,T21,T10
1	1	Covered	T2,T21,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T10
1	0	Covered	T2,T21,T10
1	1	Covered	T2,T21,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	2961	0	0
SrcPulseCheck_M	1245272608	3033	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	2961
T2	127882	20
T3	19948	0
T4	1680	0
T7	11518	0
T8	1282	0
T10	0	20
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T21	0	20
T37	0	40
T48	0	60
T53	558	0
T54	0	20
T56	0	20
T58	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	3033
T2	176965	20
T3	498715	0
T4	115890	0
T7	143974	0
T8	55893	0
T10	0	20
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T21	0	20
T37	0	40
T48	0	60
T53	67054	0
T54	0	20
T56	0	20
T58	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T10
1	0	Covered	T2,T21,T10
1	1	Covered	T2,T21,T10

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T10
1	0	Covered	T2,T21,T10
1	1	Covered	T2,T21,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	3021	0	0
SrcPulseCheck_M	8903055	3021	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	3021
T2	176965	20
T3	498715	0
T4	115890	0
T7	143974	0
T8	55893	0
T10	0	20
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T21	0	20
T37	0	40
T48	0	60
T53	67054	0
T54	0	20
T56	0	20
T58	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	3021
T2	127882	20
T3	19948	0
T4	1680	0
T7	11518	0
T8	1282	0
T10	0	20
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T21	0	20
T37	0	40
T48	0	60
T53	558	0
T54	0	20
T56	0	20
T58	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T22
1	0	Covered	T2,T21,T22
1	1	Covered	T2,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T22
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	6554	0	0
SrcPulseCheck_M	1245272608	6632	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	6554
T2	127882	41
T3	19948	0
T4	1680	0
T7	11518	0
T8	1282	0
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T21	0	1
T22	0	20
T23	0	20
T48	0	83
T53	558	0
T54	0	1
T55	0	20
T56	0	1
T57	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	6632
T2	176965	41
T3	498715	0
T4	115890	0
T7	143974	0
T8	55893	0
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T21	0	1
T22	0	20
T23	0	20
T48	0	83
T53	67054	0
T54	0	1
T55	0	20
T56	0	1
T57	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T22
1	0	Covered	T2,T21,T22
1	1	Covered	T2,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T21,T22
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	6616	0	0
SrcPulseCheck_M	8903055	6616	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	6616
T2	176965	41
T3	498715	0
T4	115890	0
T7	143974	0
T8	55893	0
T10	0	1
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T21	0	1
T22	0	20
T23	0	20
T48	0	83
T53	67054	0
T54	0	1
T55	0	20
T56	0	1
T57	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	6616
T2	127882	41
T3	19948	0
T4	1680	0
T7	11518	0
T8	1282	0
T10	0	1
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T21	0	1
T22	0	20
T23	0	20
T48	0	83
T53	558	0
T54	0	1
T55	0	20
T56	0	1
T57	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T2,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T2,T22,T23
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	7618	0	0
SrcPulseCheck_M	1245272608	7690	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	7618
T1	28754	12
T2	127882	43
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T13	711	0
T14	426	0
T15	421	0
T16	223329	1
T17	1471	0
T21	0	1
T22	0	20
T23	0	20
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	7690
T1	136587	12
T2	176965	43
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	1
T17	176548	0
T21	0	1
T22	0	20
T23	0	20
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T2,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T2,T22,T23
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	7678	0	0
SrcPulseCheck_M	8903055	7678	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	7678
T1	136587	12
T2	176965	43
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	1
T17	176548	0
T21	0	1
T22	0	20
T23	0	20
T53	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	7678
T1	28754	12
T2	127882	43
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T13	711	0
T14	426	0
T15	421	0
T16	223329	1
T17	1471	0
T21	0	1
T22	0	20
T23	0	20
T53	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T22,T23
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T22,T23
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	6425	0	0
SrcPulseCheck_M	1245272608	6503	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	6425
T2	127882	40
T3	19948	0
T4	1680	0
T7	11518	0
T8	1282	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T22	0	20
T23	0	20
T37	0	20
T48	0	80
T50	0	40
T53	558	0
T55	0	20
T57	0	20
T64	0	20
T65	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	6503
T2	176965	40
T3	498715	0
T4	115890	0
T7	143974	0
T8	55893	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T22	0	20
T23	0	20
T37	0	20
T48	0	80
T50	0	40
T53	67054	0
T55	0	20
T57	0	20
T64	0	20
T65	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T22,T23
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T22,T23

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T2,T22,T23
1	0	Covered	T2,T22,T23
1	1	Covered	T2,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	6489	0	0
SrcPulseCheck_M	8903055	6489	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	6489
T2	176965	40
T3	498715	0
T4	115890	0
T7	143974	0
T8	55893	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T22	0	20
T23	0	20
T37	0	20
T48	0	80
T50	0	40
T53	67054	0
T55	0	20
T57	0	20
T64	0	20
T65	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	6489
T2	127882	40
T3	19948	0
T4	1680	0
T7	11518	0
T8	1282	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T22	0	20
T23	0	20
T37	0	20
T48	0	80
T50	0	40
T53	558	0
T55	0	20
T57	0	20
T64	0	20
T65	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T11,T12,T24
1	0	Covered	T11,T12,T24
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T11,T12,T24
1	0	Covered	T71,T59,T18
1	1	Covered	T11,T12,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	823	0	0
SrcPulseCheck_M	1245272608	899	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	823
T11	1622	1
T12	597	1
T24	901	1
T35	0	1
T37	4791	1
T38	0	1
T40	0	1
T41	0	1
T42	0	2
T43	0	1
T50	11510	0
T54	490	0
T55	503	0
T56	490	0
T57	507	0
T58	491	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	899
T11	170832	1
T12	71642	1
T24	33749	1
T35	0	1
T37	237218	1
T38	0	1
T40	0	1
T41	0	1
T42	0	2
T43	0	1
T50	141964	0
T54	238286	0
T55	121007	0
T56	238095	0
T57	65948	0
T58	216321	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T11,T12,T24
1	0	Covered	T11,T12,T24
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T11,T12,T24
1	0	Covered	T71,T59,T18
1	1	Covered	T11,T12,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	887	0	0
SrcPulseCheck_M	8903055	887	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	887
T11	170832	1
T12	71642	1
T24	33749	1
T35	0	1
T37	237218	1
T38	0	1
T40	0	1
T41	0	1
T42	0	2
T43	0	1
T50	141964	0
T54	238286	0
T55	121007	0
T56	238095	0
T57	65948	0
T58	216321	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	887
T11	1622	1
T12	597	1
T24	901	1
T35	0	1
T37	4791	1
T38	0	1
T40	0	1
T41	0	1
T42	0	2
T43	0	1
T50	11510	0
T54	490	0
T55	503	0
T56	490	0
T57	507	0
T58	491	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1723	0	0
SrcPulseCheck_M	1245272608	1799	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1723
T1	28754	12
T2	127882	1
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T11	0	2
T12	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1799
T1	136587	12
T2	176965	1
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T11	0	2
T12	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1788	0	0
SrcPulseCheck_M	8903055	1788	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1788
T1	136587	12
T2	176965	1
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T11	0	2
T12	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1788
T1	28754	12
T2	127882	1
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T11	0	2
T12	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1225	0	0
SrcPulseCheck_M	1245272608	1297	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1225
T2	127882	0
T3	19948	0
T4	1680	0
T7	11518	0
T10	0	4
T13	711	4
T14	426	0
T15	421	0
T16	223329	0
T17	1471	5
T25	0	5
T47	0	5
T48	0	5
T49	0	5
T50	0	6
T51	0	4
T52	0	4
T53	558	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1297
T2	176965	0
T3	498715	0
T4	115890	0
T7	143974	0
T10	0	4
T13	355540	4
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	5
T25	0	5
T47	0	5
T48	0	5
T49	0	5
T50	0	6
T51	0	4
T52	0	4
T53	67054	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1285	0	0
SrcPulseCheck_M	8903055	1285	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1285
T2	176965	0
T3	498715	0
T4	115890	0
T7	143974	0
T10	0	4
T13	355540	4
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	5
T25	0	5
T47	0	5
T48	0	5
T49	0	5
T50	0	6
T51	0	4
T52	0	4
T53	67054	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1285
T2	127882	0
T3	19948	0
T4	1680	0
T7	11518	0
T10	0	4
T13	711	4
T14	426	0
T15	421	0
T16	223329	0
T17	1471	5
T25	0	5
T47	0	5
T48	0	5
T49	0	5
T50	0	6
T51	0	4
T52	0	4
T53	558	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1048	0	0
SrcPulseCheck_M	1245272608	1123	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1048
T2	127882	0
T3	19948	0
T4	1680	0
T7	11518	0
T10	0	3
T13	711	3
T14	426	0
T15	421	0
T16	223329	0
T17	1471	3
T25	0	3
T47	0	3
T48	0	3
T49	0	3
T50	0	4
T51	0	3
T52	0	3
T53	558	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1123
T2	176965	0
T3	498715	0
T4	115890	0
T7	143974	0
T10	0	3
T13	355540	3
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	3
T25	0	3
T47	0	3
T48	0	3
T49	0	3
T50	0	4
T51	0	3
T52	0	3
T53	67054	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T13,T17,T25
1	0	Covered	T13,T17,T25
1	1	Covered	T13,T17,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1109	0	0
SrcPulseCheck_M	8903055	1109	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1109
T2	176965	0
T3	498715	0
T4	115890	0
T7	143974	0
T10	0	3
T13	355540	3
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	3
T25	0	3
T47	0	3
T48	0	3
T49	0	3
T50	0	4
T51	0	3
T52	0	3
T53	67054	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1109
T2	127882	0
T3	19948	0
T4	1680	0
T7	11518	0
T10	0	3
T13	711	3
T14	426	0
T15	421	0
T16	223329	0
T17	1471	3
T25	0	3
T47	0	3
T48	0	3
T49	0	3
T50	0	4
T51	0	3
T52	0	3
T53	558	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	6848	0	0
SrcPulseCheck_M	1245272608	6920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	6848
T2	127882	0
T3	19948	71
T4	1680	0
T6	17174	55
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	73
T31	0	1
T34	0	78
T45	0	51
T46	0	88
T66	0	68
T67	0	88
T68	0	67

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	6920
T2	176965	0
T3	498715	71
T4	115890	0
T6	163154	55
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	73
T31	0	1
T34	0	78
T45	0	51
T46	0	88
T66	0	68
T67	0	88
T68	0	67

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	6907	0	0
SrcPulseCheck_M	8903055	6907	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	6907
T2	176965	0
T3	498715	71
T4	115890	0
T6	163154	55
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	73
T31	0	1
T34	0	78
T45	0	51
T46	0	88
T66	0	68
T67	0	88
T68	0	67

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	6907
T2	127882	0
T3	19948	71
T4	1680	0
T6	17174	55
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	73
T31	0	1
T34	0	78
T45	0	51
T46	0	88
T66	0	68
T67	0	88
T68	0	67

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	6996	0	0
SrcPulseCheck_M	1245272608	7074	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	6996
T2	127882	0
T3	19948	57
T4	1680	0
T6	17174	61
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T34	0	76
T45	0	51
T46	0	84
T66	0	79
T67	0	88
T68	0	76
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	7074
T2	176965	0
T3	498715	57
T4	115890	0
T6	163154	61
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T34	0	76
T45	0	51
T46	0	84
T66	0	79
T67	0	88
T68	0	76
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	7061	0	0
SrcPulseCheck_M	8903055	7061	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	7061
T2	176965	0
T3	498715	57
T4	115890	0
T6	163154	61
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T34	0	76
T45	0	51
T46	0	84
T66	0	79
T67	0	88
T68	0	76
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	7061
T2	127882	0
T3	19948	57
T4	1680	0
T6	17174	61
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T34	0	76
T45	0	51
T46	0	84
T66	0	79
T67	0	88
T68	0	76
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	6750	0	0
SrcPulseCheck_M	1245272608	6825	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	6750
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	60
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	71
T34	0	75
T45	0	51
T46	0	72
T66	0	62
T67	0	72
T68	0	93
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	6825
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	60
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	71
T34	0	75
T45	0	51
T46	0	72
T66	0	62
T67	0	72
T68	0	93
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	6814	0	0
SrcPulseCheck_M	8903055	6814	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	6814
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	60
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	71
T34	0	75
T45	0	51
T46	0	72
T66	0	62
T67	0	72
T68	0	93
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	6814
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	60
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	71
T34	0	75
T45	0	51
T46	0	72
T66	0	62
T67	0	72
T68	0	93
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	6930	0	0
SrcPulseCheck_M	1245272608	7006	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	6930
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	63
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T34	0	76
T45	0	51
T46	0	72
T66	0	73
T67	0	61
T68	0	76
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	7006
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	63
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T34	0	76
T45	0	51
T46	0	72
T66	0	73
T67	0	61
T68	0	76
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	6992	0	0
SrcPulseCheck_M	8903055	6992	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	6992
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	63
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T34	0	76
T45	0	51
T46	0	72
T66	0	73
T67	0	61
T68	0	76
T69	0	51

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	6992
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	63
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T34	0	76
T45	0	51
T46	0	72
T66	0	73
T67	0	61
T68	0	76
T69	0	51

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1016	0	0
SrcPulseCheck_M	1245272608	1095	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1016
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T31	0	1
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1095
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T31	0	1
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1081	0	0
SrcPulseCheck_M	8903055	1081	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1081
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T31	0	1
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1081
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T31	0	1
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	960	0	0
SrcPulseCheck_M	1245272608	1034	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	960
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1034
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1022	0	0
SrcPulseCheck_M	8903055	1022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1022
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1022
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	950	0	0
SrcPulseCheck_M	1245272608	1023	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	950
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1023
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1009	0	0
SrcPulseCheck_M	8903055	1009	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1009
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1009
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	981	0	0
SrcPulseCheck_M	1245272608	1058	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	981
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1058
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T6,T3,T26
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T6,T3,T26
1	0	Covered	T71,T59,T18
1	1	Covered	T6,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1045	0	0
SrcPulseCheck_M	8903055	1045	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1045
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	143974	0
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1045
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	11518	0
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T34	0	6
T45	0	1
T46	0	4
T66	0	4
T67	0	4
T68	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	7452	0	0
SrcPulseCheck_M	1245272608	7526	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	7452
T1	28754	12
T2	127882	1
T3	19948	71
T4	1680	0
T6	17174	55
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	7526
T1	136587	12
T2	176965	1
T3	498715	71
T4	115890	0
T6	163154	55
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	7514	0	0
SrcPulseCheck_M	8903055	7514	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	7514
T1	136587	12
T2	176965	1
T3	498715	71
T4	115890	0
T6	163154	55
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	7514
T1	28754	12
T2	127882	1
T3	19948	71
T4	1680	0
T6	17174	55
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	7521	0	0
SrcPulseCheck_M	1245272608	7599	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	7521
T1	28754	12
T2	127882	0
T3	19948	57
T4	1680	0
T6	17174	61
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T45	0	51
T46	0	84
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	7599
T1	136587	12
T2	176965	0
T3	498715	57
T4	115890	0
T6	163154	61
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T45	0	51
T46	0	84
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	7584	0	0
SrcPulseCheck_M	8903055	7584	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	7584
T1	136587	12
T2	176965	0
T3	498715	57
T4	115890	0
T6	163154	61
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T45	0	51
T46	0	84
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	7584
T1	28754	12
T2	127882	0
T3	19948	57
T4	1680	0
T6	17174	61
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T45	0	51
T46	0	84
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	7290	0	0
SrcPulseCheck_M	1245272608	7369	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	7290
T1	28754	12
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	60
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	71
T45	0	51
T46	0	72
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	7369
T1	136587	12
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	60
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	71
T45	0	51
T46	0	72
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	7359	0	0
SrcPulseCheck_M	8903055	7359	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	7359
T1	136587	12
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	60
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	71
T45	0	51
T46	0	72
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	7359
T1	28754	12
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	60
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	71
T45	0	51
T46	0	72
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	7472	0	0
SrcPulseCheck_M	1245272608	7545	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	7472
T1	28754	12
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	63
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T45	0	51
T46	0	72
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	7545
T1	136587	12
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	63
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T45	0	51
T46	0	72
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T6,T3,T26

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T6,T3,T26
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	7532	0	0
SrcPulseCheck_M	8903055	7532	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	7532
T1	136587	12
T2	176965	0
T3	498715	79
T4	115890	0
T6	163154	63
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	95
T45	0	51
T46	0	72
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	7532
T1	28754	12
T2	127882	0
T3	19948	79
T4	1680	0
T6	17174	63
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	95
T45	0	51
T46	0	72
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1628	0	0
SrcPulseCheck_M	1245272608	1701	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1628
T1	28754	12
T2	127882	1
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1701
T1	136587	12
T2	176965	1
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1686	0	0
SrcPulseCheck_M	8903055	1686	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1686
T1	136587	12
T2	176965	1
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1686
T1	28754	12
T2	127882	1
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1534	0	0
SrcPulseCheck_M	1245272608	1607	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1534
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1607
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1594	0	0
SrcPulseCheck_M	8903055	1594	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1594
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1594
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1551	0	0
SrcPulseCheck_M	1245272608	1626	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1551
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1626
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1612	0	0
SrcPulseCheck_M	8903055	1612	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1612
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1612
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1557	0	0
SrcPulseCheck_M	1245272608	1630	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1557
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1630
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1618	0	0
SrcPulseCheck_M	8903055	1618	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1618
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1618
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1633	0	0
SrcPulseCheck_M	1245272608	1711	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1633
T1	28754	12
T2	127882	1
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1711
T1	136587	12
T2	176965	1
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T1,T6,T2
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T2
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T2

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1697	0	0
SrcPulseCheck_M	8903055	1697	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1697
T1	136587	12
T2	176965	1
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T48	0	1
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1697
T1	28754	12
T2	127882	1
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T11	0	1
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T48	0	1
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1552	0	0
SrcPulseCheck_M	1245272608	1623	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1552
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1623
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1610	0	0
SrcPulseCheck_M	8903055	1610	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1610
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1610
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1548	0	0
SrcPulseCheck_M	1245272608	1623	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1548
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1623
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1609	0	0
SrcPulseCheck_M	8903055	1609	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1609
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1609
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	8903055	1558	0	0
SrcPulseCheck_M	1245272608	1631	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	8903055	1558
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1245272608	1631
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T1,T6,T3
1	1	Covered	T71,T59,T18

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T1,T6
0	1	Covered	T1,T6,T3
1	0	Covered	T71,T59,T18
1	1	Covered	T1,T6,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T1,T6
0	Covered	T5,T1,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1245272608	1619	0	0
SrcPulseCheck_M	8903055	1619	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1245272608	1619
T1	136587	12
T2	176965	0
T3	498715	7
T4	115890	0
T6	163154	5
T7	0	3
T9	0	8
T10	0	2
T13	355540	0
T14	36259	0
T15	210782	0
T16	267993	0
T17	176548	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	8903055	1619
T1	28754	12
T2	127882	0
T3	19948	7
T4	1680	0
T6	17174	5
T7	0	3
T9	0	8
T10	0	2
T13	711	0
T14	426	0
T15	421	0
T16	223329	0
T17	1471	0
T26	0	8
T45	0	1
T46	0	4
T50	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc