Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T2 |
10 |
|
T15 |
13 |
|
T17 |
9 |
| auto[1] |
799 |
1 |
|
|
T2 |
10 |
|
T15 |
7 |
|
T17 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T2 |
13 |
|
T15 |
10 |
|
T17 |
10 |
| auto[1] |
845 |
1 |
|
|
T2 |
7 |
|
T15 |
10 |
|
T17 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
797 |
1 |
|
|
T2 |
12 |
|
T15 |
6 |
|
T17 |
10 |
| auto[1] |
843 |
1 |
|
|
T2 |
8 |
|
T15 |
14 |
|
T17 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T2 |
11 |
|
T15 |
11 |
|
T17 |
13 |
| auto[1] |
789 |
1 |
|
|
T2 |
9 |
|
T15 |
9 |
|
T17 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
835 |
1 |
|
|
T2 |
11 |
|
T15 |
12 |
|
T17 |
9 |
| auto[1] |
805 |
1 |
|
|
T2 |
9 |
|
T15 |
8 |
|
T17 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T2 |
11 |
|
T15 |
8 |
|
T17 |
11 |
| auto[1] |
800 |
1 |
|
|
T2 |
9 |
|
T15 |
12 |
|
T17 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
802 |
1 |
|
|
T2 |
9 |
|
T15 |
11 |
|
T17 |
8 |
| auto[1] |
838 |
1 |
|
|
T2 |
11 |
|
T15 |
9 |
|
T17 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
768 |
1 |
|
|
T2 |
13 |
|
T15 |
6 |
|
T17 |
6 |
| auto[1] |
872 |
1 |
|
|
T2 |
7 |
|
T15 |
14 |
|
T17 |
14 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T2 |
11 |
|
T15 |
12 |
|
T17 |
13 |
| auto[1] |
804 |
1 |
|
|
T2 |
9 |
|
T15 |
8 |
|
T17 |
7 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T2 |
7 |
|
T15 |
12 |
|
T17 |
10 |
| auto[1] |
820 |
1 |
|
|
T2 |
13 |
|
T15 |
8 |
|
T17 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T2 |
15 |
|
T15 |
8 |
|
T17 |
8 |
| auto[1] |
792 |
1 |
|
|
T2 |
5 |
|
T15 |
12 |
|
T17 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T2 |
10 |
|
T15 |
14 |
|
T17 |
13 |
| auto[1] |
809 |
1 |
|
|
T2 |
10 |
|
T15 |
6 |
|
T17 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T2 |
12 |
|
T15 |
10 |
|
T17 |
12 |
| auto[1] |
809 |
1 |
|
|
T2 |
8 |
|
T15 |
10 |
|
T17 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T2 |
13 |
|
T15 |
10 |
|
T17 |
10 |
| auto[1] |
845 |
1 |
|
|
T2 |
7 |
|
T15 |
10 |
|
T17 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T2 |
10 |
|
T15 |
11 |
|
T17 |
7 |
| auto[1] |
790 |
1 |
|
|
T2 |
10 |
|
T15 |
9 |
|
T17 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
824 |
1 |
|
|
T2 |
11 |
|
T15 |
8 |
|
T17 |
6 |
| auto[1] |
816 |
1 |
|
|
T2 |
9 |
|
T15 |
12 |
|
T17 |
14 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T2 |
8 |
|
T15 |
11 |
|
T17 |
9 |
| auto[1] |
804 |
1 |
|
|
T2 |
12 |
|
T15 |
9 |
|
T17 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
809 |
1 |
|
|
T2 |
10 |
|
T15 |
11 |
|
T17 |
9 |
| auto[1] |
831 |
1 |
|
|
T2 |
10 |
|
T15 |
9 |
|
T17 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T2 |
8 |
|
T15 |
15 |
|
T17 |
14 |
| auto[1] |
799 |
1 |
|
|
T2 |
12 |
|
T15 |
5 |
|
T17 |
6 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
839 |
1 |
|
|
T2 |
8 |
|
T15 |
10 |
|
T17 |
10 |
| auto[1] |
801 |
1 |
|
|
T2 |
12 |
|
T15 |
10 |
|
T17 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
835 |
1 |
|
|
T2 |
11 |
|
T15 |
9 |
|
T17 |
10 |
| auto[1] |
805 |
1 |
|
|
T2 |
9 |
|
T15 |
11 |
|
T17 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
846 |
1 |
|
|
T2 |
14 |
|
T15 |
6 |
|
T17 |
12 |
| auto[1] |
794 |
1 |
|
|
T2 |
6 |
|
T15 |
14 |
|
T17 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T2 |
10 |
|
T15 |
12 |
|
T17 |
12 |
| auto[1] |
834 |
1 |
|
|
T2 |
10 |
|
T15 |
8 |
|
T17 |
8 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T2 |
10 |
|
T15 |
14 |
|
T17 |
13 |
| auto[1] |
809 |
1 |
|
|
T2 |
10 |
|
T15 |
6 |
|
T17 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
409 |
1 |
|
|
T2 |
7 |
|
T15 |
3 |
|
T17 |
3 |
| auto[0] |
auto[1] |
441 |
1 |
|
|
T2 |
3 |
|
T15 |
8 |
|
T17 |
4 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T2 |
5 |
|
T15 |
3 |
|
T17 |
7 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T2 |
5 |
|
T15 |
6 |
|
T17 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
423 |
1 |
|
|
T2 |
7 |
|
T15 |
4 |
|
T17 |
4 |
| auto[0] |
auto[1] |
401 |
1 |
|
|
T2 |
4 |
|
T15 |
4 |
|
T17 |
2 |
| auto[1] |
auto[0] |
428 |
1 |
|
|
T2 |
4 |
|
T15 |
7 |
|
T17 |
9 |
| auto[1] |
auto[1] |
388 |
1 |
|
|
T2 |
5 |
|
T15 |
5 |
|
T17 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
433 |
1 |
|
|
T2 |
6 |
|
T15 |
6 |
|
T17 |
4 |
| auto[0] |
auto[1] |
403 |
1 |
|
|
T2 |
2 |
|
T15 |
5 |
|
T17 |
5 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T2 |
5 |
|
T15 |
6 |
|
T17 |
5 |
| auto[1] |
auto[1] |
402 |
1 |
|
|
T2 |
7 |
|
T15 |
3 |
|
T17 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T2 |
7 |
|
T15 |
4 |
|
T17 |
5 |
| auto[0] |
auto[1] |
387 |
1 |
|
|
T2 |
3 |
|
T15 |
7 |
|
T17 |
4 |
| auto[1] |
auto[0] |
418 |
1 |
|
|
T2 |
4 |
|
T15 |
4 |
|
T17 |
6 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T2 |
6 |
|
T15 |
5 |
|
T17 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
413 |
1 |
|
|
T2 |
3 |
|
T15 |
6 |
|
T17 |
6 |
| auto[0] |
auto[1] |
428 |
1 |
|
|
T2 |
5 |
|
T15 |
9 |
|
T17 |
8 |
| auto[1] |
auto[0] |
389 |
1 |
|
|
T2 |
6 |
|
T15 |
5 |
|
T17 |
2 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T2 |
6 |
|
T17 |
4 |
|
T63 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
395 |
1 |
|
|
T2 |
5 |
|
T15 |
1 |
|
T17 |
3 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T2 |
3 |
|
T15 |
9 |
|
T17 |
7 |
| auto[1] |
auto[0] |
373 |
1 |
|
|
T2 |
8 |
|
T15 |
5 |
|
T17 |
3 |
| auto[1] |
auto[1] |
428 |
1 |
|
|
T2 |
4 |
|
T15 |
5 |
|
T17 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T2 |
6 |
|
T15 |
2 |
|
T17 |
7 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T2 |
8 |
|
T15 |
4 |
|
T17 |
5 |
| auto[1] |
auto[0] |
379 |
1 |
|
|
T2 |
1 |
|
T15 |
10 |
|
T17 |
3 |
| auto[1] |
auto[1] |
415 |
1 |
|
|
T2 |
5 |
|
T15 |
4 |
|
T17 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
435 |
1 |
|
|
T2 |
8 |
|
T15 |
3 |
|
T17 |
6 |
| auto[0] |
auto[1] |
371 |
1 |
|
|
T2 |
2 |
|
T15 |
9 |
|
T17 |
6 |
| auto[1] |
auto[0] |
413 |
1 |
|
|
T2 |
7 |
|
T15 |
5 |
|
T17 |
2 |
| auto[1] |
auto[1] |
421 |
1 |
|
|
T2 |
3 |
|
T15 |
3 |
|
T17 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
421 |
1 |
|
|
T2 |
4 |
|
T15 |
7 |
|
T17 |
5 |
| auto[0] |
auto[1] |
410 |
1 |
|
|
T2 |
8 |
|
T15 |
3 |
|
T17 |
7 |
| auto[1] |
auto[0] |
420 |
1 |
|
|
T2 |
6 |
|
T15 |
6 |
|
T17 |
4 |
| auto[1] |
auto[1] |
389 |
1 |
|
|
T2 |
2 |
|
T15 |
4 |
|
T17 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
795 |
1 |
|
|
T2 |
13 |
|
T15 |
10 |
|
T17 |
10 |
| auto[1] |
auto[1] |
845 |
1 |
|
|
T2 |
7 |
|
T15 |
10 |
|
T17 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T2 |
8 |
|
T15 |
6 |
|
T17 |
6 |
| auto[0] |
auto[1] |
416 |
1 |
|
|
T2 |
3 |
|
T15 |
3 |
|
T17 |
4 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T2 |
3 |
|
T15 |
6 |
|
T17 |
7 |
| auto[1] |
auto[1] |
388 |
1 |
|
|
T2 |
6 |
|
T15 |
5 |
|
T17 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
831 |
1 |
|
|
T2 |
10 |
|
T15 |
14 |
|
T17 |
13 |
| auto[1] |
auto[1] |
809 |
1 |
|
|
T2 |
10 |
|
T15 |
6 |
|
T17 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T2 |
10 |
|
T40 |
12 |
|
T331 |
10 |
| auto[1] |
150 |
1 |
|
|
T2 |
10 |
|
T40 |
8 |
|
T331 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T2 |
11 |
|
T40 |
11 |
|
T331 |
14 |
| auto[1] |
153 |
1 |
|
|
T2 |
9 |
|
T40 |
9 |
|
T331 |
6 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T2 |
12 |
|
T40 |
9 |
|
T331 |
11 |
| auto[1] |
154 |
1 |
|
|
T2 |
8 |
|
T40 |
11 |
|
T331 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T2 |
10 |
|
T40 |
8 |
|
T331 |
10 |
| auto[1] |
155 |
1 |
|
|
T2 |
10 |
|
T40 |
12 |
|
T331 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T2 |
12 |
|
T40 |
12 |
|
T331 |
8 |
| auto[1] |
143 |
1 |
|
|
T2 |
8 |
|
T40 |
8 |
|
T331 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T2 |
12 |
|
T40 |
9 |
|
T331 |
11 |
| auto[1] |
145 |
1 |
|
|
T2 |
8 |
|
T40 |
11 |
|
T331 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T2 |
11 |
|
T40 |
12 |
|
T331 |
10 |
| auto[1] |
156 |
1 |
|
|
T2 |
9 |
|
T40 |
8 |
|
T331 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T2 |
10 |
|
T40 |
12 |
|
T331 |
13 |
| auto[1] |
156 |
1 |
|
|
T2 |
10 |
|
T40 |
8 |
|
T331 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T2 |
10 |
|
T40 |
12 |
|
T331 |
11 |
| auto[1] |
150 |
1 |
|
|
T2 |
10 |
|
T40 |
8 |
|
T331 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
152 |
1 |
|
|
T2 |
12 |
|
T40 |
10 |
|
T331 |
12 |
| auto[1] |
148 |
1 |
|
|
T2 |
8 |
|
T40 |
10 |
|
T331 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T2 |
11 |
|
T40 |
13 |
|
T331 |
9 |
| auto[1] |
142 |
1 |
|
|
T2 |
9 |
|
T40 |
7 |
|
T331 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T2 |
10 |
|
T40 |
10 |
|
T331 |
10 |
| auto[1] |
151 |
1 |
|
|
T2 |
10 |
|
T40 |
10 |
|
T331 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T2 |
5 |
|
T40 |
9 |
|
T331 |
11 |
| auto[1] |
169 |
1 |
|
|
T2 |
15 |
|
T40 |
11 |
|
T331 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T2 |
11 |
|
T40 |
11 |
|
T331 |
14 |
| auto[1] |
153 |
1 |
|
|
T2 |
9 |
|
T40 |
9 |
|
T331 |
6 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T2 |
14 |
|
T40 |
8 |
|
T331 |
12 |
| auto[1] |
139 |
1 |
|
|
T2 |
6 |
|
T40 |
12 |
|
T331 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T2 |
12 |
|
T40 |
11 |
|
T331 |
9 |
| auto[1] |
152 |
1 |
|
|
T2 |
8 |
|
T40 |
9 |
|
T331 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T2 |
10 |
|
T40 |
8 |
|
T331 |
11 |
| auto[1] |
156 |
1 |
|
|
T2 |
10 |
|
T40 |
12 |
|
T331 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T2 |
8 |
|
T40 |
9 |
|
T331 |
6 |
| auto[1] |
150 |
1 |
|
|
T2 |
12 |
|
T40 |
11 |
|
T331 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T2 |
9 |
|
T40 |
9 |
|
T331 |
9 |
| auto[1] |
171 |
1 |
|
|
T2 |
11 |
|
T40 |
11 |
|
T331 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T2 |
12 |
|
T40 |
5 |
|
T331 |
14 |
| auto[1] |
157 |
1 |
|
|
T2 |
8 |
|
T40 |
15 |
|
T331 |
6 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T2 |
8 |
|
T40 |
10 |
|
T331 |
9 |
| auto[1] |
151 |
1 |
|
|
T2 |
12 |
|
T40 |
10 |
|
T331 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
155 |
1 |
|
|
T2 |
10 |
|
T40 |
12 |
|
T331 |
11 |
| auto[1] |
145 |
1 |
|
|
T2 |
10 |
|
T40 |
8 |
|
T331 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T2 |
13 |
|
T40 |
9 |
|
T331 |
8 |
| auto[1] |
147 |
1 |
|
|
T2 |
7 |
|
T40 |
11 |
|
T331 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T2 |
10 |
|
T40 |
10 |
|
T331 |
10 |
| auto[1] |
151 |
1 |
|
|
T2 |
10 |
|
T40 |
10 |
|
T331 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
80 |
1 |
|
|
T2 |
7 |
|
T40 |
3 |
|
T331 |
6 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T2 |
7 |
|
T40 |
5 |
|
T331 |
6 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T2 |
5 |
|
T40 |
6 |
|
T331 |
5 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T2 |
1 |
|
T40 |
6 |
|
T331 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
73 |
1 |
|
|
T2 |
5 |
|
T40 |
4 |
|
T331 |
4 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T2 |
7 |
|
T40 |
7 |
|
T331 |
5 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T2 |
5 |
|
T40 |
4 |
|
T331 |
6 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T2 |
3 |
|
T40 |
5 |
|
T331 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T2 |
6 |
|
T40 |
6 |
|
T331 |
4 |
| auto[0] |
auto[1] |
75 |
1 |
|
|
T2 |
4 |
|
T40 |
2 |
|
T331 |
7 |
| auto[1] |
auto[0] |
88 |
1 |
|
|
T2 |
6 |
|
T40 |
6 |
|
T331 |
4 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T2 |
4 |
|
T40 |
6 |
|
T331 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T2 |
5 |
|
T40 |
5 |
|
T331 |
3 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T2 |
3 |
|
T40 |
4 |
|
T331 |
3 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T2 |
7 |
|
T40 |
4 |
|
T331 |
8 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T2 |
5 |
|
T40 |
7 |
|
T331 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
52 |
1 |
|
|
T2 |
4 |
|
T40 |
5 |
|
T331 |
4 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T2 |
5 |
|
T40 |
4 |
|
T331 |
5 |
| auto[1] |
auto[0] |
92 |
1 |
|
|
T2 |
7 |
|
T40 |
7 |
|
T331 |
6 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T2 |
4 |
|
T40 |
4 |
|
T331 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T2 |
5 |
|
T40 |
3 |
|
T331 |
8 |
| auto[0] |
auto[1] |
84 |
1 |
|
|
T2 |
7 |
|
T40 |
2 |
|
T331 |
6 |
| auto[1] |
auto[0] |
85 |
1 |
|
|
T2 |
5 |
|
T40 |
9 |
|
T331 |
5 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T2 |
3 |
|
T40 |
6 |
|
T331 |
1 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T2 |
5 |
|
T40 |
6 |
|
T331 |
8 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T2 |
5 |
|
T40 |
6 |
|
T331 |
3 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T2 |
7 |
|
T40 |
4 |
|
T331 |
4 |
| auto[1] |
auto[1] |
67 |
1 |
|
|
T2 |
3 |
|
T40 |
4 |
|
T331 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T2 |
6 |
|
T40 |
6 |
|
T331 |
5 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T2 |
7 |
|
T40 |
3 |
|
T331 |
3 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T2 |
5 |
|
T40 |
7 |
|
T331 |
4 |
| auto[1] |
auto[1] |
65 |
1 |
|
|
T2 |
2 |
|
T40 |
4 |
|
T331 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T2 |
2 |
|
T40 |
6 |
|
T331 |
5 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T2 |
3 |
|
T40 |
3 |
|
T331 |
6 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T2 |
8 |
|
T40 |
6 |
|
T331 |
5 |
| auto[1] |
auto[1] |
86 |
1 |
|
|
T2 |
7 |
|
T40 |
5 |
|
T331 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
147 |
1 |
|
|
T2 |
11 |
|
T40 |
11 |
|
T331 |
14 |
| auto[1] |
auto[1] |
153 |
1 |
|
|
T2 |
9 |
|
T40 |
9 |
|
T331 |
6 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T2 |
4 |
|
T40 |
6 |
|
T331 |
6 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T2 |
4 |
|
T40 |
4 |
|
T331 |
3 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T2 |
6 |
|
T40 |
6 |
|
T331 |
5 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T2 |
6 |
|
T40 |
4 |
|
T331 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
149 |
1 |
|
|
T2 |
10 |
|
T40 |
10 |
|
T331 |
10 |
| auto[1] |
auto[1] |
151 |
1 |
|
|
T2 |
10 |
|
T40 |
10 |
|
T331 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T40 |
10 |
|
T189 |
9 |
|
T152 |
10 |
| auto[1] |
101 |
1 |
|
|
T40 |
10 |
|
T189 |
11 |
|
T152 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T40 |
9 |
|
T189 |
12 |
|
T152 |
11 |
| auto[1] |
109 |
1 |
|
|
T40 |
11 |
|
T189 |
8 |
|
T152 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
86 |
1 |
|
|
T40 |
6 |
|
T189 |
10 |
|
T152 |
10 |
| auto[1] |
134 |
1 |
|
|
T40 |
14 |
|
T189 |
10 |
|
T152 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T40 |
13 |
|
T189 |
11 |
|
T152 |
12 |
| auto[1] |
97 |
1 |
|
|
T40 |
7 |
|
T189 |
9 |
|
T152 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
114 |
1 |
|
|
T40 |
10 |
|
T189 |
8 |
|
T152 |
9 |
| auto[1] |
106 |
1 |
|
|
T40 |
10 |
|
T189 |
12 |
|
T152 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T40 |
9 |
|
T189 |
7 |
|
T152 |
11 |
| auto[1] |
109 |
1 |
|
|
T40 |
11 |
|
T189 |
13 |
|
T152 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T40 |
8 |
|
T189 |
9 |
|
T152 |
11 |
| auto[1] |
120 |
1 |
|
|
T40 |
12 |
|
T189 |
11 |
|
T152 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T40 |
12 |
|
T189 |
6 |
|
T152 |
10 |
| auto[1] |
110 |
1 |
|
|
T40 |
8 |
|
T189 |
14 |
|
T152 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T40 |
9 |
|
T189 |
9 |
|
T152 |
8 |
| auto[1] |
112 |
1 |
|
|
T40 |
11 |
|
T189 |
11 |
|
T152 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T40 |
10 |
|
T189 |
9 |
|
T152 |
13 |
| auto[1] |
108 |
1 |
|
|
T40 |
10 |
|
T189 |
11 |
|
T152 |
7 |