SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_key_intr_status_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 28 | 0 | 28 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_ac_present_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ac_present_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst_l_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_ec_rst_l_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_flash_wp_l_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_flash_wp_l_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key0_in_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key1_in_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_key2_in_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_h2l | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_pwrb_l2h | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 923 | 1 | T7 | 6 | T9 | 27 | T10 | 4 | ||||
auto[1] | 106 | 1 | T7 | 1 | T12 | 2 | T25 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 884 | 1 | T7 | 5 | T9 | 24 | T10 | 1 | ||||
auto[1] | 145 | 1 | T7 | 2 | T9 | 3 | T10 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 897 | 1 | T7 | 7 | T9 | 27 | T10 | 3 | ||||
auto[1] | 132 | 1 | T10 | 1 | T12 | 3 | T25 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 931 | 1 | T7 | 7 | T9 | 27 | T10 | 3 | ||||
auto[1] | 98 | 1 | T10 | 1 | T12 | 2 | T25 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 877 | 1 | T7 | 7 | T9 | 27 | T10 | 4 | ||||
auto[1] | 152 | 1 | T12 | 3 | T25 | 5 | T37 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 928 | 1 | T7 | 6 | T9 | 27 | T10 | 2 | ||||
auto[1] | 101 | 1 | T7 | 1 | T10 | 2 | T12 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 940 | 1 | T7 | 6 | T9 | 27 | T10 | 3 | ||||
auto[1] | 89 | 1 | T7 | 1 | T10 | 1 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 899 | 1 | T7 | 5 | T9 | 25 | T10 | 4 | ||||
auto[1] | 130 | 1 | T7 | 2 | T9 | 2 | T25 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 927 | 1 | T7 | 7 | T9 | 27 | T10 | 3 | ||||
auto[1] | 102 | 1 | T10 | 1 | T12 | 1 | T25 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 895 | 1 | T7 | 7 | T9 | 24 | T10 | 3 | ||||
auto[1] | 134 | 1 | T9 | 3 | T10 | 1 | T12 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 923 | 1 | T7 | 6 | T9 | 27 | T10 | 2 | ||||
auto[1] | 106 | 1 | T7 | 1 | T10 | 2 | T25 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 888 | 1 | T7 | 7 | T9 | 27 | T10 | 4 | ||||
auto[1] | 141 | 1 | T12 | 4 | T25 | 2 | T38 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 940 | 1 | T7 | 7 | T9 | 24 | T10 | 3 | ||||
auto[1] | 89 | 1 | T9 | 3 | T10 | 1 | T12 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 886 | 1 | T7 | 6 | T9 | 26 | T10 | 4 | ||||
auto[1] | 143 | 1 | T7 | 1 | T9 | 1 | T12 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |