Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2158

1

T1

7

T2

15

T3

8

auto[1]

663

1

T1

2

T2

4

T3

8

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2280

1

T1

3

T2

8

T3

10

auto[1]

541

1

T1

6

T2

11

T3

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2158

1

T2

15

T3

14

T7

2

auto[1]

663

1

T1

9

T2

4

T3

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2099

1

T1

6

T2

16

T3

14

auto[1]

722

1

T1

3

T2

3

T3

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2599

1

T1

9

T2

19

T3

16

auto[1]

222

1

T8

8

T27

3

T29

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2564

1

T1

9

T2

19

T3

16

auto[1]

257

1

T65

2

T66

13

T67

8

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2577

1

T1

9

T2

19

T3

16

auto[1]

244

1

T27

3

T29

18

T39

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2540

1

T1

9

T2

19

T3

16

auto[1]

281

1

T8

3

T27

3

T65

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2567

1

T1

9

T2

19

T3

16

auto[1]

254

1

T29

9

T39

3

T67

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2156

1

T1

6

T2

14

T3

6

auto[1]

665

1

T1

3

T2

5

T3

10

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	915	1			T1	9		T2	19		T3	16
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	57	1			T8	8		T65	1		T68	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	69	1			T29	9		T352	4		T353	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	26	1			T354	4		T355	13		T356	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	92	1			T8	3		T66	6		T67	20
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	20	1			T155	3		T334	7		T357	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	23	1			T67	5		T155	7		T353	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	8	1			T358	2		T207	3		T359	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	87	1			T29	14		T333	5		T340	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	20	1			T29	4		T66	5		T334	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	9	1			T338	4		T360	1		T361	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T39	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	29	1			T334	6		T362	2		T338	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T27	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	13	1			T155	4		T333	2		T363	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	1	1			T355	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	54	1			T66	8		T68	4		T92	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	27	1			T66	5		T68	3		T80	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	51	1			T88	7		T223	12		T91	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	11	1			T364	7		T365	4		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	22	1			T65	1		T224	3		T366	7
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T67	6		T367	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T355	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	45	1			T222	1		T357	2		T368	13
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	9	1			T334	2		T369	5		T370	2
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T155	1		T371	5		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

125

1

T29

7

T129

18

T46

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

141

1

T2

5

T3

8

T223

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

67

1

T245

2

T222

1

T224

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

169

1

T7

2

T45

9

T66

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

71

1

T43

8

T246

7

T68

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

60

1

T333

5

T157

8

T160

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T29

7

T143

4

T357

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

115

1

T29

9

T240

9

T66

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

79

1

T67

10

T68

5

T152

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T65

1

T240

4

T332

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T65

1

T129

4

T244

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

89

1

T13

6

T244

8

T246

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T2

3

T332

4

T91

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T1

3

T245

4

T179

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T3

2

T13

2

T156

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

100

1

T2

10

T27

3

T150

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

45

1

T3

6

T60

4

T334

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T66

6

T334

5

T226

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T43

2

T227

5

T93

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

54

1

T8

4

T13

5

T39

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T248

8

T249

3

T337

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T8

4

T29

4

T240

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T240

2

T150

4

T157

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T1

4

T45

7

T372

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T1

2

T2

1

T352

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

15

1

T8

3

T246

1

T190

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T143

1

T98

2

T373

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

15

1

T43

1

T34

1

T152

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T179

3

T336

1

T276

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T186

1

T374

2

T203

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T160

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded