Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1158

1

T4

10

T7

11

T9

19

auto[1]

1094

1

T4

10

T7

9

T9

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

533

1

T4

6

T7

6

T9

10

from_0to1

536

1

T4

6

T7

6

T9

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T4

11

T7

11

T9

18

auto[1]

1099

1

T4

9

T7

9

T9

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T4

10

T7

8

T9

19

auto[1]

1133

1

T4

10

T7

12

T9

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T7

1

T291

1

T134

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T4

1

T7

1

T24

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T4

1

T12

1

T291

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T4

1

T7

1

T9

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T7

2

T9

1

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T4

1

T7

1

T9

3

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T4

1

T9

3

T24

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T4

1

T7

1

T9

2

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T4

1

T7

1

T9

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T4

1

T7

1

T9

3

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T9

2

T12

1

T239

2

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T4

1

T7

1

T9

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T4

3

T7

1

T12

2

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T9

1

T12

1

T239

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T9

1

T12

1

T63

2

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T7

1

T12

1

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T4

12

T7

11

T9

21

auto[1]

1121

1

T4

8

T7

9

T9

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T4

4

T7

5

T9

10

from_0to1

556

1

T4

4

T7

5

T9

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1159

1

T4

10

T7

9

T9

22

auto[1]

1093

1

T4

10

T7

11

T9

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T4

9

T7

7

T9

17

auto[1]

1168

1

T4

11

T7

13

T9

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T9

1

T24

1

T12

2

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T4

1

T7

1

T9

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T4

1

T46

2

T291

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T4

1

T9

2

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T4

1

T7

2

T9

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T7

1

T9

3

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T4

1

T7

2

T9

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T4

1

T9

1

T24

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T7

1

T9

2

T12

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T4

1

T7

2

T9

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T12

1

T63

2

T239

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T7

1

T9

2

T24

2

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T4

1

T9

1

T12

1

auto[1]

from_0to1

auto[0]

auto[1]

85

1

T9

1

T12

2

T63

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T24

1

T12

1

T46

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T9

2

T12

1

T63

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T4

10

T7

12

T9

23

auto[1]

1127

1

T4

10

T7

8

T9

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T4

5

T7

5

T9

10

from_0to1

537

1

T4

5

T7

6

T9

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T4

12

T7

11

T9

18

auto[1]

1144

1

T4

8

T7

9

T9

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T4

9

T7

8

T9

16

auto[1]

1126

1

T4

11

T7

12

T9

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T4

1

T7

1

T9

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T4

1

T9

2

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T9

2

T24

1

T239

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T4

1

T7

1

T9

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T7

1

T9

2

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T4

1

T7

1

T9

2

auto[0]

from_0to1

auto[1]

auto[0]

81

1

T4

1

T7

2

T9

3

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T24

1

T12

1

T46

3

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T4

1

T24

1

T12

3

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T4

1

T7

2

T9

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T9

1

T24

2

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T7

1

T9

1

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T4

1

T9

1

T12

3

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T4

1

T7

1

T12

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T7

1

T24

1

T12

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T4

1

T9

3

T24

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1111

1

T4

13

T7

12

T9

18

auto[1]

1141

1

T4

7

T7

8

T9

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T4

7

T7

4

T9

8

from_0to1

522

1

T4

7

T7

5

T9

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T4

8

T7

11

T9

25

auto[1]

1095

1

T4

12

T7

9

T9

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T4

9

T7

10

T9

17

auto[1]

1139

1

T4

11

T7

10

T9

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T4

1

T9

1

T12

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T7

1

T9

1

T24

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T4

3

T7

1

T24

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T4

1

T9

1

T24

1

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T7

1

T9

2

T63

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T7

1

T9

1

T24

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T4

2

T7

1

T9

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T4

2

T24

1

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T7

1

T9

1

T12

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T4

2

T9

2

T12

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T7

1

T9

1

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T9

1

T24

1

T12

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T7

1

T9

1

T12

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T4

1

T9

2

T12

2

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T4

1

T12

3

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T4

1

T7

1

T24

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T4

14

T7

12

T9

18

auto[1]

1087

1

T4

6

T7

8

T9

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

532

1

T4

5

T7

3

T9

7

from_0to1

539

1

T4

5

T7

2

T9

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T4

10

T7

9

T9

14

auto[1]

1143

1

T4

10

T7

11

T9

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T4

8

T7

8

T9

18

auto[1]

1112

1

T4

12

T7

12

T9

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T63

1

T134

2

T384

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T4

2

T7

1

T24

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T9

1

T24

2

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T4

1

T7

1

T9

2

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T4

1

T24

1

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T4

1

T24

1

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T4

1

T239

1

T291

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T4

1

T9

2

T24

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T7

1

T9

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T9

2

T12

3

T385

2

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T4

1

T24

1

T12

2

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T4

1

T12

1

T386

2

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T9

1

T24

1

T12

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T12

2

T63

1

T291

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T4

1

T9

3

T24

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T7

2

T9

2

T12

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1159

1

T4

12

T7

12

T9

25

auto[1]

1093

1

T4

8

T7

8

T9

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T4

6

T7

6

T9

8

from_0to1

523

1

T4

7

T7

5

T9

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T4

10

T7

7

T9

16

auto[1]

1111

1

T4

10

T7

13

T9

24

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085

1

T4

8

T7

9

T9

22

auto[1]

1167

1

T4

12

T7

11

T9

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T9

1

T12

1

T63

2

auto[0]

from_1to0

auto[0]

auto[1]

63

1

T4

1

T24

1

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

51

1

T4

1

T7

1

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T4

2

T7

2

T9

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T4

1

T9

1

T24

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T4

2

T7

1

T9

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T7

1

T9

4

T24

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T7

2

T9

1

T24

1

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T9

3

T12

2

T63

3

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T63

1

T385

1

T384

1

auto[1]

from_1to0

auto[1]

auto[0]

82

1

T4

1

T7

1

T9

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T4

1

T7

2

T9

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T12

2

T63

1

T82

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T4

2

T63

1

T46

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T4

1

T7

1

T9

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T4

1

T46

1

T385

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T4

13

T7

8

T9

18

auto[1]

1173

1

T4

7

T7

12

T9

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T4

5

T7

5

T9

14

from_0to1

547

1

T4

5

T7

5

T9

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T4

14

T7

8

T9

15

auto[1]

1121

1

T4

6

T7

12

T9

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T4

12

T7

6

T9

20

auto[1]

1125

1

T4

8

T7

14

T9

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

86

1

T4

2

T9

1

T24

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T4

2

T7

3

T9

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T9

1

T12

1

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T7

1

T9

1

T24

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T4

1

T9

2

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T9

1

T12

2

T239

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T4

2

T7

2

T9

4

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T9

1

T24

2

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T9

1

T24

1

T12

4

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T9

2

T291

1

T386

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T4

1

T9

2

T24

2

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T7

1

T9

5

T12

2

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T24

2

T239

1

T134

3

auto[1]

from_0to1

auto[0]

auto[1]

80

1

T4

1

T7

2

T9

2

auto[1]

from_0to1

auto[1]

auto[0]

85

1

T7

1

T9

3

T12

2

auto[1]

from_0to1

auto[1]

auto[1]

88

1

T4

1

T9

2

T12

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T4

13

T7

9

T9

19

auto[1]

1140

1

T4

7

T7

11

T9

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T4

4

T7

7

T9

9

from_0to1

549

1

T4

4

T7

7

T9

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T4

7

T7

10

T9

14

auto[1]

1126

1

T4

13

T7

10

T9

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1148

1

T4

5

T7

9

T9

24

auto[1]

1104

1

T4

15

T7

11

T9

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T7

1

T9

1

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T9

1

T24

1

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T7

1

T9

2

T24

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T7

1

T12

1

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T4

1

T9

2

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T7

1

T239

1

T46

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T4

1

T7

1

T9

2

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T4

1

T7

2

T63

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T12

2

T63

2

T239

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T4

2

T7

1

T9

2

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T7

1

T9

2

T24

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T4

2

T7

2

T9

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T9

1

T12

1

T239

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T4

1

T7

1

T9

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T9

1

T24

1

T12

3

auto[1]

from_0to1

auto[1]

auto[1]

85

1

T7

2

T9

2

T24

1