Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156789	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119224

1

T4

51

T5

18

T1

251

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141010	1			T4	62		T5	2		T6	2
values[0x0]	66960	1			T4	37		T5	24		T17	2
values[0x1]	68043	1			T4	23		T5	37		T17	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127004	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149009

1

T4

65

T5

28

T17

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2209	1			T2	5		T3	2		T9	9
valid_sources[0x01]	991	1			T2	2		T3	3		T7	3
valid_sources[0x02]	1012	1			T6	2		T2	4		T3	3
valid_sources[0x03]	1437	1			T3	1		T7	1		T9	6
valid_sources[0x04]	904	1			T5	2		T2	1		T3	2
valid_sources[0x05]	930	1			T5	1		T2	1		T3	3
valid_sources[0x06]	2388	1			T2	3		T3	2		T7	2
valid_sources[0x07]	848	1			T2	4		T3	2		T7	3
valid_sources[0x08]	956	1			T2	1		T3	1		T7	2
valid_sources[0x09]	878	1			T2	2		T3	3		T7	4
valid_sources[0x0a]	710	1			T3	2		T7	5		T9	7
valid_sources[0x0b]	858	1			T2	2		T3	1		T7	1
valid_sources[0x0c]	962	1			T5	1		T3	1		T7	1
valid_sources[0x0d]	1157	1			T5	1		T2	2		T7	3
valid_sources[0x0e]	1083	1			T14	28		T2	4		T3	2
valid_sources[0x0f]	935	1			T2	11		T7	2		T9	2
valid_sources[0x10]	870	1			T3	3		T7	1		T9	1
valid_sources[0x11]	937	1			T2	3		T3	2		T9	3
valid_sources[0x12]	1009	1			T1	24		T2	1		T3	1
valid_sources[0x13]	973	1			T2	2		T3	4		T7	9
valid_sources[0x14]	1039	1			T3	2		T7	3		T9	2
valid_sources[0x15]	979	1			T2	3		T3	1		T7	8
valid_sources[0x16]	874	1			T2	6		T3	3		T7	1
valid_sources[0x17]	1020	1			T1	3		T3	3		T7	4
valid_sources[0x18]	896	1			T3	6		T7	2		T9	1
valid_sources[0x19]	981	1			T3	2		T7	3		T9	7
valid_sources[0x1a]	1102	1			T3	2		T7	4		T12	3
valid_sources[0x1b]	1108	1			T2	3		T3	1		T7	3
valid_sources[0x1c]	1284	1			T2	1		T3	4		T7	2
valid_sources[0x1d]	1415	1			T2	9		T7	1		T9	3
valid_sources[0x1e]	857	1			T2	3		T3	2		T9	2
valid_sources[0x1f]	872	1			T5	1		T2	1		T3	1
valid_sources[0x20]	1042	1			T3	2		T7	1		T9	5
valid_sources[0x21]	939	1			T2	5		T3	2		T7	2
valid_sources[0x22]	1183	1			T7	3		T9	1		T24	2
valid_sources[0x23]	870	1			T17	6		T7	3		T9	3
valid_sources[0x24]	1817	1			T5	1		T2	1		T3	3
valid_sources[0x25]	948	1			T2	1		T3	1		T7	2
valid_sources[0x26]	805	1			T5	2		T3	3		T7	3
valid_sources[0x27]	901	1			T5	3		T1	1		T2	5
valid_sources[0x28]	1322	1			T2	3		T3	2		T9	7
valid_sources[0x29]	745	1			T3	1		T9	1		T24	3
valid_sources[0x2a]	830	1			T2	10		T3	2		T7	1
valid_sources[0x2b]	948	1			T2	2		T3	2		T7	6
valid_sources[0x2c]	811	1			T2	1		T3	5		T7	2
valid_sources[0x2d]	1138	1			T14	17		T2	1		T9	4
valid_sources[0x2e]	924	1			T3	2		T7	4		T13	1
valid_sources[0x2f]	915	1			T2	3		T3	2		T7	4
valid_sources[0x30]	1065	1			T5	1		T1	1		T2	3
valid_sources[0x31]	1029	1			T3	1		T7	1		T9	3
valid_sources[0x32]	920	1			T3	3		T7	2		T9	1
valid_sources[0x33]	1087	1			T2	3		T3	3		T7	3
valid_sources[0x34]	861	1			T5	3		T3	2		T7	5
valid_sources[0x35]	996	1			T2	7		T7	2		T12	1
valid_sources[0x36]	1050	1			T2	2		T3	1		T7	1
valid_sources[0x37]	935	1			T5	1		T2	2		T3	3
valid_sources[0x38]	1094	1			T2	6		T3	3		T9	1
valid_sources[0x39]	781	1			T2	1		T3	1		T7	2
valid_sources[0x3a]	1405	1			T1	1		T2	7		T3	2
valid_sources[0x3b]	1238	1			T5	1		T1	22		T3	2
valid_sources[0x3c]	880	1			T5	1		T2	2		T3	3
valid_sources[0x3d]	913	1			T2	9		T3	5		T7	1
valid_sources[0x3e]	1153	1			T1	30		T3	1		T7	1
valid_sources[0x3f]	913	1			T2	1		T9	3		T24	1
valid_sources[0x40]	954	1			T2	2		T3	3		T7	3
valid_sources[0x41]	851	1			T2	7		T3	3		T7	1
valid_sources[0x42]	815	1			T3	2		T7	2		T9	7
valid_sources[0x43]	1008	1			T2	9		T3	1		T7	3
valid_sources[0x44]	893	1			T3	2		T7	2		T9	10
valid_sources[0x45]	838	1			T1	2		T3	2		T7	1
valid_sources[0x46]	886	1			T7	1		T9	7		T12	2
valid_sources[0x47]	1624	1			T3	3		T7	2		T9	4
valid_sources[0x48]	1446	1			T5	1		T2	3		T3	4
valid_sources[0x49]	1188	1			T3	2		T7	2		T51	1
valid_sources[0x4a]	892	1			T3	2		T7	3		T13	1
valid_sources[0x4b]	898	1			T2	4		T7	1		T9	1
valid_sources[0x4c]	1081	1			T3	4		T7	6		T9	7
valid_sources[0x4d]	1061	1			T5	1		T1	2		T2	3
valid_sources[0x4e]	857	1			T2	1		T3	3		T7	1
valid_sources[0x4f]	848	1			T3	2		T7	2		T9	6
valid_sources[0x50]	1176	1			T3	4		T7	4		T12	6
valid_sources[0x51]	1384	1			T2	1		T3	2		T7	1
valid_sources[0x52]	1007	1			T1	2		T3	2		T7	3
valid_sources[0x53]	1671	1			T5	1		T2	3		T3	3
valid_sources[0x54]	989	1			T3	5		T7	4		T12	2
valid_sources[0x55]	1307	1			T5	1		T2	1		T3	1
valid_sources[0x56]	1123	1			T3	2		T9	1		T24	1
valid_sources[0x57]	915	1			T2	9		T3	4		T7	4
valid_sources[0x58]	1252	1			T2	5		T3	4		T7	2
valid_sources[0x59]	1001	1			T2	3		T3	3		T7	1
valid_sources[0x5a]	1024	1			T2	7		T3	3		T7	1
valid_sources[0x5b]	1248	1			T4	122		T2	4		T3	1
valid_sources[0x5c]	1466	1			T3	2		T7	1		T12	3
valid_sources[0x5d]	768	1			T2	11		T3	2		T7	1
valid_sources[0x5e]	925	1			T3	3		T7	1		T9	1
valid_sources[0x5f]	1121	1			T5	1		T2	2		T3	2
valid_sources[0x60]	831	1			T1	18		T2	4		T3	1
valid_sources[0x61]	857	1			T2	3		T7	6		T10	1
valid_sources[0x62]	1038	1			T2	2		T7	3		T9	2
valid_sources[0x63]	925	1			T1	1		T3	1		T7	1
valid_sources[0x64]	994	1			T3	4		T9	8		T24	3
valid_sources[0x65]	1026	1			T5	1		T1	21		T2	5
valid_sources[0x66]	772	1			T2	3		T3	2		T7	3
valid_sources[0x67]	1050	1			T1	3		T3	1		T9	2
valid_sources[0x68]	845	1			T2	1		T3	3		T7	2
valid_sources[0x69]	1277	1			T5	1		T3	3		T7	4
valid_sources[0x6a]	906	1			T2	1		T3	2		T9	5
valid_sources[0x6b]	832	1			T2	2		T3	3		T7	1
valid_sources[0x6c]	922	1			T24	2		T12	1		T40	1
valid_sources[0x6d]	1902	1			T3	3		T7	2		T9	1
valid_sources[0x6e]	904	1			T5	1		T3	2		T7	1
valid_sources[0x6f]	973	1			T2	2		T3	1		T7	1
valid_sources[0x70]	1052	1			T2	4		T3	3		T7	1
valid_sources[0x71]	1984	1			T5	1		T3	2		T9	12
valid_sources[0x72]	927	1			T2	13		T7	4		T9	7
valid_sources[0x73]	968	1			T3	4		T7	1		T9	15
valid_sources[0x74]	1060	1			T3	3		T7	2		T24	1
valid_sources[0x75]	948	1			T1	13		T3	1		T7	5
valid_sources[0x76]	993	1			T5	2		T1	2		T2	8
valid_sources[0x77]	870	1			T3	5		T7	3		T9	3
valid_sources[0x78]	1017	1			T2	1		T3	2		T7	3
valid_sources[0x79]	924	1			T5	2		T3	4		T7	3
valid_sources[0x7a]	929	1			T2	1		T3	8		T7	5
valid_sources[0x7b]	946	1			T2	1		T3	2		T7	1
valid_sources[0x7c]	1484	1			T5	1		T3	2		T7	5
valid_sources[0x7d]	879	1			T2	3		T7	3		T9	2
valid_sources[0x7e]	931	1			T1	6		T3	5		T7	4
valid_sources[0x7f]	865	1			T2	4		T3	2		T7	1
valid_sources[0x80]	946	1			T2	3		T3	5		T7	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63352

1

T4

33

T5

1

T1

207

values[0x0]

all_enables

biggest_size

32636

1

T4

13

T5

8

T1

26

values[0x1]

all_enables

biggest_size

23236

1

T4

5

T5

9

T1

18