Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T26,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T26,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T26,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T24
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T26,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T26,T24
0	1	Covered	T95,T96,T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T26,T24
0	1	Covered	T7,T26,T24
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T26,T24
1	-	Covered	T7,T26,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T26,T24
DetectSt	168	Covered	T7,T26,T24
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T26,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T26,T24
DebounceSt->IdleSt	163	Covered	T41,T46,T85
DetectSt->IdleSt	186	Covered	T95,T96,T102
DetectSt->StableSt	191	Covered	T7,T26,T24
IdleSt->DebounceSt	148	Covered	T7,T26,T24
StableSt->IdleSt	206	Covered	T7,T26,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T26,T24
0	1	Covered	T7,T26,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T26,T24
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T26,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T26,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T86,T117
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T26,T24
DetectSt	-	-	-	-	1	-	-	Covered	T95,T96,T102
DetectSt	-	-	-	-	0	1	-	Covered	T7,T26,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T26,T24
StableSt	-	-	-	-	-	-	0	Covered	T7,T26,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	254	0	0
CntIncr_A	5638357	177357	0	0
CntNoWrap_A	5638357	5001790	0	0
DetectStDropOut_A	5638357	3	0	0
DetectedOut_A	5638357	781	0	0
DetectedPulseOut_A	5638357	112	0	0
DisabledIdleSt_A	5638357	4818584	0	0
DisabledNoDetection_A	5638357	4820888	0	0
EnterDebounceSt_A	5638357	144	0	0
EnterDetectSt_A	5638357	115	0	0
EnterStableSt_A	5638357	112	0	0
PulseIsPulse_A	5638357	112	0	0
StayInStableSt	5638357	669	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5638357	6768	0	0
gen_low_level_sva.LowLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	112	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	254	0	0
T7	9756	2	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	2	0	0
T26	682	4	0	0
T40	0	2	0	0
T41	0	2	0	0
T44	0	6	0	0
T46	0	4	0	0
T47	0	2	0	0
T49	0	4	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	177357	0	0
T7	9756	50	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	49	0	0
T26	682	77	0	0
T40	0	45	0	0
T41	0	148	0	0
T44	0	50978	0	0
T46	0	185	0	0
T47	0	68	0	0
T49	0	146	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001790	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4512	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	3	0	0
T95	694	1	0	0
T96	21224	1	0	0
T97	19832	0	0	0
T102	0	1	0	0
T107	919	0	0	0
T108	435	0	0	0
T109	504	0	0	0
T110	523	0	0	0
T111	447	0	0	0
T112	85136	0	0	0
T113	602	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	781	0	0
T7	9756	6	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	8	0	0
T26	682	20	0	0
T40	0	4	0	0
T41	0	5	0	0
T44	0	18	0	0
T46	0	11	0	0
T47	0	8	0	0
T49	0	11	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	112	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	1	0	0
T26	682	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4818584	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4414	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4820888	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4429	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	144	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	1	0	0
T26	682	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T44	0	3	0	0
T46	0	3	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	115	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	1	0	0
T26	682	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	112	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	1	0	0
T26	682	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	112	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	1	0	0
T26	682	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	669	0	0
T7	9756	5	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	7	0	0
T26	682	18	0	0
T40	0	3	0	0
T41	0	4	0	0
T44	0	15	0	0
T46	0	9	0	0
T47	0	7	0	0
T49	0	9	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	17	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	6768	0	0
T1	14725	11	0	0
T2	17278	7	0	0
T3	18805	8	0	0
T4	502	6	0	0
T5	521	5	0	0
T6	422	3	0	0
T7	9756	31	0	0
T8	14317	22	0	0
T14	454	4	0	0
T15	0	7	0	0
T17	611	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	112	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T24	0	1	0	0
T26	682	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T87	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Covered	T11,T72,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Unreachable
1	0	Covered	T7,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T11
DetectSt	168	Covered	T7,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T11
DebounceSt->IdleSt	163	Covered	T81,T82,T94
DetectSt->IdleSt	186	Covered	T11,T72,T81
DetectSt->StableSt	191	Covered	T7,T9,T11
IdleSt->DebounceSt	148	Covered	T7,T9,T11
StableSt->IdleSt	206	Covered	T7,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T11
0	1	Covered	T7,T9,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T81,T82,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T11,T72,T81
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	162	0	0
CntIncr_A	5638357	58834	0	0
CntNoWrap_A	5638357	5001882	0	0
DetectStDropOut_A	5638357	17	0	0
DetectedOut_A	5638357	9923	0	0
DetectedPulseOut_A	5638357	47	0	0
DisabledIdleSt_A	5638357	4493299	0	0
DisabledNoDetection_A	5638357	4495647	0	0
EnterDebounceSt_A	5638357	100	0	0
EnterDetectSt_A	5638357	64	0	0
EnterStableSt_A	5638357	47	0	0
PulseIsPulse_A	5638357	47	0	0
StayInStableSt	5638357	9876	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5638357	6768	0	0
gen_low_level_sva.LowLevelEvent_A	5638357	5004394	0	0
gen_sticky_sva.StableStDropOut_A	5638357	263740	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	162	0	0
T7	9756	2	0	0
T8	14317	0	0	0
T9	8766	2	0	0
T10	626	0	0	0
T11	0	6	0	0
T12	0	4	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	2	0	0
T46	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	2	0	0
T57	0	4	0	0
T72	0	4	0	0
T73	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	58834	0	0
T7	9756	48	0	0
T8	14317	0	0	0
T9	8766	92	0	0
T10	626	0	0	0
T11	0	141	0	0
T12	0	106	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	71	0	0
T46	0	10	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	85	0	0
T57	0	42	0	0
T72	0	102	0	0
T73	0	114	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001882	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4512	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	17	0	0
T11	1317	2	0	0
T12	10728	0	0	0
T13	21096	0	0	0
T27	12059	0	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T72	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T100	0	1	0	0
T104	526	0	0	0
T105	431	0	0	0
T118	0	2	0	0
T119	0	5	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	9923	0	0
T7	9756	224	0	0
T8	14317	0	0	0
T9	8766	243	0	0
T10	626	0	0	0
T11	0	99	0	0
T12	0	301	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	83	0	0
T46	0	75	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	408	0	0
T57	0	98	0	0
T72	0	156	0	0
T73	0	611	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	47	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4493299	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4119	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4495647	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4134	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	100	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	64	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	47	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	47	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	9876	0	0
T7	9756	223	0	0
T8	14317	0	0	0
T9	8766	242	0	0
T10	626	0	0	0
T11	0	98	0	0
T12	0	299	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	82	0	0
T46	0	74	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	407	0	0
T57	0	96	0	0
T72	0	155	0	0
T73	0	609	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	6768	0	0
T1	14725	11	0	0
T2	17278	7	0	0
T3	18805	8	0	0
T4	502	6	0	0
T5	521	5	0	0
T6	422	3	0	0
T7	9756	31	0	0
T8	14317	22	0	0
T14	454	4	0	0
T15	0	7	0	0
T17	611	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	263740	0	0
T7	9756	97	0	0
T8	14317	0	0	0
T9	8766	50	0	0
T10	626	0	0	0
T11	0	282	0	0
T12	0	462	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	147358	0	0
T46	0	707	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	448	0	0
T57	0	472	0	0
T72	0	430	0	0
T73	0	261	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T14
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Covered	T42,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T12
0	1	Unreachable
1	0	Covered	T9,T11,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T11
DetectSt	168	Covered	T9,T11,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T12
DebounceSt->IdleSt	163	Covered	T7,T9,T12
DetectSt->IdleSt	186	Covered	T42,T83,T84
DetectSt->StableSt	191	Covered	T9,T11,T12
IdleSt->DebounceSt	148	Covered	T7,T9,T11
StableSt->IdleSt	206	Covered	T9,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T11
0	1	Covered	T7,T9,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T9,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T42,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	162	0	0
CntIncr_A	5638357	9921	0	0
CntNoWrap_A	5638357	5001882	0	0
DetectStDropOut_A	5638357	10	0	0
DetectedOut_A	5638357	36060	0	0
DetectedPulseOut_A	5638357	45	0	0
DisabledIdleSt_A	5638357	4493299	0	0
DisabledNoDetection_A	5638357	4495647	0	0
EnterDebounceSt_A	5638357	109	0	0
EnterDetectSt_A	5638357	55	0	0
EnterStableSt_A	5638357	45	0	0
PulseIsPulse_A	5638357	45	0	0
StayInStableSt	5638357	36015	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_sticky_sva.StableStDropOut_A	5638357	275867	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	162	0	0
T7	9756	4	0	0
T8	14317	0	0	0
T9	8766	3	0	0
T10	626	0	0	0
T11	0	2	0	0
T12	0	4	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	4	0	0
T46	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	5	0	0
T57	0	4	0	0
T72	0	5	0	0
T73	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	9921	0	0
T7	9756	64	0	0
T8	14317	0	0	0
T9	8766	134	0	0
T10	626	0	0	0
T11	0	77	0	0
T12	0	270	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	64	0	0
T46	0	78	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	465	0	0
T57	0	140	0	0
T72	0	415	0	0
T73	0	144	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001882	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4510	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	10	0	0
T28	461	0	0	0
T42	149782	2	0	0
T43	25544	0	0	0
T44	51522	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T83	0	3	0	0
T84	0	4	0	0
T106	523	0	0	0
T114	493	0	0	0
T122	0	1	0	0
T123	404	0	0	0
T124	615	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	36060	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	536	0	0
T12	10728	301	0	0
T23	495	0	0	0
T24	2609	0	0	0
T26	682	0	0	0
T46	0	554	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T57	0	385	0	0
T73	0	709	0	0
T81	0	41	0	0
T82	0	185	0	0
T115	0	314	0	0
T116	0	862	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	45	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	1	0	0
T12	10728	1	0	0
T23	495	0	0	0
T24	2609	0	0	0
T26	682	0	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T57	0	2	0	0
T73	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T115	0	1	0	0
T116	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4493299	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4119	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4495647	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4134	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	109	0	0
T7	9756	4	0	0
T8	14317	0	0	0
T9	8766	2	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	3	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	2	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	5	0	0
T57	0	2	0	0
T72	0	5	0	0
T73	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	55	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	1	0	0
T12	10728	1	0	0
T23	495	0	0	0
T24	2609	0	0	0
T26	682	0	0	0
T42	0	2	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T57	0	2	0	0
T73	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	45	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	1	0	0
T12	10728	1	0	0
T23	495	0	0	0
T24	2609	0	0	0
T26	682	0	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T57	0	2	0	0
T73	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T115	0	1	0	0
T116	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	45	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	1	0	0
T12	10728	1	0	0
T23	495	0	0	0
T24	2609	0	0	0
T26	682	0	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T57	0	2	0	0
T73	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T115	0	1	0	0
T116	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	36015	0	0
T11	1317	535	0	0
T12	10728	300	0	0
T13	21096	0	0	0
T27	12059	0	0	0
T40	652	0	0	0
T41	6388	0	0	0
T46	0	553	0	0
T53	522	0	0	0
T57	0	383	0	0
T63	504	0	0	0
T73	0	707	0	0
T81	0	40	0	0
T82	0	184	0	0
T104	526	0	0	0
T105	431	0	0	0
T115	0	313	0	0
T116	0	860	0	0
T125	0	5	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	275867	0	0
T9	8766	129	0	0
T10	626	0	0	0
T11	1317	102	0	0
T12	10728	189	0	0
T23	495	0	0	0
T24	2609	0	0	0
T26	682	0	0	0
T46	0	165	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T57	0	90	0	0
T73	0	142	0	0
T81	0	150	0	0
T82	0	53675	0	0
T115	0	397	0	0
T116	0	199	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Covered	T57,T73,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T11
0	1	Unreachable
1	0	Covered	T7,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T11
DetectSt	168	Covered	T7,T9,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T11
DebounceSt->IdleSt	163	Covered	T46,T81,T82
DetectSt->IdleSt	186	Covered	T57,T73,T81
DetectSt->StableSt	191	Covered	T7,T9,T11
IdleSt->DebounceSt	148	Covered	T7,T9,T11
StableSt->IdleSt	206	Covered	T7,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T11
0	1	Covered	T7,T9,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T81,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T57,T73,T81
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	167	0	0
CntIncr_A	5638357	205760	0	0
CntNoWrap_A	5638357	5001877	0	0
DetectStDropOut_A	5638357	9	0	0
DetectedOut_A	5638357	204483	0	0
DetectedPulseOut_A	5638357	49	0	0
DisabledIdleSt_A	5638357	4493299	0	0
DisabledNoDetection_A	5638357	4495647	0	0
EnterDebounceSt_A	5638357	111	0	0
EnterDetectSt_A	5638357	58	0	0
EnterStableSt_A	5638357	49	0	0
PulseIsPulse_A	5638357	49	0	0
StayInStableSt	5638357	204434	0	0
gen_high_event_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_sticky_sva.StableStDropOut_A	5638357	8260	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	167	0	0
T7	9756	2	0	0
T8	14317	0	0	0
T9	8766	2	0	0
T10	626	0	0	0
T11	0	2	0	0
T12	0	4	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	2	0	0
T46	0	5	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	2	0	0
T57	0	6	0	0
T72	0	4	0	0
T73	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	205760	0	0
T7	9756	38	0	0
T8	14317	0	0	0
T9	8766	11	0	0
T10	626	0	0	0
T11	0	48	0	0
T12	0	178	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	36960	0	0
T46	0	100	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	96	0	0
T57	0	126	0	0
T72	0	116	0	0
T73	0	216	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001877	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4512	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	9	0	0
T38	655	0	0	0
T39	13435	0	0	0
T57	1866	2	0	0
T61	490	0	0	0
T65	9508	0	0	0
T72	2107	0	0	0
T73	0	5	0	0
T81	0	1	0	0
T82	0	1	0	0
T126	870	0	0	0
T127	422	0	0	0
T128	673	0	0	0
T129	23978	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	204483	0	0
T7	9756	140	0	0
T8	14317	0	0	0
T9	8766	17	0	0
T10	626	0	0	0
T11	0	336	0	0
T12	0	604	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	110523	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	533	0	0
T57	0	44	0	0
T72	0	435	0	0
T73	0	38	0	0
T115	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	49	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0
T115	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4493299	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4119	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4495647	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4134	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	111	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T46	0	5	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	3	0	0
T72	0	2	0	0
T73	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	58	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	3	0	0
T72	0	2	0	0
T73	0	6	0	0
T81	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	49	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0
T115	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	49	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0
T115	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	204434	0	0
T7	9756	139	0	0
T8	14317	0	0	0
T9	8766	16	0	0
T10	626	0	0	0
T11	0	335	0	0
T12	0	602	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	110522	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	532	0	0
T57	0	43	0	0
T72	0	433	0	0
T73	0	37	0	0
T115	0	89	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	8260	0	0
T7	9756	211	0	0
T8	14317	0	0	0
T9	8766	374	0	0
T10	626	0	0	0
T11	0	344	0	0
T12	0	106	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T42	0	33	0	0
T50	438	0	0	0
T51	822	0	0	0
T55	0	328	0	0
T57	0	226	0	0
T72	0	288	0	0
T73	0	218	0	0
T115	0	691	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T12,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T10,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T25
0	1	Covered	T35
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T25
0	1	Covered	T12,T25,T130
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T12,T25
1	-	Covered	T12,T25,T130

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T12,T25
DetectSt	168	Covered	T10,T12,T25
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T12,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T12,T25
DebounceSt->IdleSt	163	Covered	T12,T74
DetectSt->IdleSt	186	Covered	T35
DetectSt->StableSt	191	Covered	T10,T12,T25
IdleSt->DebounceSt	148	Covered	T10,T12,T25
StableSt->IdleSt	206	Covered	T12,T25,T130

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T12,T25
0	1	Covered	T10,T12,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T12,T25
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T12,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T12,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T12
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T12,T25
DetectSt	-	-	-	-	1	-	-	Covered	T35
DetectSt	-	-	-	-	0	1	-	Covered	T10,T12,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T25,T130
StableSt	-	-	-	-	-	-	0	Covered	T10,T12,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	86	0	0
CntIncr_A	5638357	51417	0	0
CntNoWrap_A	5638357	5001958	0	0
DetectStDropOut_A	5638357	2	0	0
DetectedOut_A	5638357	2738	0	0
DetectedPulseOut_A	5638357	40	0	0
DisabledIdleSt_A	5638357	4795767	0	0
DisabledNoDetection_A	5638357	4798066	0	0
EnterDebounceSt_A	5638357	44	0	0
EnterDetectSt_A	5638357	42	0	0
EnterStableSt_A	5638357	40	0	0
PulseIsPulse_A	5638357	40	0	0
StayInStableSt	5638357	2682	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	86	0	0
T10	626	2	0	0
T11	1317	0	0	0
T12	10728	5	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T35	0	4	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	2	0	0
T79	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0
T132	0	6	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	51417	0	0
T10	626	69	0	0
T11	1317	0	0	0
T12	10728	176	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	18	0	0
T26	682	0	0	0
T35	0	136	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	66	0	0
T79	0	70	0	0
T130	0	96	0	0
T131	0	38	0	0
T132	0	100	0	0
T133	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001958	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2	0	0
T35	955	2	0	0
T62	493	0	0	0
T67	27167	0	0	0
T68	23545	0	0	0
T69	510	0	0	0
T134	2252	0	0	0
T135	412	0	0	0
T136	667	0	0	0
T137	504	0	0	0
T138	1056	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2738	0	0
T10	626	60	0	0
T11	1317	0	0	0
T12	10728	45	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	8	0	0
T26	682	0	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	47	0	0
T79	0	197	0	0
T107	0	82	0	0
T130	0	40	0	0
T131	0	155	0	0
T132	0	123	0	0
T133	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	40	0	0
T10	626	1	0	0
T11	1317	0	0	0
T12	10728	2	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	1	0	0
T79	0	1	0	0
T107	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4795767	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4359	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4798066	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4373	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	44	0	0
T10	626	1	0	0
T11	1317	0	0	0
T12	10728	3	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T35	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	1	0	0
T79	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	42	0	0
T10	626	1	0	0
T11	1317	0	0	0
T12	10728	2	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T35	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	1	0	0
T79	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	40	0	0
T10	626	1	0	0
T11	1317	0	0	0
T12	10728	2	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	1	0	0
T79	0	1	0	0
T107	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	40	0	0
T10	626	1	0	0
T11	1317	0	0	0
T12	10728	2	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	1	0	0
T79	0	1	0	0
T107	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	3	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2682	0	0
T10	626	58	0	0
T11	1317	0	0	0
T12	10728	42	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	7	0	0
T26	682	0	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T53	522	0	0	0
T77	0	45	0	0
T79	0	195	0	0
T107	0	81	0	0
T130	0	39	0	0
T131	0	153	0	0
T132	0	119	0	0
T133	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	23	0	0
T12	10728	1	0	0
T13	21096	0	0	0
T25	2457	1	0	0
T27	12059	0	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T100	0	1	0	0
T104	526	0	0	0
T105	431	0	0	0
T107	0	1	0	0
T130	0	1	0	0
T132	0	2	0	0
T133	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T25,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T25,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T25,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T37
1	0	Covered	T4,T5,T6
1	1	Covered	T12,T25,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T37
0	1	Covered	T78,T79,T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T37
0	1	Covered	T12,T25,T37
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T25,T37
1	-	Covered	T12,T25,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T25,T37
DetectSt	168	Covered	T12,T25,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T25,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T25,T37
DebounceSt->IdleSt	163	Covered	T143,T144,T74
DetectSt->IdleSt	186	Covered	T78,T79,T142
DetectSt->StableSt	191	Covered	T12,T25,T37
IdleSt->DebounceSt	148	Covered	T12,T25,T37
StableSt->IdleSt	206	Covered	T12,T25,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T25,T37
0	1	Covered	T12,T25,T37
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T25,T37
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T25,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T25,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T25,T37
DetectSt	-	-	-	-	1	-	-	Covered	T78,T79,T142
DetectSt	-	-	-	-	0	1	-	Covered	T12,T25,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T25,T37
StableSt	-	-	-	-	-	-	0	Covered	T12,T25,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	161	0	0
CntIncr_A	5638357	77841	0	0
CntNoWrap_A	5638357	5001883	0	0
DetectStDropOut_A	5638357	4	0	0
DetectedOut_A	5638357	71899	0	0
DetectedPulseOut_A	5638357	75	0	0
DisabledIdleSt_A	5638357	4793360	0	0
DisabledNoDetection_A	5638357	4795652	0	0
EnterDebounceSt_A	5638357	83	0	0
EnterDetectSt_A	5638357	79	0	0
EnterStableSt_A	5638357	75	0	0
PulseIsPulse_A	5638357	75	0	0
StayInStableSt	5638357	71794	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5638357	2599	0	0
gen_low_level_sva.LowLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	44	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	161	0	0
T12	10728	4	0	0
T13	21096	0	0	0
T25	2457	6	0	0
T27	12059	0	0	0
T34	0	4	0	0
T37	0	4	0	0
T38	0	2	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	4	0	0
T79	0	2	0	0
T82	0	4	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	4	0	0
T147	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	77841	0	0
T12	10728	158	0	0
T13	21096	0	0	0
T25	2457	53	0	0
T27	12059	0	0	0
T34	0	142	0	0
T37	0	68	0	0
T38	0	19	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	22	0	0
T82	0	107	0	0
T104	526	0	0	0
T105	431	0	0	0
T143	0	79	0	0
T146	0	200	0	0
T147	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001883	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4	0	0
T78	610	1	0	0
T79	38283	1	0	0
T142	0	1	0	0
T148	0	1	0	0
T149	407	0	0	0
T150	41282	0	0	0
T151	435	0	0	0
T152	19971	0	0	0
T153	767	0	0	0
T154	527	0	0	0
T155	28846	0	0	0
T156	20510	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	71899	0	0
T12	10728	86	0	0
T13	21096	0	0	0
T25	2457	153	0	0
T27	12059	0	0	0
T34	0	26	0	0
T37	0	150	0	0
T38	0	76	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	58	0	0
T82	0	339	0	0
T104	526	0	0	0
T105	431	0	0	0
T131	0	27	0	0
T146	0	324	0	0
T147	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	75	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	3	0	0
T27	12059	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	1	0	0
T82	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T131	0	1	0	0
T146	0	2	0	0
T147	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4793360	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4795652	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	83	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	3	0	0
T27	12059	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	2	0	0
T82	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T143	0	1	0	0
T146	0	2	0	0
T147	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	79	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	3	0	0
T27	12059	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	2	0	0
T79	0	1	0	0
T82	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	2	0	0
T147	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	75	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	3	0	0
T27	12059	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	1	0	0
T82	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T131	0	1	0	0
T146	0	2	0	0
T147	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	75	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	3	0	0
T27	12059	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	1	0	0
T82	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T131	0	1	0	0
T146	0	2	0	0
T147	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	71794	0	0
T12	10728	84	0	0
T13	21096	0	0	0
T25	2457	149	0	0
T27	12059	0	0	0
T34	0	24	0	0
T37	0	147	0	0
T38	0	75	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T78	0	56	0	0
T82	0	335	0	0
T104	526	0	0	0
T105	431	0	0	0
T131	0	26	0	0
T146	0	322	0	0
T147	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2599	0	0
T1	14725	0	0	0
T2	17278	0	0	0
T3	18805	0	0	0
T4	502	5	0	0
T5	521	6	0	0
T6	422	3	0	0
T7	9756	24	0	0
T8	14317	0	0	0
T9	0	25	0	0
T10	0	1	0	0
T14	454	5	0	0
T15	0	6	0	0
T17	611	0	0	0
T23	0	5	0	0
T50	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	44	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	2	0	0
T27	12059	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T104	526	0	0	0
T105	431	0	0	0
T107	0	1	0	0
T131	0	1	0	0
T133	0	1	0	0
T146	0	2	0	0
T157	0	2	0	0