Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T12,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T12,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T25
0	1	Covered	T35
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T37
0	1	Covered	T9,T12,T25
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T37
1	-	Covered	T9,T12,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T12,T25
DetectSt	168	Covered	T9,T12,T25
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T12,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T25
DebounceSt->IdleSt	163	Covered	T37,T35,T36
DetectSt->IdleSt	186	Covered	T35
DetectSt->StableSt	191	Covered	T9,T12,T25
IdleSt->DebounceSt	148	Covered	T9,T12,T25
StableSt->IdleSt	206	Covered	T9,T12,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T12,T25
0	1	Covered	T9,T12,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T25
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T12,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T35,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T12,T25
DetectSt	-	-	-	-	1	-	-	Covered	T35
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T25
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	138	0	0
CntIncr_A	5638357	3961	0	0
CntNoWrap_A	5638357	5001906	0	0
DetectStDropOut_A	5638357	1	0	0
DetectedOut_A	5638357	5434	0	0
DetectedPulseOut_A	5638357	65	0	0
DisabledIdleSt_A	5638357	4982092	0	0
DisabledNoDetection_A	5638357	4984390	0	0
EnterDebounceSt_A	5638357	74	0	0
EnterDetectSt_A	5638357	66	0	0
EnterStableSt_A	5638357	65	0	0
PulseIsPulse_A	5638357	65	0	0
StayInStableSt	5638357	5342	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	138	0	0
T9	8766	2	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	8	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	6	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	5	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	4	0	0
T146	0	2	0	0
T158	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	3961	0	0
T9	8766	54	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	194	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	17	0	0
T26	682	0	0	0
T34	0	195	0	0
T35	0	136	0	0
T36	0	47	0	0
T37	0	102	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	132	0	0
T146	0	100	0	0
T158	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001906	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1	0	0
T35	955	1	0	0
T62	493	0	0	0
T67	27167	0	0	0
T68	23545	0	0	0
T69	510	0	0	0
T134	2252	0	0	0
T135	412	0	0	0
T136	667	0	0	0
T137	504	0	0	0
T138	1056	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5434	0	0
T9	8766	45	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	196	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	220	0	0
T37	0	84	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	89	0	0
T82	0	167	0	0
T143	0	45	0	0
T146	0	328	0	0
T158	0	168	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	65	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	4	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T37	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	2	0	0
T82	0	3	0	0
T143	0	1	0	0
T146	0	1	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4982092	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4984390	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	74	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	4	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	3	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	2	0	0
T146	0	1	0	0
T158	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	66	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	4	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T35	0	1	0	0
T37	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	2	0	0
T143	0	1	0	0
T146	0	1	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	65	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	4	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T37	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	2	0	0
T82	0	3	0	0
T143	0	1	0	0
T146	0	1	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	65	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	4	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T37	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	2	0	0
T82	0	3	0	0
T143	0	1	0	0
T146	0	1	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5342	0	0
T9	8766	44	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	190	0	0
T23	495	0	0	0
T24	2609	0	0	0
T26	682	0	0	0
T34	0	216	0	0
T37	0	81	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	86	0	0
T82	0	163	0	0
T130	0	40	0	0
T143	0	43	0	0
T146	0	326	0	0
T158	0	166	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	37	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	2	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	2	0	0
T130	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T25,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T12,T25,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T34,T77

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T12,T25,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T34,T36
0	1	Covered	T77,T132
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T34,T36
0	1	Covered	T34,T169,T82
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T34,T36
1	-	Covered	T34,T169,T82

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T25,T34
DetectSt	168	Covered	T25,T34,T77
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T25,T34,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T34,T77
DebounceSt->IdleSt	163	Covered	T12,T79,T74
DetectSt->IdleSt	186	Covered	T77,T132
DetectSt->StableSt	191	Covered	T25,T34,T36
IdleSt->DebounceSt	148	Covered	T12,T25,T34
StableSt->IdleSt	206	Covered	T25,T34,T169

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T25,T34
0	1	Covered	T12,T25,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T34,T77
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T25,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T34,T77
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T79
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T25,T34
DetectSt	-	-	-	-	1	-	-	Covered	T77,T132
DetectSt	-	-	-	-	0	1	-	Covered	T25,T34,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T169,T82
StableSt	-	-	-	-	-	-	0	Covered	T25,T34,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	83	0	0
CntIncr_A	5638357	2478	0	0
CntNoWrap_A	5638357	5001961	0	0
DetectStDropOut_A	5638357	2	0	0
DetectedOut_A	5638357	2657	0	0
DetectedPulseOut_A	5638357	38	0	0
DisabledIdleSt_A	5638357	4970432	0	0
DisabledNoDetection_A	5638357	4972727	0	0
EnterDebounceSt_A	5638357	43	0	0
EnterDetectSt_A	5638357	40	0	0
EnterStableSt_A	5638357	38	0	0
PulseIsPulse_A	5638357	38	0	0
StayInStableSt	5638357	2598	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5638357	6154	0	0
gen_low_level_sva.LowLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	83	0	0
T12	10728	1	0	0
T13	21096	0	0	0
T25	2457	2	0	0
T27	12059	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	2	0	0
T79	0	1	0	0
T82	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T169	0	2	0	0
T178	0	2	0	0
T211	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2478	0	0
T12	10728	79	0	0
T13	21096	0	0	0
T25	2457	18	0	0
T27	12059	0	0	0
T34	0	62	0	0
T36	0	47	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	66	0	0
T79	0	70	0	0
T82	0	87	0	0
T104	526	0	0	0
T105	431	0	0	0
T169	0	38	0	0
T178	0	94	0	0
T211	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001961	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2	0	0
T48	598	0	0	0
T49	755	0	0	0
T73	1760	0	0	0
T77	789	1	0	0
T87	582	0	0	0
T132	0	1	0	0
T212	493	0	0	0
T213	524	0	0	0
T214	422	0	0	0
T215	403	0	0	0
T216	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2657	0	0
T25	2457	124	0	0
T28	461	0	0	0
T34	0	31	0	0
T36	0	43	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T82	0	39	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T132	0	39	0	0
T133	0	38	0	0
T144	0	52	0	0
T169	0	40	0	0
T178	0	41	0	0
T211	0	47	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	38	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T82	0	1	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0
T211	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4970432	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4972727	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	43	0	0
T12	10728	1	0	0
T13	21096	0	0	0
T25	2457	1	0	0
T27	12059	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	1	0	0
T79	0	1	0	0
T82	0	1	0	0
T104	526	0	0	0
T105	431	0	0	0
T169	0	1	0	0
T178	0	1	0	0
T211	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	40	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	1	0	0
T82	0	1	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T132	0	2	0	0
T133	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0
T211	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	38	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T82	0	1	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0
T211	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	38	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T82	0	1	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T144	0	1	0	0
T169	0	1	0	0
T178	0	1	0	0
T211	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2598	0	0
T25	2457	122	0	0
T28	461	0	0	0
T34	0	30	0	0
T36	0	41	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T82	0	38	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T132	0	37	0	0
T133	0	36	0	0
T144	0	51	0	0
T169	0	39	0	0
T178	0	39	0	0
T211	0	45	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	6154	0	0
T1	14725	10	0	0
T2	17278	11	0	0
T3	18805	10	0	0
T4	502	5	0	0
T5	521	5	0	0
T6	422	2	0	0
T7	9756	23	0	0
T8	14317	34	0	0
T14	454	8	0	0
T15	0	4	0	0
T17	611	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	16	0	0
T34	17042	1	0	0
T39	13435	0	0	0
T57	1866	0	0	0
T61	490	0	0	0
T65	9508	0	0	0
T72	2107	0	0	0
T82	0	1	0	0
T126	870	0	0	0
T127	422	0	0	0
T128	673	0	0	0
T140	0	1	0	0
T141	0	1	0	0
T144	0	1	0	0
T157	0	1	0	0
T160	0	2	0	0
T169	0	1	0	0
T186	0	2	0	0
T210	8402	0	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T9,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T9,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T9,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T25
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T25
0	1	Covered	T9,T25,T34
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T25
1	-	Covered	T9,T25,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T25
DetectSt	168	Covered	T7,T9,T25
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T9,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T25
DebounceSt->IdleSt	163	Covered	T9,T74,T218
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T9,T25
IdleSt->DebounceSt	148	Covered	T7,T9,T25
StableSt->IdleSt	206	Covered	T7,T9,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T25
0	1	Covered	T7,T9,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T25
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T198,T219
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T25
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T25,T34
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	123	0	0
CntIncr_A	5638357	13909	0	0
CntNoWrap_A	5638357	5001921	0	0
DetectStDropOut_A	5638357	0	0	0
DetectedOut_A	5638357	7661	0	0
DetectedPulseOut_A	5638357	59	0	0
DisabledIdleSt_A	5638357	4952632	0	0
DisabledNoDetection_A	5638357	4954932	0	0
EnterDebounceSt_A	5638357	65	0	0
EnterDetectSt_A	5638357	59	0	0
EnterStableSt_A	5638357	59	0	0
PulseIsPulse_A	5638357	59	0	0
StayInStableSt	5638357	7572	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	123	0	0
T7	9756	2	0	0
T8	14317	0	0	0
T9	8766	3	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	6	0	0
T35	0	4	0	0
T37	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	2	0	0
T77	0	4	0	0
T143	0	2	0	0
T147	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	13909	0	0
T7	9756	38	0	0
T8	14317	0	0	0
T9	8766	108	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	17	0	0
T26	682	0	0	0
T34	0	204	0	0
T35	0	136	0	0
T37	0	34	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	77	0	0
T77	0	132	0	0
T143	0	30	0	0
T147	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001921	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4512	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	7661	0	0
T7	9756	111	0	0
T8	14317	0	0	0
T9	8766	91	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	76	0	0
T26	682	0	0	0
T34	0	77	0	0
T35	0	154	0	0
T37	0	50	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	41	0	0
T77	0	71	0	0
T143	0	44	0	0
T147	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	59	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	1	0	0
T77	0	2	0	0
T143	0	1	0	0
T147	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4952632	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4359	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4954932	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4373	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	65	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	2	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	1	0	0
T77	0	2	0	0
T143	0	1	0	0
T147	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	59	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	1	0	0
T77	0	2	0	0
T143	0	1	0	0
T147	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	59	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	1	0	0
T77	0	2	0	0
T143	0	1	0	0
T147	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	59	0	0
T7	9756	1	0	0
T8	14317	0	0	0
T9	8766	1	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T37	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	1	0	0
T77	0	2	0	0
T143	0	1	0	0
T147	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	7572	0	0
T7	9756	109	0	0
T8	14317	0	0	0
T9	8766	90	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T25	0	75	0	0
T26	682	0	0	0
T34	0	73	0	0
T35	0	152	0	0
T37	0	48	0	0
T50	438	0	0	0
T51	822	0	0	0
T64	0	39	0	0
T77	0	68	0	0
T143	0	42	0	0
T147	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	28	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	1	0	0
T26	682	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	1	0	0
T78	0	1	0	0
T82	0	1	0	0
T131	0	1	0	0
T132	0	2	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T25,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T10,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T25,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T34,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T34,T35
0	1	Covered	T25,T77,T130
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T34,T35
1	-	Covered	T25,T77,T130

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T34,T35
DetectSt	168	Covered	T25,T34,T35
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T25,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T34,T35
DebounceSt->IdleSt	163	Covered	T35,T131,T133
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T25,T34,T35
IdleSt->DebounceSt	148	Covered	T25,T34,T35
StableSt->IdleSt	206	Covered	T25,T34,T77

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T34,T35
0	1	Covered	T25,T34,T35
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T34,T35
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T131,T133
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T34,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T25,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T77,T130
StableSt	-	-	-	-	-	-	0	Covered	T25,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	70	0	0
CntIncr_A	5638357	2114	0	0
CntNoWrap_A	5638357	5001974	0	0
DetectStDropOut_A	5638357	0	0	0
DetectedOut_A	5638357	2157	0	0
DetectedPulseOut_A	5638357	32	0	0
DisabledIdleSt_A	5638357	4782575	0	0
DisabledNoDetection_A	5638357	4784874	0	0
EnterDebounceSt_A	5638357	38	0	0
EnterDetectSt_A	5638357	32	0	0
EnterStableSt_A	5638357	32	0	0
PulseIsPulse_A	5638357	32	0	0
StayInStableSt	5638357	2113	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5638357	6121	0	0
gen_low_level_sva.LowLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	70	0	0
T25	2457	2	0	0
T28	461	0	0	0
T34	0	2	0	0
T35	0	3	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	2	0	0
T106	523	0	0	0
T107	0	2	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	2	0	0
T131	0	1	0	0
T133	0	3	0	0
T158	0	2	0	0
T185	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2114	0	0
T25	2457	18	0	0
T28	461	0	0	0
T34	0	62	0	0
T35	0	136	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	66	0	0
T106	523	0	0	0
T107	0	85	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	96	0	0
T131	0	38	0	0
T133	0	40	0	0
T158	0	75	0	0
T185	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001974	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2157	0	0
T25	2457	7	0	0
T28	461	0	0	0
T34	0	44	0	0
T35	0	118	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	109	0	0
T106	523	0	0	0
T107	0	213	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	95	0	0
T133	0	1	0	0
T158	0	43	0	0
T185	0	41	0	0
T186	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	1	0	0
T106	523	0	0	0
T107	0	1	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	1	0	0
T133	0	1	0	0
T158	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4782575	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4359	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4784874	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4373	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	38	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T35	0	2	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	1	0	0
T106	523	0	0	0
T107	0	1	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	1	0	0
T131	0	1	0	0
T133	0	2	0	0
T158	0	1	0	0
T185	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	1	0	0
T106	523	0	0	0
T107	0	1	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	1	0	0
T133	0	1	0	0
T158	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	1	0	0
T106	523	0	0	0
T107	0	1	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	1	0	0
T133	0	1	0	0
T158	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	1	0	0
T106	523	0	0	0
T107	0	1	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	1	0	0
T133	0	1	0	0
T158	0	1	0	0
T185	0	1	0	0
T186	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2113	0	0
T25	2457	6	0	0
T28	461	0	0	0
T34	0	42	0	0
T35	0	116	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	108	0	0
T106	523	0	0	0
T107	0	211	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	94	0	0
T158	0	41	0	0
T185	0	39	0	0
T186	0	68	0	0
T209	0	79	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	6121	0	0
T1	14725	11	0	0
T2	17278	13	0	0
T3	18805	11	0	0
T4	502	4	0	0
T5	521	4	0	0
T6	422	4	0	0
T7	9756	20	0	0
T8	14317	39	0	0
T14	454	6	0	0
T15	0	6	0	0
T17	611	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	19	0	0
T25	2457	1	0	0
T28	461	0	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T77	0	1	0	0
T100	0	1	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T130	0	1	0	0
T133	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T186	0	2	0	0
T209	0	1	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T12,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T25,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T37
0	1	Covered	T82,T133,T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T37
0	1	Covered	T12,T25,T37
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T25,T37
1	-	Covered	T12,T25,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T12,T25
DetectSt	168	Covered	T12,T25,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T25,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T25,T37
DebounceSt->IdleSt	163	Covered	T9,T12,T25
DetectSt->IdleSt	186	Covered	T82,T133,T186
DetectSt->StableSt	191	Covered	T12,T25,T37
IdleSt->DebounceSt	148	Covered	T9,T12,T25
StableSt->IdleSt	206	Covered	T12,T25,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T12,T25
0	1	Covered	T9,T12,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T25,T37
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T12,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T25,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T12,T25
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T12,T25
DetectSt	-	-	-	-	1	-	-	Covered	T82,T133,T186
DetectSt	-	-	-	-	0	1	-	Covered	T12,T25,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T25,T37
StableSt	-	-	-	-	-	-	0	Covered	T12,T25,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	150	0	0
CntIncr_A	5638357	53137	0	0
CntNoWrap_A	5638357	5001894	0	0
DetectStDropOut_A	5638357	3	0	0
DetectedOut_A	5638357	79707	0	0
DetectedPulseOut_A	5638357	68	0	0
DisabledIdleSt_A	5638357	4795061	0	0
DisabledNoDetection_A	5638357	4797355	0	0
EnterDebounceSt_A	5638357	79	0	0
EnterDetectSt_A	5638357	71	0	0
EnterStableSt_A	5638357	68	0	0
PulseIsPulse_A	5638357	68	0	0
StayInStableSt	5638357	79613	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	150	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	5	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	3	0	0
T26	682	0	0	0
T34	0	6	0	0
T37	0	4	0	0
T38	0	4	0	0
T46	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	4	0	0
T146	0	2	0	0
T147	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	53137	0	0
T9	8766	54	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	176	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	36	0	0
T26	682	0	0	0
T34	0	204	0	0
T37	0	68	0	0
T38	0	38	0	0
T46	0	51	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	132	0	0
T146	0	100	0	0
T147	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001894	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	3	0	0
T82	62263	1	0	0
T91	25681	0	0	0
T130	1792	0	0	0
T133	0	1	0	0
T186	0	1	0	0
T190	10487	0	0	0
T191	427	0	0	0
T192	424	0	0	0
T193	496	0	0	0
T194	859	0	0	0
T195	6050	0	0	0
T196	493	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	79707	0	0
T12	10728	186	0	0
T13	21096	0	0	0
T25	2457	9	0	0
T27	12059	0	0	0
T34	0	403	0	0
T36	0	177	0	0
T37	0	65	0	0
T38	0	173	0	0
T40	652	0	0	0
T41	6388	0	0	0
T46	0	49	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	69	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	333	0	0
T147	0	10	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	68	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	1	0	0
T27	12059	0	0	0
T34	0	3	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	652	0	0	0
T41	6388	0	0	0
T46	0	1	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	1	0	0
T147	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4795061	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4359	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4797355	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4373	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	79	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	3	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	3	0	0
T37	0	2	0	0
T38	0	2	0	0
T46	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T77	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	71	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	1	0	0
T27	12059	0	0	0
T34	0	3	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	652	0	0	0
T41	6388	0	0	0
T46	0	1	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	1	0	0
T147	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	68	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	1	0	0
T27	12059	0	0	0
T34	0	3	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	652	0	0	0
T41	6388	0	0	0
T46	0	1	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	1	0	0
T147	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	68	0	0
T12	10728	2	0	0
T13	21096	0	0	0
T25	2457	1	0	0
T27	12059	0	0	0
T34	0	3	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	652	0	0	0
T41	6388	0	0	0
T46	0	1	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	1	0	0
T147	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	79613	0	0
T12	10728	183	0	0
T13	21096	0	0	0
T25	2457	8	0	0
T27	12059	0	0	0
T34	0	398	0	0
T36	0	176	0	0
T37	0	63	0	0
T38	0	170	0	0
T40	652	0	0	0
T41	6388	0	0	0
T46	0	47	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	66	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	332	0	0
T147	0	9	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	41	0	0
T12	10728	1	0	0
T13	21096	0	0	0
T25	2457	1	0	0
T27	12059	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	652	0	0	0
T41	6388	0	0	0
T53	522	0	0	0
T63	504	0	0	0
T77	0	1	0	0
T82	0	2	0	0
T104	526	0	0	0
T105	431	0	0	0
T146	0	1	0	0
T147	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T25,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T25,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T25,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T25,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T25,T34
0	1	Covered	T25,T34,T169
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T25,T34
1	-	Covered	T25,T34,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T34
DetectSt	168	Covered	T9,T25,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T25,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T25,T34
DebounceSt->IdleSt	163	Covered	T74
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T25,T34
IdleSt->DebounceSt	148	Covered	T9,T25,T34
StableSt->IdleSt	206	Covered	T9,T25,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T34
0	1	Covered	T9,T25,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T25,T34
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T25,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T25,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T34,T169
StableSt	-	-	-	-	-	-	0	Covered	T9,T25,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	65	0	0
CntIncr_A	5638357	1818	0	0
CntNoWrap_A	5638357	5001979	0	0
DetectStDropOut_A	5638357	0	0	0
DetectedOut_A	5638357	1703	0	0
DetectedPulseOut_A	5638357	32	0	0
DisabledIdleSt_A	5638357	4955151	0	0
DisabledNoDetection_A	5638357	4957458	0	0
EnterDebounceSt_A	5638357	33	0	0
EnterDetectSt_A	5638357	32	0	0
EnterStableSt_A	5638357	32	0	0
PulseIsPulse_A	5638357	32	0	0
StayInStableSt	5638357	1658	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5638357	6768	0	0
gen_low_level_sva.LowLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	65	0	0
T9	8766	2	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	4	0	0
T26	682	0	0	0
T34	0	2	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	4	0	0
T130	0	2	0	0
T144	0	2	0	0
T147	0	2	0	0
T157	0	2	0	0
T169	0	4	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1818	0	0
T9	8766	54	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	36	0	0
T26	682	0	0	0
T34	0	71	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	174	0	0
T130	0	96	0	0
T144	0	11	0	0
T147	0	19	0	0
T157	0	92	0	0
T169	0	76	0	0
T179	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001979	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1703	0	0
T9	8766	41	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	76	0	0
T26	682	0	0	0
T34	0	21	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	84	0	0
T130	0	49	0	0
T144	0	40	0	0
T147	0	40	0	0
T157	0	40	0	0
T169	0	83	0	0
T179	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	2	0	0
T130	0	1	0	0
T144	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T169	0	2	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4955151	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4957458	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	33	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	2	0	0
T130	0	1	0	0
T144	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T169	0	2	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	2	0	0
T130	0	1	0	0
T144	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T169	0	2	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	2	0	0
T130	0	1	0	0
T144	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T169	0	2	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	32	0	0
T9	8766	1	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	2	0	0
T26	682	0	0	0
T34	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	2	0	0
T130	0	1	0	0
T144	0	1	0	0
T147	0	1	0	0
T157	0	1	0	0
T169	0	2	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1658	0	0
T9	8766	39	0	0
T10	626	0	0	0
T11	1317	0	0	0
T12	10728	0	0	0
T23	495	0	0	0
T24	2609	0	0	0
T25	0	73	0	0
T26	682	0	0	0
T34	0	20	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T82	0	81	0	0
T130	0	47	0	0
T144	0	39	0	0
T147	0	38	0	0
T157	0	38	0	0
T169	0	80	0	0
T179	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	6768	0	0
T1	14725	11	0	0
T2	17278	7	0	0
T3	18805	8	0	0
T4	502	6	0	0
T5	521	5	0	0
T6	422	3	0	0
T7	9756	31	0	0
T8	14317	22	0	0
T14	454	4	0	0
T15	0	7	0	0
T17	611	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	18	0	0
T25	2457	1	0	0
T28	461	0	0	0
T34	0	1	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T82	0	1	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T144	0	1	0	0
T160	0	1	0	0
T169	0	1	0	0
T179	0	1	0	0
T184	0	1	0	0
T186	0	2	0	0
T188	0	1	0	0