Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T27,T29
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T28
0	1	Covered	T27,T39,T65
1	0	Covered	T27,T39,T65

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T29
0	1	Covered	T8,T29,T66
1	0	Covered	T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T28,T29
1	-	Covered	T8,T29,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T28
DetectSt	168	Covered	T8,T27,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T28,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T27,T28
DebounceSt->IdleSt	163	Covered	T220,T221,T74
DetectSt->IdleSt	186	Covered	T27,T39,T65
DetectSt->StableSt	191	Covered	T8,T28,T29
IdleSt->DebounceSt	148	Covered	T8,T27,T28
StableSt->IdleSt	206	Covered	T8,T29,T66

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T27,T28
0	1	Covered	T8,T27,T28
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T27,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T8,T27,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T220,T221,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T27,T39,T65
DetectSt	-	-	-	-	0	1	-	Covered	T8,T28,T29
DetectSt	-	-	-	-	0	0	-	Covered	T8,T27,T28
StableSt	-	-	-	-	-	-	1	Covered	T8,T29,T66
StableSt	-	-	-	-	-	-	0	Covered	T8,T28,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	3033	0	0
CntIncr_A	5638357	94985	0	0
CntNoWrap_A	5638357	4999011	0	0
DetectStDropOut_A	5638357	460	0	0
DetectedOut_A	5638357	68908	0	0
DetectedPulseOut_A	5638357	856	0	0
DisabledIdleSt_A	5638357	4581464	0	0
DisabledNoDetection_A	5638357	4583598	0	0
EnterDebounceSt_A	5638357	1532	0	0
EnterDetectSt_A	5638357	1501	0	0
EnterStableSt_A	5638357	856	0	0
PulseIsPulse_A	5638357	856	0	0
StayInStableSt	5638357	67928	0	0
gen_high_event_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	731	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	3033	0	0
T8	14317	46	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	60	0	0
T28	0	2	0	0
T29	0	46	0	0
T39	0	42	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	24	0	0
T66	0	26	0	0
T67	0	26	0	0
T68	0	34	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	94985	0	0
T8	14317	1748	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	1636	0	0
T28	0	21	0	0
T29	0	1587	0	0
T39	0	1344	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	760	0	0
T66	0	884	0	0
T67	0	1040	0	0
T68	0	1360	0	0
T69	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4999011	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13861	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	460	0	0
T25	2457	0	0	0
T27	12059	21	0	0
T28	461	0	0	0
T39	0	19	0	0
T41	6388	0	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T63	504	0	0	0
T65	0	5	0	0
T71	0	21	0	0
T88	0	9	0	0
T89	0	16	0	0
T90	0	11	0	0
T91	0	14	0	0
T92	0	12	0	0
T104	526	0	0	0
T105	431	0	0	0
T106	523	0	0	0
T220	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	68908	0	0
T8	14317	2018	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T28	0	35	0	0
T29	0	4086	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	1510	0	0
T67	0	1206	0	0
T68	0	2325	0	0
T69	0	84	0	0
T70	0	1303	0	0
T222	0	236	0	0
T223	0	2743	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	856	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T28	0	1	0	0
T29	0	23	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	13	0	0
T67	0	13	0	0
T68	0	17	0	0
T69	0	1	0	0
T70	0	16	0	0
T222	0	12	0	0
T223	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4581464	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	6869	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4583598	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	6869	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1532	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	30	0	0
T28	0	1	0	0
T29	0	23	0	0
T39	0	21	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	12	0	0
T66	0	13	0	0
T67	0	13	0	0
T68	0	17	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1501	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	30	0	0
T28	0	1	0	0
T29	0	23	0	0
T39	0	21	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	12	0	0
T66	0	13	0	0
T67	0	13	0	0
T68	0	17	0	0
T69	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	856	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T28	0	1	0	0
T29	0	23	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	13	0	0
T67	0	13	0	0
T68	0	17	0	0
T69	0	1	0	0
T70	0	16	0	0
T222	0	12	0	0
T223	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	856	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T28	0	1	0	0
T29	0	23	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	13	0	0
T67	0	13	0	0
T68	0	17	0	0
T69	0	1	0	0
T70	0	16	0	0
T222	0	12	0	0
T223	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	67928	0	0
T8	14317	1993	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T28	0	33	0	0
T29	0	4057	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	1493	0	0
T67	0	1190	0	0
T68	0	2304	0	0
T69	0	82	0	0
T70	0	1287	0	0
T222	0	223	0	0
T223	0	2706	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	731	0	0
T8	14317	21	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T29	0	17	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	9	0	0
T67	0	10	0	0
T68	0	13	0	0
T70	0	16	0	0
T155	0	1	0	0
T222	0	11	0	0
T223	0	17	0	0
T224	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T93,T94
1	0	Covered	T74,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T9,T12,T43
DetectSt->IdleSt	186	Covered	T13,T93,T94
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T43,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T13,T93,T94
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	994	0	0
CntIncr_A	5638357	51180	0	0
CntNoWrap_A	5638357	5001050	0	0
DetectStDropOut_A	5638357	47	0	0
DetectedOut_A	5638357	18039	0	0
DetectedPulseOut_A	5638357	405	0	0
DisabledIdleSt_A	5638357	4627339	0	0
DisabledNoDetection_A	5638357	4628917	0	0
EnterDebounceSt_A	5638357	539	0	0
EnterDetectSt_A	5638357	455	0	0
EnterStableSt_A	5638357	405	0	0
PulseIsPulse_A	5638357	405	0	0
StayInStableSt	5638357	17596	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	359	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	994	0	0
T1	14725	6	0	0
T2	17278	2	0	0
T3	18805	4	0	0
T7	9756	4	0	0
T8	14317	2	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	4	0	0
T13	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T28	0	1	0	0
T42	0	2	0	0
T43	0	17	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	51180	0	0
T1	14725	414	0	0
T2	17278	117	0	0
T3	18805	262	0	0
T7	9756	212	0	0
T8	14317	76	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	65	0	0
T13	0	84	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T28	0	20	0	0
T42	0	25	0	0
T43	0	771	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001050	0	0
T1	14725	14290	0	0
T2	17278	16838	0	0
T3	18805	18359	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4510	0	0
T8	14317	13905	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	47	0	0
T13	21096	1	0	0
T25	2457	0	0	0
T27	12059	0	0	0
T41	6388	0	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T63	504	0	0	0
T93	0	4	0	0
T94	0	4	0	0
T97	0	4	0	0
T98	0	13	0	0
T99	0	3	0	0
T100	0	8	0	0
T101	0	5	0	0
T103	0	5	0	0
T104	526	0	0	0
T105	431	0	0	0
T106	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	18039	0	0
T1	14725	45	0	0
T2	17278	65	0	0
T3	18805	44	0	0
T7	9756	19	0	0
T8	14317	78	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	3	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T42	0	3	0	0
T43	0	141	0	0
T59	0	3	0	0
T114	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	405	0	0
T1	14725	3	0	0
T2	17278	1	0	0
T3	18805	2	0	0
T7	9756	2	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	1	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T42	0	1	0	0
T43	0	8	0	0
T59	0	1	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4627339	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	3833	0	0
T8	14317	11891	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4628917	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	3846	0	0
T8	14317	11892	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	539	0	0
T1	14725	3	0	0
T2	17278	1	0	0
T3	18805	2	0	0
T7	9756	2	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	3	0	0
T13	0	1	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T28	0	1	0	0
T42	0	1	0	0
T43	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	455	0	0
T1	14725	3	0	0
T2	17278	1	0	0
T3	18805	2	0	0
T7	9756	2	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T42	0	1	0	0
T43	0	8	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	405	0	0
T1	14725	3	0	0
T2	17278	1	0	0
T3	18805	2	0	0
T7	9756	2	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	1	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T42	0	1	0	0
T43	0	8	0	0
T59	0	1	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	405	0	0
T1	14725	3	0	0
T2	17278	1	0	0
T3	18805	2	0	0
T7	9756	2	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	1	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T42	0	1	0	0
T43	0	8	0	0
T59	0	1	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	17596	0	0
T1	14725	42	0	0
T2	17278	64	0	0
T3	18805	42	0	0
T7	9756	17	0	0
T8	14317	77	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T42	0	2	0	0
T43	0	133	0	0
T59	0	2	0	0
T114	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	359	0	0
T1	14725	3	0	0
T2	17278	1	0	0
T3	18805	2	0	0
T7	9756	2	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T12	0	1	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T42	0	1	0	0
T43	0	8	0	0
T59	0	1	0	0
T114	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T27,T29
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T29
0	1	Covered	T27,T70,T71
1	0	Covered	T27,T70,T222

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T29,T39
0	1	Covered	T8,T29,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T29,T39
1	-	Covered	T8,T29,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T29
DetectSt	168	Covered	T8,T27,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T29,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T27,T29
DebounceSt->IdleSt	163	Covered	T220,T221,T74
DetectSt->IdleSt	186	Covered	T27,T70,T71
DetectSt->StableSt	191	Covered	T8,T29,T39
IdleSt->DebounceSt	148	Covered	T8,T27,T29
StableSt->IdleSt	206	Covered	T8,T29,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T27,T29
0	1	Covered	T8,T27,T29
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T27,T29
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T29
IdleSt	0	-	-	-	-	-	-	Covered	T8,T27,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T27,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T220,T221,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T29
DetectSt	-	-	-	-	1	-	-	Covered	T27,T70,T71
DetectSt	-	-	-	-	0	1	-	Covered	T8,T29,T39
DetectSt	-	-	-	-	0	0	-	Covered	T8,T27,T29
StableSt	-	-	-	-	-	-	1	Covered	T8,T29,T39
StableSt	-	-	-	-	-	-	0	Covered	T8,T29,T39
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	2945	0	0
CntIncr_A	5638357	94289	0	0
CntNoWrap_A	5638357	4999099	0	0
DetectStDropOut_A	5638357	394	0	0
DetectedOut_A	5638357	80017	0	0
DetectedPulseOut_A	5638357	804	0	0
DisabledIdleSt_A	5638357	4571272	0	0
DisabledNoDetection_A	5638357	4573399	0	0
EnterDebounceSt_A	5638357	1489	0	0
EnterDetectSt_A	5638357	1457	0	0
EnterStableSt_A	5638357	804	0	0
PulseIsPulse_A	5638357	804	0	0
StayInStableSt	5638357	79080	0	0
gen_high_event_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	671	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2945	0	0
T8	14317	46	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	28	0	0
T29	0	50	0	0
T39	0	8	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	18	0	0
T66	0	22	0	0
T67	0	44	0	0
T68	0	22	0	0
T70	0	58	0	0
T71	0	40	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	94289	0	0
T8	14317	2070	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	752	0	0
T29	0	2000	0	0
T39	0	252	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	432	0	0
T66	0	682	0	0
T67	0	1276	0	0
T68	0	737	0	0
T70	0	1790	0	0
T71	0	1140	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4999099	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13861	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	394	0	0
T25	2457	0	0	0
T27	12059	9	0	0
T28	461	0	0	0
T41	6388	0	0	0
T42	149782	0	0	0
T43	25544	0	0	0
T63	504	0	0	0
T70	0	13	0	0
T71	0	20	0	0
T88	0	5	0	0
T89	0	28	0	0
T90	0	7	0	0
T91	0	5	0	0
T104	526	0	0	0
T105	431	0	0	0
T106	523	0	0	0
T222	0	10	0	0
T225	0	8	0	0
T226	0	15	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	80017	0	0
T8	14317	1696	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T29	0	3450	0	0
T39	0	1546	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	737	0	0
T66	0	1244	0	0
T67	0	4005	0	0
T68	0	972	0	0
T155	0	2384	0	0
T223	0	1585	0	0
T224	0	91	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	804	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T29	0	25	0	0
T39	0	4	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	9	0	0
T66	0	11	0	0
T67	0	22	0	0
T68	0	11	0	0
T155	0	11	0	0
T223	0	14	0	0
T224	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4571272	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	6869	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4573399	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	6869	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1489	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	14	0	0
T29	0	25	0	0
T39	0	4	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	9	0	0
T66	0	11	0	0
T67	0	22	0	0
T68	0	11	0	0
T70	0	29	0	0
T71	0	20	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1457	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	14	0	0
T29	0	25	0	0
T39	0	4	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	9	0	0
T66	0	11	0	0
T67	0	22	0	0
T68	0	11	0	0
T70	0	29	0	0
T71	0	20	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	804	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T29	0	25	0	0
T39	0	4	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	9	0	0
T66	0	11	0	0
T67	0	22	0	0
T68	0	11	0	0
T155	0	11	0	0
T223	0	14	0	0
T224	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	804	0	0
T8	14317	23	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T29	0	25	0	0
T39	0	4	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	9	0	0
T66	0	11	0	0
T67	0	22	0	0
T68	0	11	0	0
T155	0	11	0	0
T223	0	14	0	0
T224	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	79080	0	0
T8	14317	1671	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T29	0	3421	0	0
T39	0	1539	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	727	0	0
T66	0	1230	0	0
T67	0	3975	0	0
T68	0	959	0	0
T155	0	2367	0	0
T223	0	1567	0	0
T224	0	85	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	671	0	0
T8	14317	21	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T29	0	21	0	0
T39	0	1	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	8	0	0
T66	0	8	0	0
T67	0	14	0	0
T68	0	9	0	0
T155	0	5	0	0
T223	0	10	0	0
T224	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T45,T227,T228
1	0	Covered	T74,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T74,T229

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T45,T60
DetectSt->IdleSt	186	Covered	T45,T227,T228
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T45,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T45,T227,T228
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	962	0	0
CntIncr_A	5638357	53331	0	0
CntNoWrap_A	5638357	5001082	0	0
DetectStDropOut_A	5638357	77	0	0
DetectedOut_A	5638357	19565	0	0
DetectedPulseOut_A	5638357	380	0	0
DisabledIdleSt_A	5638357	4617108	0	0
DisabledNoDetection_A	5638357	4618737	0	0
EnterDebounceSt_A	5638357	501	0	0
EnterDetectSt_A	5638357	461	0	0
EnterStableSt_A	5638357	380	0	0
PulseIsPulse_A	5638357	380	0	0
StayInStableSt	5638357	19146	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	338	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	962	0	0
T1	14725	8	0	0
T2	17278	12	0	0
T3	18805	12	0	0
T7	9756	2	0	0
T8	14317	4	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	12	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	7	0	0
T43	0	4	0	0
T45	0	11	0	0
T60	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	53331	0	0
T1	14725	584	0	0
T2	17278	1054	0	0
T3	18805	840	0	0
T7	9756	162	0	0
T8	14317	148	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	342	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	362	0	0
T43	0	196	0	0
T45	0	1227	0	0
T60	0	548	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001082	0	0
T1	14725	14288	0	0
T2	17278	16828	0	0
T3	18805	18351	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4512	0	0
T8	14317	13903	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	77	0	0
T29	28701	0	0	0
T37	794	0	0	0
T45	31832	5	0	0
T55	2741	0	0	0
T60	16048	0	0	0
T97	0	9	0	0
T162	524	0	0	0
T163	402	0	0	0
T164	522	0	0	0
T165	422	0	0	0
T166	429	0	0	0
T227	0	5	0	0
T228	0	3	0	0
T230	0	3	0	0
T231	0	12	0	0
T232	0	4	0	0
T233	0	11	0	0
T234	0	3	0	0
T235	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	19565	0	0
T1	14725	31	0	0
T2	17278	25	0	0
T3	18805	81	0	0
T7	9756	41	0	0
T8	14317	158	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	161	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	168	0	0
T39	0	961	0	0
T43	0	17	0	0
T60	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	380	0	0
T1	14725	4	0	0
T2	17278	5	0	0
T3	18805	6	0	0
T7	9756	1	0	0
T8	14317	2	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	6	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T39	0	3	0	0
T43	0	2	0	0
T60	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4617108	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	3908	0	0
T8	14317	12213	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4618737	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	3922	0	0
T8	14317	12214	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	501	0	0
T1	14725	4	0	0
T2	17278	7	0	0
T3	18805	6	0	0
T7	9756	1	0	0
T8	14317	2	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	6	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	4	0	0
T43	0	2	0	0
T45	0	6	0	0
T60	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	461	0	0
T1	14725	4	0	0
T2	17278	5	0	0
T3	18805	6	0	0
T7	9756	1	0	0
T8	14317	2	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	6	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T43	0	2	0	0
T45	0	5	0	0
T60	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	380	0	0
T1	14725	4	0	0
T2	17278	5	0	0
T3	18805	6	0	0
T7	9756	1	0	0
T8	14317	2	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	6	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T39	0	3	0	0
T43	0	2	0	0
T60	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	380	0	0
T1	14725	4	0	0
T2	17278	5	0	0
T3	18805	6	0	0
T7	9756	1	0	0
T8	14317	2	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	6	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T39	0	3	0	0
T43	0	2	0	0
T60	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	19146	0	0
T1	14725	27	0	0
T2	17278	20	0	0
T3	18805	75	0	0
T7	9756	40	0	0
T8	14317	155	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	155	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	165	0	0
T39	0	958	0	0
T43	0	15	0	0
T60	0	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	338	0	0
T1	14725	4	0	0
T2	17278	5	0	0
T3	18805	6	0	0
T7	9756	1	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	6	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T39	0	3	0	0
T43	0	2	0	0
T60	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T27,T29
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T29
0	1	Covered	T39,T70,T71
1	0	Covered	T39,T65,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T29
0	1	Covered	T8,T27,T29
1	0	Covered	T74,T80,T54

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T27,T29
1	-	Covered	T8,T27,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T29
DetectSt	168	Covered	T8,T27,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T27,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T27,T29
DebounceSt->IdleSt	163	Covered	T220,T221,T74
DetectSt->IdleSt	186	Covered	T39,T65,T70
DetectSt->StableSt	191	Covered	T8,T27,T29
IdleSt->DebounceSt	148	Covered	T8,T27,T29
StableSt->IdleSt	206	Covered	T8,T27,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T27,T29
0	1	Covered	T8,T27,T29
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T27,T29
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T29
IdleSt	0	-	-	-	-	-	-	Covered	T8,T27,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T27,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T220,T221,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T29
DetectSt	-	-	-	-	1	-	-	Covered	T39,T65,T70
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T29
DetectSt	-	-	-	-	0	0	-	Covered	T8,T27,T29
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T29
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	3076	0	0
CntIncr_A	5638357	98221	0	0
CntNoWrap_A	5638357	4998968	0	0
DetectStDropOut_A	5638357	447	0	0
DetectedOut_A	5638357	65057	0	0
DetectedPulseOut_A	5638357	865	0	0
DisabledIdleSt_A	5638357	4584830	0	0
DisabledNoDetection_A	5638357	4586971	0	0
EnterDebounceSt_A	5638357	1552	0	0
EnterDetectSt_A	5638357	1524	0	0
EnterStableSt_A	5638357	865	0	0
PulseIsPulse_A	5638357	865	0	0
StayInStableSt	5638357	64075	0	0
gen_high_event_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	738	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	3076	0	0
T8	14317	24	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	6	0	0
T29	0	50	0	0
T39	0	40	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	10	0	0
T66	0	60	0	0
T67	0	14	0	0
T68	0	46	0	0
T70	0	58	0	0
T71	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	98221	0	0
T8	14317	780	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	159	0	0
T29	0	2075	0	0
T39	0	1282	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	318	0	0
T66	0	2580	0	0
T67	0	630	0	0
T68	0	1794	0	0
T70	0	1776	0	0
T71	0	1199	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4998968	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13883	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	447	0	0
T38	655	0	0	0
T39	13435	16	0	0
T64	539	0	0	0
T65	9508	0	0	0
T70	0	20	0	0
T71	0	21	0	0
T72	2107	0	0	0
T88	0	4	0	0
T89	0	16	0	0
T90	0	11	0	0
T127	422	0	0	0
T128	673	0	0	0
T129	23978	0	0	0
T220	0	2	0	0
T225	0	12	0	0
T236	0	10	0	0
T237	0	26	0	0
T238	406	0	0	0
T239	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	65057	0	0
T8	14317	764	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	12	0	0
T29	0	3375	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	2802	0	0
T67	0	1098	0	0
T68	0	1752	0	0
T91	0	1891	0	0
T155	0	706	0	0
T222	0	1533	0	0
T223	0	3656	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	865	0	0
T8	14317	12	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	25	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	30	0	0
T67	0	7	0	0
T68	0	23	0	0
T91	0	15	0	0
T155	0	9	0	0
T222	0	13	0	0
T223	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4584830	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	7847	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4586971	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	7849	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1552	0	0
T8	14317	12	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	25	0	0
T39	0	20	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	5	0	0
T66	0	30	0	0
T67	0	7	0	0
T68	0	23	0	0
T70	0	29	0	0
T71	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1524	0	0
T8	14317	12	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	25	0	0
T39	0	20	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	5	0	0
T66	0	30	0	0
T67	0	7	0	0
T68	0	23	0	0
T70	0	29	0	0
T71	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	865	0	0
T8	14317	12	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	25	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	30	0	0
T67	0	7	0	0
T68	0	23	0	0
T91	0	15	0	0
T155	0	9	0	0
T222	0	13	0	0
T223	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	865	0	0
T8	14317	12	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	25	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	30	0	0
T67	0	7	0	0
T68	0	23	0	0
T91	0	15	0	0
T155	0	9	0	0
T222	0	13	0	0
T223	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	64075	0	0
T8	14317	752	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	9	0	0
T29	0	3346	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	2765	0	0
T67	0	1087	0	0
T68	0	1726	0	0
T91	0	1872	0	0
T155	0	694	0	0
T222	0	1520	0	0
T223	0	3617	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	738	0	0
T8	14317	12	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	21	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T66	0	22	0	0
T67	0	3	0	0
T68	0	20	0	0
T91	0	11	0	0
T155	0	6	0	0
T222	0	13	0	0
T223	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T43,T143,T190
1	0	Covered	T74,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T45,T129
DetectSt->IdleSt	186	Covered	T43,T143,T190
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T45,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T43,T143,T190
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	872	0	0
CntIncr_A	5638357	49948	0	0
CntNoWrap_A	5638357	5001172	0	0
DetectStDropOut_A	5638357	78	0	0
DetectedOut_A	5638357	14896	0	0
DetectedPulseOut_A	5638357	330	0	0
DisabledIdleSt_A	5638357	4633615	0	0
DisabledNoDetection_A	5638357	4635269	0	0
EnterDebounceSt_A	5638357	462	0	0
EnterDetectSt_A	5638357	413	0	0
EnterStableSt_A	5638357	330	0	0
PulseIsPulse_A	5638357	330	0	0
StayInStableSt	5638357	14526	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	290	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	872	0	0
T1	14725	4	0	0
T2	17278	23	0	0
T3	18805	16	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	4	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	6	0	0
T43	0	2	0	0
T45	0	15	0	0
T66	0	8	0	0
T129	0	23	0	0
T240	0	19	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	49948	0	0
T1	14725	182	0	0
T2	17278	1166	0	0
T3	18805	656	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	122	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	195	0	0
T43	0	105	0	0
T45	0	1218	0	0
T66	0	336	0	0
T129	0	827	0	0
T240	0	1049	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001172	0	0
T1	14725	14292	0	0
T2	17278	16817	0	0
T3	18805	18347	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13907	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	78	0	0
T28	461	0	0	0
T43	25544	1	0	0
T44	51522	0	0	0
T58	496	0	0	0
T59	3107	0	0	0
T94	0	6	0	0
T99	0	6	0	0
T106	523	0	0	0
T114	493	0	0	0
T123	404	0	0	0
T124	615	0	0	0
T143	0	8	0	0
T186	0	1	0	0
T190	0	1	0	0
T227	0	11	0	0
T228	0	3	0	0
T241	0	4	0	0
T242	0	1	0	0
T243	439	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	14896	0	0
T1	14725	126	0	0
T2	17278	914	0	0
T3	18805	577	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	45	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	284	0	0
T45	0	449	0	0
T66	0	126	0	0
T129	0	387	0	0
T240	0	836	0	0
T244	0	25	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	330	0	0
T1	14725	2	0	0
T2	17278	10	0	0
T3	18805	8	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T45	0	7	0	0
T66	0	4	0	0
T129	0	10	0	0
T240	0	9	0	0
T244	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4633615	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	3908	0	0
T8	14317	13143	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4635269	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	3922	0	0
T8	14317	13146	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	462	0	0
T1	14725	2	0	0
T2	17278	13	0	0
T3	18805	8	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T43	0	1	0	0
T45	0	8	0	0
T66	0	4	0	0
T129	0	13	0	0
T240	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	413	0	0
T1	14725	2	0	0
T2	17278	10	0	0
T3	18805	8	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T43	0	1	0	0
T45	0	7	0	0
T66	0	4	0	0
T129	0	10	0	0
T240	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	330	0	0
T1	14725	2	0	0
T2	17278	10	0	0
T3	18805	8	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T45	0	7	0	0
T66	0	4	0	0
T129	0	10	0	0
T240	0	9	0	0
T244	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	330	0	0
T1	14725	2	0	0
T2	17278	10	0	0
T3	18805	8	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	3	0	0
T45	0	7	0	0
T66	0	4	0	0
T129	0	10	0	0
T240	0	9	0	0
T244	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	14526	0	0
T1	14725	124	0	0
T2	17278	904	0	0
T3	18805	569	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	43	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T29	0	278	0	0
T45	0	442	0	0
T66	0	118	0	0
T129	0	377	0	0
T240	0	827	0	0
T244	0	21	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	290	0	0
T1	14725	2	0	0
T2	17278	10	0	0
T3	18805	8	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	2	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T45	0	7	0	0
T129	0	10	0	0
T240	0	9	0	0
T244	0	4	0	0
T245	0	1	0	0
T246	0	1	0	0