Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T8,T27,T29
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T27,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T27,T29
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T29
0	1	Covered	T39,T70,T71
1	0	Covered	T39,T70,T222

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T27,T29
0	1	Covered	T8,T27,T29
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T27,T29
1	-	Covered	T8,T27,T29

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T27,T29
DetectSt	168	Covered	T8,T27,T29
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T27,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T27,T29
DebounceSt->IdleSt	163	Covered	T220,T221,T74
DetectSt->IdleSt	186	Covered	T39,T70,T71
DetectSt->StableSt	191	Covered	T8,T27,T29
IdleSt->DebounceSt	148	Covered	T8,T27,T29
StableSt->IdleSt	206	Covered	T8,T27,T29

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T27,T29
0	1	Covered	T8,T27,T29
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T27,T29
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T8,T27,T29
IdleSt	0	-	-	-	-	-	-	Covered	T8,T27,T29
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T27,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T220,T221,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T27,T29
DetectSt	-	-	-	-	1	-	-	Covered	T39,T70,T71
DetectSt	-	-	-	-	0	1	-	Covered	T8,T27,T29
DetectSt	-	-	-	-	0	0	-	Covered	T8,T27,T29
StableSt	-	-	-	-	-	-	1	Covered	T8,T27,T29
StableSt	-	-	-	-	-	-	0	Covered	T8,T27,T29
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	2563	0	0
CntIncr_A	5638357	78752	0	0
CntNoWrap_A	5638357	4999481	0	0
DetectStDropOut_A	5638357	330	0	0
DetectedOut_A	5638357	66493	0	0
DetectedPulseOut_A	5638357	738	0	0
DisabledIdleSt_A	5638357	4583590	0	0
DisabledNoDetection_A	5638357	4585733	0	0
EnterDebounceSt_A	5638357	1295	0	0
EnterDetectSt_A	5638357	1268	0	0
EnterStableSt_A	5638357	738	0	0
PulseIsPulse_A	5638357	738	0	0
StayInStableSt	5638357	65639	0	0
gen_high_event_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	622	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	2563	0	0
T8	14317	54	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	14	0	0
T29	0	20	0	0
T39	0	26	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	56	0	0
T66	0	36	0	0
T67	0	44	0	0
T68	0	46	0	0
T70	0	58	0	0
T71	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	78752	0	0
T8	14317	2511	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	329	0	0
T29	0	810	0	0
T39	0	825	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	1456	0	0
T66	0	1548	0	0
T67	0	1452	0	0
T68	0	1587	0	0
T70	0	1790	0	0
T71	0	224	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4999481	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13853	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	330	0	0
T38	655	0	0	0
T39	13435	12	0	0
T64	539	0	0	0
T65	9508	0	0	0
T70	0	13	0	0
T71	0	4	0	0
T72	2107	0	0	0
T89	0	28	0	0
T90	0	5	0	0
T127	422	0	0	0
T128	673	0	0	0
T129	23978	0	0	0
T222	0	10	0	0
T225	0	12	0	0
T226	0	15	0	0
T236	0	16	0	0
T237	0	8	0	0
T238	406	0	0	0
T239	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	66493	0	0
T8	14317	2188	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	705	0	0
T29	0	1920	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	1984	0	0
T66	0	1567	0	0
T67	0	3829	0	0
T68	0	2866	0	0
T88	0	1824	0	0
T91	0	2188	0	0
T223	0	1473	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	738	0	0
T8	14317	27	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	7	0	0
T29	0	10	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	28	0	0
T66	0	18	0	0
T67	0	22	0	0
T68	0	23	0	0
T88	0	10	0	0
T91	0	23	0	0
T223	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4583590	0	0
T1	14725	14296	0	0
T2	17278	16840	0	0
T3	18805	18363	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	6383	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4585733	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	6384	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1295	0	0
T8	14317	27	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	7	0	0
T29	0	10	0	0
T39	0	13	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	28	0	0
T66	0	18	0	0
T67	0	22	0	0
T68	0	23	0	0
T70	0	29	0	0
T71	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	1268	0	0
T8	14317	27	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	7	0	0
T29	0	10	0	0
T39	0	13	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	28	0	0
T66	0	18	0	0
T67	0	22	0	0
T68	0	23	0	0
T70	0	29	0	0
T71	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	738	0	0
T8	14317	27	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	7	0	0
T29	0	10	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	28	0	0
T66	0	18	0	0
T67	0	22	0	0
T68	0	23	0	0
T88	0	10	0	0
T91	0	23	0	0
T223	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	738	0	0
T8	14317	27	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	7	0	0
T29	0	10	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	28	0	0
T66	0	18	0	0
T67	0	22	0	0
T68	0	23	0	0
T88	0	10	0	0
T91	0	23	0	0
T223	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	65639	0	0
T8	14317	2160	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	695	0	0
T29	0	1909	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	1955	0	0
T66	0	1545	0	0
T67	0	3799	0	0
T68	0	2839	0	0
T88	0	1807	0	0
T91	0	2158	0	0
T223	0	1455	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	622	0	0
T8	14317	26	0	0
T9	8766	0	0	0
T10	626	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	4	0	0
T29	0	9	0	0
T50	438	0	0	0
T51	822	0	0	0
T52	405	0	0	0
T65	0	27	0	0
T66	0	14	0	0
T67	0	14	0	0
T68	0	19	0	0
T88	0	3	0	0
T91	0	16	0	0
T223	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T228
1	0	Covered	T74,T54

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T13
0	1	Covered	T2,T8,T13
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T8,T13
1	-	Covered	T2,T8,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T8,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T129,T240,T244
DetectSt->IdleSt	186	Covered	T1,T3,T228
DetectSt->StableSt	191	Covered	T2,T8,T13
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T2,T8,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T54
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T129,T240,T244
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T1,T3,T228
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T13
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T8,T13
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5638357	893	0	0
CntIncr_A	5638357	49535	0	0
CntNoWrap_A	5638357	5001151	0	0
DetectStDropOut_A	5638357	58	0	0
DetectedOut_A	5638357	18221	0	0
DetectedPulseOut_A	5638357	367	0	0
DisabledIdleSt_A	5638357	4636912	0	0
DisabledNoDetection_A	5638357	4638575	0	0
EnterDebounceSt_A	5638357	464	0	0
EnterDetectSt_A	5638357	430	0	0
EnterStableSt_A	5638357	367	0	0
PulseIsPulse_A	5638357	367	0	0
StayInStableSt	5638357	17819	0	0
gen_high_level_sva.HighLevelEvent_A	5638357	5004394	0	0
gen_not_sticky_sva.StableStDropOut_A	5638357	327	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	893	0	0
T1	14725	4	0	0
T2	17278	6	0	0
T3	18805	4	0	0
T7	9756	0	0	0
T8	14317	2	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	10	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T27	0	6	0	0
T29	0	2	0	0
T43	0	2	0	0
T45	0	10	0	0
T60	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	49535	0	0
T1	14725	306	0	0
T2	17278	531	0	0
T3	18805	306	0	0
T7	9756	0	0	0
T8	14317	101	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	375	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T27	0	192	0	0
T29	0	66	0	0
T43	0	87	0	0
T45	0	1030	0	0
T60	0	280	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5001151	0	0
T1	14725	14292	0	0
T2	17278	16834	0	0
T3	18805	18359	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	4514	0	0
T8	14317	13905	0	0
T14	454	53	0	0
T17	611	210	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	58	0	0
T1	14725	2	0	0
T2	17278	0	0	0
T3	18805	2	0	0
T7	9756	0	0	0
T8	14317	0	0	0
T9	8766	0	0	0
T10	626	0	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T98	0	13	0	0
T99	0	1	0	0
T203	0	7	0	0
T228	0	9	0	0
T231	0	12	0	0
T247	0	2	0	0
T248	0	5	0	0
T249	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	18221	0	0
T2	17278	16	0	0
T3	18805	0	0	0
T7	9756	0	0	0
T8	14317	52	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	43	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	167	0	0
T29	0	94	0	0
T34	0	4	0	0
T43	0	18	0	0
T45	0	63	0	0
T60	0	263	0	0
T65	0	317	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	367	0	0
T2	17278	3	0	0
T3	18805	0	0	0
T7	9756	0	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	5	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	1	0	0
T34	0	1	0	0
T43	0	1	0	0
T45	0	5	0	0
T60	0	4	0	0
T65	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4636912	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	101	0	0
T5	521	120	0	0
T6	422	21	0	0
T7	9756	3908	0	0
T8	14317	11720	0	0
T14	454	53	0	0
T17	611	210	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	4638575	0	0
T1	14725	10072	0	0
T2	17278	12087	0	0
T3	18805	14101	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	3922	0	0
T8	14317	11722	0	0
T14	454	54	0	0
T17	611	211	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	464	0	0
T1	14725	2	0	0
T2	17278	3	0	0
T3	18805	2	0	0
T7	9756	0	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	5	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T27	0	3	0	0
T29	0	1	0	0
T43	0	1	0	0
T45	0	5	0	0
T60	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	430	0	0
T1	14725	2	0	0
T2	17278	3	0	0
T3	18805	2	0	0
T7	9756	0	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	5	0	0
T14	454	0	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T27	0	3	0	0
T29	0	1	0	0
T43	0	1	0	0
T45	0	5	0	0
T60	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	367	0	0
T2	17278	3	0	0
T3	18805	0	0	0
T7	9756	0	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	5	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	1	0	0
T34	0	1	0	0
T43	0	1	0	0
T45	0	5	0	0
T60	0	4	0	0
T65	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	367	0	0
T2	17278	3	0	0
T3	18805	0	0	0
T7	9756	0	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	5	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	1	0	0
T34	0	1	0	0
T43	0	1	0	0
T45	0	5	0	0
T60	0	4	0	0
T65	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	17819	0	0
T2	17278	13	0	0
T3	18805	0	0	0
T7	9756	0	0	0
T8	14317	51	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	38	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	164	0	0
T29	0	93	0	0
T34	0	3	0	0
T43	0	17	0	0
T45	0	58	0	0
T60	0	259	0	0
T65	0	312	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	5004394	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5638357	327	0	0
T2	17278	3	0	0
T3	18805	0	0	0
T7	9756	0	0	0
T8	14317	1	0	0
T9	8766	0	0	0
T10	626	0	0	0
T13	0	5	0	0
T15	2127	0	0	0
T16	58324	0	0	0
T23	495	0	0	0
T26	682	0	0	0
T27	0	3	0	0
T29	0	1	0	0
T34	0	1	0	0
T43	0	1	0	0
T45	0	5	0	0
T60	0	4	0	0
T65	0	3	0	0