Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1101728147	13160	0	0
auto_block_debounce_ctl_rd_A	1101728147	1755	0	0
auto_block_out_ctl_rd_A	1101728147	2219	0	0
com_det_ctl_0_rd_A	1101728147	3520	0	0
com_det_ctl_1_rd_A	1101728147	3419	0	0
com_det_ctl_2_rd_A	1101728147	3625	0	0
com_det_ctl_3_rd_A	1101728147	3425	0	0
com_out_ctl_0_rd_A	1101728147	3894	0	0
com_out_ctl_1_rd_A	1101728147	3799	0	0
com_out_ctl_2_rd_A	1101728147	3871	0	0
com_out_ctl_3_rd_A	1101728147	4029	0	0
com_pre_det_ctl_0_rd_A	1101728147	1418	0	0
com_pre_det_ctl_1_rd_A	1101728147	1420	0	0
com_pre_det_ctl_2_rd_A	1101728147	1436	0	0
com_pre_det_ctl_3_rd_A	1101728147	1481	0	0
com_pre_sel_ctl_0_rd_A	1101728147	4138	0	0
com_pre_sel_ctl_1_rd_A	1101728147	3714	0	0
com_pre_sel_ctl_2_rd_A	1101728147	3802	0	0
com_pre_sel_ctl_3_rd_A	1101728147	3905	0	0
com_sel_ctl_0_rd_A	1101728147	4032	0	0
com_sel_ctl_1_rd_A	1101728147	3967	0	0
com_sel_ctl_2_rd_A	1101728147	3934	0	0
com_sel_ctl_3_rd_A	1101728147	4074	0	0
ec_rst_ctl_rd_A	1101728147	2302	0	0
intr_enable_rd_A	1101728147	2140	0	0
key_intr_ctl_rd_A	1101728147	3012	0	0
key_intr_debounce_ctl_rd_A	1101728147	1471	0	0
key_invert_ctl_rd_A	1101728147	4469	0	0
pin_allowed_ctl_rd_A	1101728147	4821	0	0
pin_out_ctl_rd_A	1101728147	4337	0	0
pin_out_value_rd_A	1101728147	4500	0	0
regwen_rd_A	1101728147	1796	0	0
ulp_ac_debounce_ctl_rd_A	1101728147	1590	0	0
ulp_ctl_rd_A	1101728147	1591	0	0
ulp_lid_debounce_ctl_rd_A	1101728147	1602	0	0
ulp_pwrb_debounce_ctl_rd_A	1101728147	1593	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	13160	0	0
T7	112636	2	0	0
T8	171804	0	0	0
T9	357044	19	0	0
T10	13806	0	0	0
T12	0	6	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T34	0	16	0	0
T41	0	7	0	0
T46	0	10	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T59	0	5	0	0
T82	0	3	0	0
T134	0	16	0	0
T143	0	7	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1755	0	0
T70	638057	0	0	0
T71	520984	0	0	0
T85	0	9	0	0
T86	0	4	0	0
T87	139867	8	0	0
T88	103358	0	0	0
T89	674627	0	0	0
T112	0	38	0	0
T132	0	21	0	0
T186	0	40	0	0
T195	0	3	0	0
T222	487712	0	0	0
T267	0	12	0	0
T268	0	6	0	0
T269	0	15	0	0
T270	51160	0	0	0
T271	193118	0	0	0
T272	238075	0	0	0
T273	253615	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2219	0	0
T70	638057	0	0	0
T71	520984	0	0	0
T85	0	12	0	0
T87	139867	8	0	0
T88	103358	0	0	0
T89	674627	0	0	0
T112	0	16	0	0
T132	0	21	0	0
T186	0	34	0	0
T222	487712	0	0	0
T267	0	15	0	0
T268	0	4	0	0
T269	0	16	0	0
T270	51160	0	0	0
T271	193118	0	0	0
T272	238075	0	0	0
T273	253615	0	0	0
T274	0	1	0	0
T275	0	14	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3520	0	0
T1	176695	62	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	72	0	0
T65	0	36	0	0
T88	0	39	0	0
T91	0	43	0	0
T129	0	69	0	0
T195	0	3	0	0
T223	0	96	0	0
T244	0	74	0	0
T245	0	82	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3419	0	0
T1	176695	80	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	78	0	0
T65	0	24	0	0
T88	0	58	0	0
T91	0	43	0	0
T129	0	56	0	0
T195	0	5	0	0
T223	0	100	0	0
T244	0	77	0	0
T245	0	81	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3625	0	0
T1	176695	68	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	86	0	0
T65	0	36	0	0
T88	0	51	0	0
T91	0	37	0	0
T129	0	67	0	0
T195	0	5	0	0
T223	0	88	0	0
T244	0	57	0	0
T245	0	69	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3425	0	0
T1	176695	49	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	66	0	0
T65	0	19	0	0
T88	0	63	0	0
T91	0	31	0	0
T129	0	70	0	0
T195	0	6	0	0
T223	0	97	0	0
T244	0	73	0	0
T245	0	71	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3894	0	0
T1	176695	74	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	87	0	0
T65	0	14	0	0
T88	0	44	0	0
T91	0	46	0	0
T129	0	62	0	0
T195	0	12	0	0
T223	0	97	0	0
T244	0	55	0	0
T245	0	68	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3799	0	0
T1	176695	94	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	60	0	0
T65	0	42	0	0
T88	0	55	0	0
T91	0	44	0	0
T129	0	62	0	0
T195	0	3	0	0
T223	0	101	0	0
T244	0	55	0	0
T245	0	64	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3871	0	0
T1	176695	81	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	57	0	0
T65	0	1	0	0
T88	0	72	0	0
T91	0	33	0	0
T129	0	66	0	0
T195	0	4	0	0
T223	0	106	0	0
T244	0	60	0	0
T245	0	56	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4029	0	0
T1	176695	59	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	88	0	0
T65	0	12	0	0
T88	0	46	0	0
T91	0	33	0	0
T129	0	52	0	0
T195	0	17	0	0
T223	0	102	0	0
T244	0	83	0	0
T245	0	62	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1418	0	0
T30	0	4	0	0
T31	0	12	0	0
T78	69210	0	0	0
T92	748706	0	0	0
T112	0	35	0	0
T121	0	18	0	0
T132	0	14	0	0
T161	0	2	0	0
T186	0	10	0	0
T195	695800	11	0	0
T196	118442	0	0	0
T197	399250	0	0	0
T218	0	31	0	0
T276	0	34	0	0
T277	176622	0	0	0
T278	125935	0	0	0
T279	202615	0	0	0
T280	30293	0	0	0
T281	248204	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1420	0	0
T30	0	5	0	0
T78	69210	0	0	0
T92	748706	0	0	0
T112	0	23	0	0
T121	0	34	0	0
T132	0	26	0	0
T161	0	4	0	0
T186	0	16	0	0
T195	695800	12	0	0
T196	118442	0	0	0
T197	399250	0	0	0
T218	0	14	0	0
T250	0	7	0	0
T276	0	18	0	0
T277	176622	0	0	0
T278	125935	0	0	0
T279	202615	0	0	0
T280	30293	0	0	0
T281	248204	0	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1436	0	0
T30	0	6	0	0
T78	69210	0	0	0
T92	748706	0	0	0
T112	0	29	0	0
T121	0	18	0	0
T132	0	12	0	0
T161	0	7	0	0
T186	0	21	0	0
T195	695800	15	0	0
T196	118442	0	0	0
T197	399250	0	0	0
T218	0	27	0	0
T250	0	3	0	0
T276	0	24	0	0
T277	176622	0	0	0
T278	125935	0	0	0
T279	202615	0	0	0
T280	30293	0	0	0
T281	248204	0	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1481	0	0
T30	0	10	0	0
T31	0	7	0	0
T78	69210	0	0	0
T92	748706	0	0	0
T112	0	35	0	0
T121	0	18	0	0
T132	0	23	0	0
T161	0	2	0	0
T186	0	25	0	0
T195	695800	5	0	0
T196	118442	0	0	0
T197	399250	0	0	0
T218	0	36	0	0
T276	0	14	0	0
T277	176622	0	0	0
T278	125935	0	0	0
T279	202615	0	0	0
T280	30293	0	0	0
T281	248204	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4138	0	0
T1	176695	37	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	52	0	0
T65	0	12	0	0
T88	0	51	0	0
T91	0	55	0	0
T129	0	100	0	0
T195	0	2	0	0
T223	0	85	0	0
T244	0	64	0	0
T245	0	92	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3714	0	0
T1	176695	88	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	59	0	0
T65	0	29	0	0
T88	0	71	0	0
T91	0	37	0	0
T129	0	68	0	0
T195	0	9	0	0
T223	0	93	0	0
T244	0	74	0	0
T245	0	67	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3802	0	0
T1	176695	59	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	62	0	0
T65	0	17	0	0
T88	0	58	0	0
T91	0	22	0	0
T129	0	103	0	0
T195	0	4	0	0
T223	0	78	0	0
T244	0	73	0	0
T245	0	73	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3905	0	0
T1	176695	54	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	64	0	0
T65	0	34	0	0
T88	0	61	0	0
T91	0	39	0	0
T129	0	76	0	0
T195	0	7	0	0
T223	0	98	0	0
T244	0	64	0	0
T245	0	53	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4032	0	0
T1	176695	74	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	77	0	0
T65	0	11	0	0
T88	0	64	0	0
T91	0	32	0	0
T129	0	63	0	0
T195	0	8	0	0
T223	0	99	0	0
T244	0	58	0	0
T245	0	68	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3967	0	0
T1	176695	75	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	82	0	0
T65	0	24	0	0
T88	0	69	0	0
T91	0	49	0	0
T129	0	59	0	0
T195	0	16	0	0
T223	0	92	0	0
T244	0	50	0	0
T245	0	65	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3934	0	0
T1	176695	70	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	74	0	0
T65	0	19	0	0
T88	0	38	0	0
T91	0	59	0	0
T129	0	73	0	0
T195	0	2	0	0
T223	0	98	0	0
T244	0	75	0	0
T245	0	91	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4074	0	0
T1	176695	65	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	72	0	0
T65	0	24	0	0
T88	0	64	0	0
T91	0	40	0	0
T129	0	59	0	0
T195	0	7	0	0
T223	0	110	0	0
T244	0	78	0	0
T245	0	87	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2302	0	0
T1	176695	22	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T43	0	19	0	0
T65	0	7	0	0
T71	0	2	0	0
T88	0	26	0	0
T124	0	2	0	0
T129	0	37	0	0
T244	0	45	0	0
T245	0	6	0	0
T282	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2140	0	0
T82	664795	0	0	0
T83	0	8	0	0
T91	308175	0	0	0
T112	0	72	0	0
T121	0	72	0	0
T130	215074	0	0	0
T132	0	31	0	0
T186	0	40	0	0
T190	508644	0	0	0
T191	44878	0	0	0
T195	0	14	0	0
T211	33476	0	0	0
T218	0	34	0	0
T276	0	53	0	0
T283	169060	17	0	0
T284	0	12	0	0
T285	203787	0	0	0
T286	125769	0	0	0
T287	240295	0	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	3012	0	0
T10	13806	10	0	0
T11	116178	0	0	0
T12	116665	0	0	0
T23	118899	0	0	0
T24	130488	0	0	0
T25	0	6	0	0
T26	163814	0	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T53	250643	0	0	0
T112	0	52	0	0
T130	0	8	0	0
T132	0	30	0	0
T181	0	8	0	0
T186	0	39	0	0
T195	0	5	0	0
T209	0	7	0	0
T211	0	9	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1471	0	0
T30	0	4	0	0
T31	0	5	0	0
T78	69210	0	0	0
T92	748706	0	0	0
T112	0	35	0	0
T121	0	30	0	0
T132	0	7	0	0
T186	0	18	0	0
T195	695800	11	0	0
T196	118442	0	0	0
T197	399250	0	0	0
T218	0	24	0	0
T250	0	7	0	0
T276	0	31	0	0
T277	176622	0	0	0
T278	125935	0	0	0
T279	202615	0	0	0
T280	30293	0	0	0
T281	248204	0	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4469	0	0
T25	117944	73	0	0
T28	103768	0	0	0
T42	114169	0	0	0
T43	306537	0	0	0
T58	238102	0	0	0
T59	528297	0	0	0
T61	0	27	0	0
T106	91686	0	0	0
T114	29620	0	0	0
T123	99022	0	0	0
T124	258360	0	0	0
T132	0	173	0	0
T193	0	76	0	0
T195	0	97	0	0
T196	0	64	0	0
T216	0	64	0	0
T288	0	25	0	0
T289	0	51	0	0
T290	0	54	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4821	0	0
T1	176695	0	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T4	243763	48	0	0
T5	255943	0	0	0
T6	200561	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T14	56813	0	0	0
T17	67276	0	0	0
T132	0	164	0	0
T137	0	72	0	0
T195	0	6	0	0
T291	0	95	0	0
T292	0	99	0	0
T293	0	58	0	0
T294	0	17	0	0
T295	0	63	0	0
T296	0	80	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4337	0	0
T1	176695	0	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T4	243763	86	0	0
T5	255943	0	0	0
T6	200561	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T14	56813	0	0	0
T17	67276	0	0	0
T132	0	167	0	0
T137	0	84	0	0
T195	0	3	0	0
T291	0	71	0	0
T292	0	58	0	0
T293	0	88	0	0
T294	0	33	0	0
T295	0	85	0	0
T296	0	50	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	4500	0	0
T1	176695	0	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T4	243763	81	0	0
T5	255943	0	0	0
T6	200561	0	0	0
T7	112636	0	0	0
T8	171804	0	0	0
T14	56813	0	0	0
T17	67276	0	0	0
T132	0	172	0	0
T137	0	78	0	0
T195	0	2	0	0
T291	0	65	0	0
T292	0	53	0	0
T293	0	51	0	0
T294	0	52	0	0
T295	0	75	0	0
T296	0	94	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1796	0	0
T18	0	38	0	0
T30	0	9	0	0
T31	0	11	0	0
T78	69210	0	0	0
T92	748706	0	0	0
T112	0	36	0	0
T121	0	18	0	0
T132	0	16	0	0
T186	0	23	0	0
T195	695800	4	0	0
T196	118442	0	0	0
T197	399250	0	0	0
T218	0	34	0	0
T276	0	29	0	0
T277	176622	0	0	0
T278	125935	0	0	0
T279	202615	0	0	0
T280	30293	0	0	0
T281	248204	0	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1590	0	0
T11	116178	1	0	0
T12	116665	0	0	0
T13	101261	0	0	0
T27	584921	0	0	0
T40	130600	0	0	0
T41	319385	0	0	0
T42	0	6	0	0
T53	250643	0	0	0
T63	63140	0	0	0
T72	0	11	0	0
T81	0	2	0	0
T104	57880	0	0	0
T105	10780	0	0	0
T116	0	9	0	0
T132	0	10	0	0
T195	0	5	0	0
T285	0	2	0	0
T297	0	8	0	0
T298	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1591	0	0
T11	116178	2	0	0
T12	116665	0	0	0
T13	101261	0	0	0
T27	584921	0	0	0
T40	130600	0	0	0
T41	319385	0	0	0
T42	0	8	0	0
T53	250643	0	0	0
T63	63140	0	0	0
T72	0	5	0	0
T104	57880	0	0	0
T105	10780	0	0	0
T112	0	21	0	0
T116	0	7	0	0
T132	0	22	0	0
T195	0	15	0	0
T298	0	9	0	0
T299	0	5	0	0
T300	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1602	0	0
T11	116178	8	0	0
T12	116665	0	0	0
T13	101261	0	0	0
T27	584921	0	0	0
T40	130600	0	0	0
T41	319385	0	0	0
T53	250643	0	0	0
T63	63140	0	0	0
T72	0	6	0	0
T81	0	8	0	0
T104	57880	0	0	0
T105	10780	0	0	0
T116	0	2	0	0
T132	0	20	0	0
T195	0	14	0	0
T297	0	2	0	0
T298	0	4	0	0
T299	0	6	0	0
T300	0	5	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1593	0	0
T11	116178	6	0	0
T12	116665	0	0	0
T13	101261	0	0	0
T27	584921	0	0	0
T40	130600	0	0	0
T41	319385	0	0	0
T42	0	1	0	0
T53	250643	0	0	0
T63	63140	0	0	0
T72	0	12	0	0
T81	0	6	0	0
T104	57880	0	0	0
T105	10780	0	0	0
T112	0	39	0	0
T116	0	1	0	0
T132	0	21	0	0
T195	0	4	0	0
T298	0	6	0	0
T301	0	2	0	0