Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T17
1	1	Covered	T4,T5,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T17
1	1	Covered	T4,T5,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T11
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T17,T1,T2
0	0	1	Covered	T17,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T17,T1,T2
0	0	1	Covered	T17,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	104165321	0	0
DstReqKnown_A	200626928	172374118	0	0
SrcAckBusyChk_A	2147483647	117269	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	104165321	0	0
T1	2473730	3578	0	0
T2	2902746	4938	0	0
T3	6581862	11568	0	0
T7	1914812	4651	0	0
T8	4295100	2336	0	0
T9	8926100	1738	0	0
T10	331344	0	0	0
T11	116178	0	0	0
T12	116665	1195	0	0
T13	0	32492	0	0
T14	795382	0	0	0
T15	20685500	0	0	0
T16	2697500	0	0	0
T17	67276	0	0	0
T23	1426788	0	0	0
T24	130488	13955	0	0
T26	1801954	6655	0	0
T27	0	15440	0	0
T40	130600	5932	0	0
T41	0	19411	0	0
T42	0	1971	0	0
T43	0	4284	0	0
T44	0	3502	0	0
T45	0	21957	0	0
T46	0	5281	0	0
T47	0	2564	0	0
T48	0	11096	0	0
T49	0	2490	0	0
T50	2526420	0	0	0
T51	1282272	0	0	0
T52	437400	0	0	0
T53	250643	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200626928	172374118	0	0
T1	500650	486234	0	0
T2	587452	572764	0	0
T3	639370	624580	0	0
T4	17068	3468	0	0
T5	17714	4114	0	0
T6	14348	748	0	0
T7	331704	153986	0	0
T8	486778	472940	0	0
T14	15436	1836	0	0
T17	20774	7174	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	117269	0	0
T1	2473730	10	0	0
T2	2902746	12	0	0
T3	6581862	14	0	0
T7	1914812	11	0	0
T8	4295100	6	0	0
T9	8926100	1	0	0
T10	331344	0	0	0
T11	116178	0	0	0
T12	116665	3	0	0
T13	0	18	0	0
T14	795382	0	0	0
T15	20685500	0	0	0
T16	2697500	0	0	0
T17	67276	0	0	0
T23	1426788	0	0	0
T24	130488	8	0	0
T26	1801954	9	0	0
T27	0	8	0	0
T40	130600	8	0	0
T41	0	12	0	0
T42	0	1	0	0
T43	0	11	0	0
T44	0	7	0	0
T45	0	13	0	0
T46	0	13	0	0
T47	0	7	0	0
T48	0	6	0	0
T49	0	7	0	0
T50	2526420	0	0	0
T51	1282272	0	0	0
T52	437400	0	0	0
T53	250643	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6007630	5997600	0	0
T2	7049526	7036164	0	0
T3	15984522	15954568	0	0
T4	8287942	8285426	0	0
T5	8702062	8699750	0	0
T6	6819074	6815742	0	0
T7	3829624	3816568	0	0
T8	5841336	5838174	0	0
T14	1931642	1928480	0	0
T17	2287384	2284120	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T54,T30,T31
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1135745	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1181	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1135745	0	0
T1	176695	2235	0	0
T2	207339	4641	0	0
T3	470133	6607	0	0
T7	112636	800	0	0
T8	171804	477	0	0
T9	357044	1724	0	0
T10	13806	0	0	0
T11	0	952	0	0
T12	0	824	0	0
T13	0	14371	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	5811	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1181	0	0
T1	176695	6	0	0
T2	207339	11	0	0
T3	470133	8	0	0
T7	112636	2	0	0
T8	171804	1	0	0
T9	357044	1	0	0
T10	13806	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T13	0	8	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T17,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T17,T1,T2
1	1	Covered	T17,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T17,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T1,T2
1	1	Covered	T17,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T17,T1,T2
0	0	1	Covered	T17,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T17,T1,T2
0	0	1	Covered	T17,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1870109	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	2109	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1870109	0	0
T1	176695	1786	0	0
T2	207339	2379	0	0
T3	470133	5458	0	0
T7	112636	707	0	0
T8	171804	1081	0	0
T9	357044	5210	0	0
T12	0	1510	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	549	0	0
T17	67276	303	0	0
T51	0	368	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2109	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	2	0	0
T8	171804	3	0	0
T9	357044	3	0	0
T12	0	4	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	1	0	0
T17	67276	1	0	0
T51	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T15,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T15,T9
1	1	Covered	T7,T15,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T15,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T15,T9
1	1	Covered	T7,T15,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T15,T9
0	0	1	Covered	T7,T15,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T15,T9
0	0	1	Covered	T7,T15,T9
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1020628	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1042	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1020628	0	0
T7	112636	333	0	0
T8	171804	0	0	0
T9	357044	1744	0	0
T10	13806	0	0	0
T11	0	1968	0	0
T12	0	1225	0	0
T15	827420	1897	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T34	0	371	0	0
T42	0	1976	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	5467	0	0
T56	0	740	0	0
T57	0	4931	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1042	0	0
T7	112636	1	0	0
T8	171804	0	0	0
T9	357044	1	0	0
T10	13806	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T15	827420	1	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T34	0	1	0	0
T42	0	1	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T15,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T15,T9
1	1	Covered	T7,T15,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T15,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T15,T9
1	1	Covered	T7,T15,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T15,T9
0	0	1	Covered	T7,T15,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T15,T9
0	0	1	Covered	T7,T15,T9
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1042988	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1048	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1042988	0	0
T7	112636	323	0	0
T8	171804	0	0	0
T9	357044	1732	0	0
T10	13806	0	0	0
T11	0	1954	0	0
T12	0	1195	0	0
T15	827420	1895	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T34	0	369	0	0
T42	0	1967	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	5443	0	0
T56	0	735	0	0
T57	0	4918	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1048	0	0
T7	112636	1	0	0
T8	171804	0	0	0
T9	357044	1	0	0
T10	13806	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T15	827420	1	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T34	0	1	0	0
T42	0	1	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T15,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T15,T9
1	1	Covered	T7,T15,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T15,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T15,T9
1	1	Covered	T7,T15,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T15,T9
0	0	1	Covered	T7,T15,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T15,T9
0	0	1	Covered	T7,T15,T9
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1051256	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1067	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1051256	0	0
T7	112636	317	0	0
T8	171804	0	0	0
T9	357044	1730	0	0
T10	13806	0	0	0
T11	0	1925	0	0
T12	0	1168	0	0
T15	827420	1893	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T34	0	367	0	0
T42	0	1961	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	5428	0	0
T56	0	731	0	0
T57	0	4901	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1067	0	0
T7	112636	1	0	0
T8	171804	0	0	0
T9	357044	1	0	0
T10	13806	0	0	0
T11	0	2	0	0
T12	0	3	0	0
T15	827420	1	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T34	0	1	0	0
T42	0	1	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T23,T24,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T23,T24,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T23,T24,T25
0	0	1	Covered	T23,T24,T25
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T23,T24,T25
0	0	1	Covered	T23,T24,T25
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	2940120	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	2932	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2940120	0	0
T11	116178	0	0	0
T12	116665	0	0	0
T13	101261	0	0	0
T23	118899	17160	0	0
T24	130488	35387	0	0
T25	0	35902	0	0
T34	0	26262	0	0
T40	130600	0	0	0
T46	0	8264	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T53	250643	0	0	0
T58	0	35419	0	0
T59	0	11902	0	0
T60	0	33383	0	0
T61	0	33377	0	0
T62	0	24850	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2932	0	0
T11	116178	0	0	0
T12	116665	0	0	0
T13	101261	0	0	0
T23	118899	20	0	0
T24	130488	20	0	0
T25	0	20	0	0
T34	0	60	0	0
T40	130600	0	0	0
T46	0	20	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T53	250643	0	0	0
T58	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	5209561	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	6412	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	5209561	0	0
T1	176695	0	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T4	243763	34378	0	0
T5	255943	34452	0	0
T6	200561	0	0	0
T7	112636	30952	0	0
T8	171804	0	0	0
T9	0	91323	0	0
T12	0	43165	0	0
T14	56813	0	0	0
T15	0	32703	0	0
T17	67276	0	0	0
T23	0	944	0	0
T24	0	69822	0	0
T53	0	35183	0	0
T63	0	8640	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6412	0	0
T1	176695	0	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T4	243763	20	0	0
T5	255943	20	0	0
T6	200561	0	0	0
T7	112636	80	0	0
T8	171804	0	0	0
T9	0	60	0	0
T12	0	100	0	0
T14	56813	0	0	0
T15	0	20	0	0
T17	67276	0	0	0
T23	0	1	0	0
T24	0	41	0	0
T53	0	20	0	0
T63	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T17
1	1	Covered	T4,T5,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T17
1	1	Covered	T4,T5,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T17
0	0	1	Covered	T4,T5,T17
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T17
0	0	1	Covered	T4,T5,T17
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6286720	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7630	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6286720	0	0
T1	176695	1966	0	0
T2	207339	2512	0	0
T3	470133	5870	0	0
T4	243763	34814	0	0
T5	255943	34695	0	0
T6	200561	0	0	0
T7	112636	33188	0	0
T8	171804	1189	0	0
T14	56813	0	0	0
T15	0	32783	0	0
T16	0	551	0	0
T17	67276	314	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7630	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T4	243763	20	0	0
T5	255943	20	0	0
T6	200561	0	0	0
T7	112636	83	0	0
T8	171804	3	0	0
T14	56813	0	0	0
T15	0	20	0	0
T16	0	1	0	0
T17	67276	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T7
1	1	Covered	T4,T5,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T7
0	0	1	Covered	T4,T5,T7
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	5192182	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	6340	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	5192182	0	0
T1	176695	0	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T4	243763	34606	0	0
T5	255943	34575	0	0
T6	200561	0	0	0
T7	112636	31528	0	0
T8	171804	0	0	0
T9	0	91753	0	0
T12	0	43893	0	0
T14	56813	0	0	0
T15	0	32743	0	0
T17	67276	0	0	0
T24	0	68580	0	0
T41	0	101801	0	0
T53	0	35339	0	0
T63	0	8773	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6340	0	0
T1	176695	0	0	0
T2	207339	0	0	0
T3	470133	0	0	0
T4	243763	20	0	0
T5	255943	20	0	0
T6	200561	0	0	0
T7	112636	80	0	0
T8	171804	0	0	0
T9	0	60	0	0
T12	0	100	0	0
T14	56813	0	0	0
T15	0	20	0	0
T17	67276	0	0	0
T24	0	40	0	0
T41	0	60	0	0
T53	0	20	0	0
T63	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T10
1	1	Covered	T7,T9,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T9,T10
0	0	1	Covered	T7,T9,T10
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1120305	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1086	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1120305	0	0
T7	112636	341	0	0
T8	171804	0	0	0
T9	357044	1752	0	0
T10	13806	111	0	0
T12	0	862	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T25	0	3823	0	0
T26	163814	0	0	0
T34	0	868	0	0
T37	0	189	0	0
T38	0	980	0	0
T46	0	657	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T64	0	998	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1086	0	0
T7	112636	1	0	0
T8	171804	0	0	0
T9	357044	1	0	0
T10	13806	1	0	0
T12	0	2	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T25	0	2	0	0
T26	163814	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T46	0	1	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T64	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1800666	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	2083	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1800666	0	0
T1	176695	1985	0	0
T2	207339	2367	0	0
T3	470133	5421	0	0
T7	112636	1150	0	0
T8	171804	1075	0	0
T9	357044	3465	0	0
T10	13806	102	0	0
T12	0	1855	0	0
T13	0	16093	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7596	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2083	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	3	0	0
T8	171804	3	0	0
T9	357044	2	0	0
T10	13806	1	0	0
T12	0	5	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T26,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T26,T24
1	1	Covered	T7,T26,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T26,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T26,T24
1	1	Covered	T7,T26,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T26,T24
0	0	1	Covered	T7,T26,T24
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T26,T24
0	0	1	Covered	T7,T26,T24
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1352905	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1383	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1352905	0	0
T7	112636	2254	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T24	0	8487	0	0
T26	163814	4530	0	0
T40	0	3769	0	0
T41	0	11470	0	0
T44	0	2024	0	0
T46	0	3344	0	0
T47	0	1508	0	0
T48	0	5554	0	0
T49	0	1398	0	0
T50	210535	0	0	0
T51	106856	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1383	0	0
T7	112636	5	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T24	0	5	0	0
T26	163814	6	0	0
T40	0	5	0	0
T41	0	7	0	0
T44	0	4	0	0
T46	0	8	0	0
T47	0	4	0	0
T48	0	3	0	0
T49	0	4	0	0
T50	210535	0	0	0
T51	106856	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T26,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T26,T24
1	1	Covered	T7,T26,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T26,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T26,T24
1	1	Covered	T7,T26,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T26,T24
0	0	1	Covered	T7,T26,T24
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T26,T24
0	0	1	Covered	T7,T26,T24
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1180292	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1203	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1180292	0	0
T7	112636	1284	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T24	0	5468	0	0
T26	163814	2125	0	0
T40	0	2163	0	0
T41	0	7941	0	0
T44	0	1478	0	0
T46	0	1937	0	0
T47	0	1056	0	0
T48	0	5542	0	0
T49	0	1092	0	0
T50	210535	0	0	0
T51	106856	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1203	0	0
T7	112636	3	0	0
T8	171804	0	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T24	0	3	0	0
T26	163814	3	0	0
T40	0	3	0	0
T41	0	5	0	0
T44	0	3	0	0
T46	0	5	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	210535	0	0	0
T51	106856	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T28
1	1	Covered	T8,T27,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T28
1	1	Covered	T8,T27,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T28
0	0	1	Covered	T8,T27,T28
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T28
0	0	1	Covered	T8,T27,T28
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6369137	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7081	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6369137	0	0
T8	171804	27236	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	109378	0	0
T28	0	900	0	0
T29	0	6433	0	0
T39	0	24013	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	35589	0	0
T66	0	153242	0	0
T67	0	120383	0	0
T68	0	17011	0	0
T69	0	1017	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7081	0	0
T8	171804	66	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	63	0	0
T28	0	1	0	0
T29	0	70	0	0
T39	0	58	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	84	0	0
T66	0	88	0	0
T67	0	68	0	0
T68	0	78	0	0
T69	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6324324	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7129	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6324324	0	0
T8	171804	26954	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	109102	0	0
T29	0	6034	0	0
T39	0	22102	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	30291	0	0
T66	0	156869	0	0
T67	0	104112	0	0
T68	0	18185	0	0
T70	0	21713	0	0
T71	0	15048	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7129	0	0
T8	171804	66	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	63	0	0
T29	0	68	0	0
T39	0	54	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	75	0	0
T66	0	90	0	0
T67	0	59	0	0
T68	0	84	0	0
T70	0	67	0	0
T71	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6244383	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7082	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6244383	0	0
T8	171804	31309	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	104011	0	0
T29	0	6134	0	0
T39	0	23520	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	32634	0	0
T66	0	123142	0	0
T67	0	128296	0	0
T68	0	15192	0	0
T70	0	21439	0	0
T71	0	14055	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7082	0	0
T8	171804	77	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	60	0	0
T29	0	68	0	0
T39	0	58	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	84	0	0
T66	0	71	0	0
T67	0	74	0	0
T68	0	72	0	0
T70	0	67	0	0
T71	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6250615	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7188	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6250615	0	0
T8	171804	25021	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	97030	0	0
T29	0	7460	0	0
T39	0	23264	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	21574	0	0
T66	0	144271	0	0
T67	0	103552	0	0
T68	0	15027	0	0
T70	0	21165	0	0
T71	0	13370	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7188	0	0
T8	171804	62	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	56	0	0
T29	0	83	0	0
T39	0	58	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	56	0	0
T66	0	83	0	0
T67	0	59	0	0
T68	0	72	0	0
T70	0	67	0	0
T71	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T28

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T28
1	1	Covered	T8,T27,T28

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T28

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T28
1	1	Covered	T8,T27,T28

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T28
0	0	1	Covered	T8,T27,T28
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T28
0	0	1	Covered	T8,T27,T28
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1303609	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1331	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1303609	0	0
T8	171804	1195	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	7756	0	0
T28	0	898	0	0
T29	0	803	0	0
T39	0	1674	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	712	0	0
T66	0	16483	0	0
T67	0	15486	0	0
T68	0	1549	0	0
T69	0	1015	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1331	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	4	0	0
T28	0	1	0	0
T29	0	9	0	0
T39	0	4	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	2	0	0
T66	0	10	0	0
T67	0	9	0	0
T68	0	7	0	0
T69	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1297916	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1341	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1297916	0	0
T8	171804	1165	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	7716	0	0
T29	0	774	0	0
T39	0	1634	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	631	0	0
T66	0	16383	0	0
T67	0	15396	0	0
T68	0	1479	0	0
T70	0	273	0	0
T71	0	221	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1341	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	4	0	0
T29	0	9	0	0
T39	0	4	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	2	0	0
T66	0	10	0	0
T67	0	9	0	0
T68	0	7	0	0
T70	0	1	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1323581	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1367	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1323581	0	0
T8	171804	1135	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	7676	0	0
T29	0	772	0	0
T39	0	1594	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	531	0	0
T66	0	16283	0	0
T67	0	15306	0	0
T68	0	1409	0	0
T70	0	263	0	0
T71	0	252	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1367	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	4	0	0
T29	0	9	0	0
T39	0	4	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	2	0	0
T66	0	10	0	0
T67	0	9	0	0
T68	0	7	0	0
T70	0	1	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T27,T29
1	1	Covered	T8,T27,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T27,T29
0	0	1	Covered	T8,T27,T29
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1260643	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1315	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1260643	0	0
T8	171804	1105	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	7636	0	0
T29	0	808	0	0
T39	0	1554	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	706	0	0
T66	0	16183	0	0
T67	0	15216	0	0
T68	0	1339	0	0
T70	0	253	0	0
T71	0	201	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1315	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T27	0	4	0	0
T29	0	9	0	0
T39	0	4	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T52	48600	0	0	0
T65	0	2	0	0
T66	0	10	0	0
T67	0	9	0	0
T68	0	7	0	0
T70	0	1	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6891238	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7747	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6891238	0	0
T1	176695	2023	0	0
T2	207339	2523	0	0
T3	470133	5985	0	0
T7	112636	813	0	0
T8	171804	27350	0	0
T9	357044	1749	0	0
T10	13806	0	0	0
T12	0	1219	0	0
T13	0	16327	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	109480	0	0
T42	0	1985	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7747	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	2	0	0
T8	171804	66	0	0
T9	357044	1	0	0
T10	13806	0	0	0
T12	0	3	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	63	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6865355	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7761	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6865355	0	0
T1	176695	1962	0	0
T2	207339	2511	0	0
T3	470133	5942	0	0
T7	112636	353	0	0
T8	171804	27068	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16309	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	109204	0	0
T43	0	4753	0	0
T45	0	22061	0	0
T60	0	7936	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7761	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	66	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	63	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6783244	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7724	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6783244	0	0
T1	176695	1920	0	0
T2	207339	2499	0	0
T3	470133	5901	0	0
T7	112636	351	0	0
T8	171804	31445	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16291	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	104107	0	0
T43	0	4647	0	0
T45	0	22035	0	0
T60	0	7898	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7724	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	77	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	60	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	6781336	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	7827	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	6781336	0	0
T1	176695	1861	0	0
T2	207339	2487	0	0
T3	470133	5853	0	0
T7	112636	343	0	0
T8	171804	25127	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16273	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	97118	0	0
T43	0	4543	0	0
T45	0	22009	0	0
T60	0	7873	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	7827	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	62	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	56	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1812991	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	2013	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1812991	0	0
T1	176695	1814	0	0
T2	207339	2475	0	0
T3	470133	5802	0	0
T7	112636	784	0	0
T8	171804	1183	0	0
T9	357044	1738	0	0
T10	13806	0	0	0
T12	0	1195	0	0
T13	0	16255	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7740	0	0
T42	0	1971	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2013	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	2	0	0
T8	171804	3	0	0
T9	357044	1	0	0
T10	13806	0	0	0
T12	0	3	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1752176	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1943	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1752176	0	0
T1	176695	1764	0	0
T2	207339	2463	0	0
T3	470133	5766	0	0
T7	112636	329	0	0
T8	171804	1153	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16237	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7700	0	0
T43	0	4284	0	0
T45	0	21957	0	0
T60	0	7822	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1943	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1792983	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1974	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1792983	0	0
T1	176695	1710	0	0
T2	207339	2451	0	0
T3	470133	5702	0	0
T7	112636	319	0	0
T8	171804	1123	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16219	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7660	0	0
T43	0	4186	0	0
T45	0	21931	0	0
T60	0	7782	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1974	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1758718	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1960	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1758718	0	0
T1	176695	1665	0	0
T2	207339	2439	0	0
T3	470133	5672	0	0
T7	112636	316	0	0
T8	171804	1093	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16201	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7620	0	0
T43	0	4080	0	0
T45	0	21905	0	0
T60	0	7744	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1960	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1828209	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	2036	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1828209	0	0
T1	176695	1616	0	0
T2	207339	2427	0	0
T3	470133	5638	0	0
T7	112636	757	0	0
T8	171804	1177	0	0
T9	357044	1726	0	0
T10	13806	0	0	0
T12	0	1173	0	0
T13	0	16183	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7732	0	0
T42	0	1958	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	2036	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	2	0	0
T8	171804	3	0	0
T9	357044	1	0	0
T10	13806	0	0	0
T12	0	3	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T42	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1754978	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1952	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1754978	0	0
T1	176695	1572	0	0
T2	207339	2415	0	0
T3	470133	5600	0	0
T7	112636	298	0	0
T8	171804	1147	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16165	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7692	0	0
T43	0	4057	0	0
T45	0	21853	0	0
T60	0	7679	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1952	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1753110	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1959	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1753110	0	0
T1	176695	1526	0	0
T2	207339	2403	0	0
T3	470133	5557	0	0
T7	112636	286	0	0
T8	171804	1117	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16147	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7652	0	0
T43	0	4201	0	0
T45	0	21827	0	0
T60	0	7644	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1959	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1762444	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1952	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1762444	0	0
T1	176695	1607	0	0
T2	207339	2391	0	0
T3	470133	5504	0	0
T7	112636	274	0	0
T8	171804	1087	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	16129	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	7612	0	0
T43	0	4439	0	0
T45	0	21801	0	0
T60	0	7612	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1952	0	0
T1	176695	5	0	0
T2	207339	6	0	0
T3	470133	7	0	0
T7	112636	1	0	0
T8	171804	3	0	0
T9	357044	0	0	0
T10	13806	0	0	0
T13	0	9	0	0
T14	56813	0	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T27	0	4	0	0
T43	0	11	0	0
T45	0	13	0	0
T60	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T11
1	-	Covered	T7,T9,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T9,T11
1	1	Covered	T7,T9,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T9,T11
0	0	1	Covered	T7,T9,T11
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1101728147	1050854	0	0
DstReqKnown_A	5900792	5069827	0	0
SrcAckBusyChk_A	1101728147	1071	0	0
SrcBusyKnown_A	1101728147	1100002126	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1050854	0	0
T7	112636	796	0	0
T8	171804	0	0	0
T9	357044	3482	0	0
T10	13806	0	0	0
T11	0	1955	0	0
T12	0	1828	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T42	0	3446	0	0
T46	0	851	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	3463	0	0
T57	0	6393	0	0
T72	0	1862	0	0
T73	0	1499	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5900792	5069827	0	0
T1	14725	14301	0	0
T2	17278	16846	0	0
T3	18805	18370	0	0
T4	502	102	0	0
T5	521	121	0	0
T6	422	22	0	0
T7	9756	4529	0	0
T8	14317	13910	0	0
T14	454	54	0	0
T17	611	211	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1071	0	0
T7	112636	2	0	0
T8	171804	0	0	0
T9	357044	2	0	0
T10	13806	0	0	0
T11	0	2	0	0
T12	0	4	0	0
T15	827420	0	0	0
T16	107900	0	0	0
T23	118899	0	0	0
T26	163814	0	0	0
T42	0	2	0	0
T46	0	2	0	0
T50	210535	0	0	0
T51	106856	0	0	0
T55	0	2	0	0
T57	0	4	0	0
T72	0	4	0	0
T73	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101728147	1100002126	0	0
T1	176695	176400	0	0
T2	207339	206946	0	0
T3	470133	469252	0	0
T4	243763	243689	0	0
T5	255943	255875	0	0
T6	200561	200463	0	0
T7	112636	112252	0	0
T8	171804	171711	0	0
T14	56813	56720	0	0
T17	67276	67180	0	0