Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1890

1

T14

12

T2

16

T3

14

auto[1]

663

1

T3

2

T4

7

T9

11

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1947

1

T14

9

T2

12

T3

15

auto[1]

606

1

T14

3

T2

4

T3

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1933

1

T14

10

T2

16

T3

14

auto[1]

620

1

T14

2

T3

2

T4

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1904

1

T14

11

T2

16

T3

14

auto[1]

649

1

T14

1

T3

2

T4

14

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2400

1

T14

11

T2

16

T3

16

auto[1]

153

1

T14

1

T48

3

T70

8

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2296

1

T14

12

T2

16

T3

16

auto[1]

257

1

T33

1

T70

7

T71

18

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2321

1

T14

11

T2

15

T3

14

auto[1]

232

1

T14

1

T2

1

T3

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2326

1

T14

12

T2

13

T3

14

auto[1]

227

1

T2

3

T3

2

T9

22

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2410

1

T14

10

T2

16

T3

15

auto[1]

143

1

T14

2

T3

1

T48

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1914

1

T14

12

T2

12

T3

16

auto[1]

639

1

T2

4

T4

12

T46

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	954	1			T4	24		T46	3		T11	13
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	59	1			T70	1		T230	8		T231	20
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	21	1			T14	2		T3	1		T246	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T246	1		T210	2		T342	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	107	1			T2	3		T3	2		T9	22
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	17	1			T71	5		T321	1		T98	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	25	1			T231	7		T318	3		T336	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T108	2		T240	1		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	67	1			T2	1		T3	2		T33	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T14	1		T330	4		T343	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	30	1			T69	1		T320	12		T95	16
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	4	1			T48	3		T333	1		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	12	1			T230	6		T98	2		T344	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T345	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	8	1			T246	5		T336	3		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	62	1			T71	18		T105	5		T255	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	22	1			T320	4		T346	6		T97	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	32	1			T320	7		T347	12		T346	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T348	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	22	1			T33	1		T230	4		T349	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T96	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T333	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	66	1			T169	39		T95	3		T350	4
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	11	1			T351	2		T352	3		T353	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	8	1			T347	3		T346	5		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T348	1		T334	2		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T257	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

113

1

T36

9

T44

7

T35

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

131

1

T4

12

T33

1

T118

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

59

1

T9

11

T71

9

T230

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

106

1

T3

2

T48

3

T34

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

65

1

T121

4

T354

6

T153

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

73

1

T46

3

T44

7

T169

13

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T34

3

T355

4

T111

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

151

1

T55

28

T35

7

T246

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

66

1

T3

2

T118

4

T347

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T71

9

T255

1

T282

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T58

1

T45

2

T354

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

73

1

T118

4

T231

10

T321

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

29

1

T355

4

T356

3

T347

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

25

1

T11

3

T354

3

T129

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T298

1

T357

3

T358

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

87

1

T3

1

T230

8

T257

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

71

1

T34

3

T35

4

T105

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

53

1

T2

4

T9

11

T11

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T11

3

T111

2

T271

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

69

1

T14

1

T4

7

T69

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

58

1

T4

5

T55

5

T321

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28

1

T33

4

T231

10

T239

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T349

1

T324

1

T359

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T14

2

T45

4

T355

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T355

2

T317

4

T282

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T69

2

T71

5

T153

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T11

3

T118

1

T34

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

11

1

T121

3

T112

1

T265

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T153

1

T214

2

T323

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

19

1

T44

1

T153

2

T129

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T129

1

T115

2

T219

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded