Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T7

11

T20

7

T10

9

auto[1]

1147

1

T7

9

T20

13

T10

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

570

1

T7

6

T20

4

T10

5

from_0to1

555

1

T7

6

T20

4

T10

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T7

9

T20

13

T10

7

auto[1]

1155

1

T7

11

T20

7

T10

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132

1

T7

11

T20

4

T10

7

auto[1]

1195

1

T7

9

T20

16

T10

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

83

1

T7

2

T10

1

T43

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T165

2

T34

2

T290

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T34

1

T45

2

T292

1

auto[0]

from_1to0

auto[1]

auto[1]

89

1

T7

3

T20

2

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T20

1

T34

1

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T34

2

T45

1

T72

2

auto[0]

from_0to1

auto[1]

auto[0]

83

1

T7

1

T10

1

T165

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T7

1

T34

1

T45

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T165

1

T45

2

T290

2

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T20

2

T10

1

T34

2

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T10

1

T34

1

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T7

1

T10

1

T43

2

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T7

2

T165

1

T34

3

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T7

1

T20

1

T10

4

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T7

1

T20

1

T165

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T20

1

T10

1

T34

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1164

1

T7

15

T20

6

T10

9

auto[1]

1163

1

T7

5

T20

14

T10

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

548

1

T7

4

T20

5

T10

5

from_0to1

546

1

T7

3

T20

4

T10

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T7

12

T20

16

T10

12

auto[1]

1201

1

T7

8

T20

4

T10

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T7

9

T20

14

T10

13

auto[1]

1214

1

T7

11

T20

6

T10

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T7

2

T20

1

T10

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T20

1

T10

2

T165

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T34

1

T45

1

T290

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T7

2

T165

1

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T20

1

T10

1

T34

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T7

1

T20

1

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T165

2

T43

1

T45

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T7

1

T10

2

T34

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T20

2

T10

2

T165

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T20

1

T165

1

T43

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T165

1

T34

2

T290

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T34

2

T45

2

T284

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T7

1

T20

2

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T165

2

T43

1

T34

3

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T34

1

T45

2

T369

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T165

3

T43

1

T34

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1182

1

T7

11

T20

9

T10

12

auto[1]

1145

1

T7

9

T20

11

T10

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

554

1

T7

5

T20

5

T10

5

from_0to1

554

1

T7

4

T20

4

T10

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1186

1

T7

14

T20

12

T10

13

auto[1]

1141

1

T7

6

T20

8

T10

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184

1

T7

11

T20

12

T10

10

auto[1]

1143

1

T7

9

T20

8

T10

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T7

1

T20

1

T165

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T10

1

T34

1

T370

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T10

2

T165

2

T34

2

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T7

2

T20

1

T165

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T7

1

T20

1

T10

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T43

1

T290

1

T371

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T7

1

T10

2

T43

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T43

1

T34

6

T45

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T7

1

T20

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T7

1

T20

1

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T20

1

T34

3

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T43

2

T34

1

T45

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T7

1

T45

3

T290

2

auto[1]

from_0to1

auto[0]

auto[1]

89

1

T7

1

T20

1

T10

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T20

2

T43

1

T34

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T165

1

T34

1

T292

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T7

11

T20

11

T10

10

auto[1]

1184

1

T7

9

T20

9

T10

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T7

3

T20

5

T10

4

from_0to1

555

1

T7

4

T20

5

T10

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T7

10

T20

10

T10

13

auto[1]

1186

1

T7

10

T20

10

T10

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1160

1

T7

13

T20

9

T10

11

auto[1]

1167

1

T7

7

T20

11

T10

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T10

1

T43

1

T34

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T20

1

T165

1

T34

2

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T7

2

T20

1

T43

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T10

1

T34

1

T45

3

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T20

1

T10

1

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T7

1

T20

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

88

1

T7

1

T20

1

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T20

1

T10

1

T165

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T20

1

T10

1

T165

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T20

1

T10

1

T165

1

auto[1]

from_1to0

auto[1]

auto[0]

73

1

T7

1

T34

2

T45

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T20

1

T165

1

T34

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T7

1

T20

1

T43

2

auto[1]

from_0to1

auto[0]

auto[1]

67

1

T10

1

T45

4

T292

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T7

1

T165

1

T34

2

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T165

1

T45

1

T290

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T7

9

T20

8

T10

9

auto[1]

1186

1

T7

11

T20

12

T10

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

558

1

T7

4

T20

5

T10

6

from_0to1

555

1

T7

4

T20

6

T10

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T7

10

T20

9

T10

9

auto[1]

1191

1

T7

10

T20

11

T10

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1164

1

T7

12

T20

12

T10

12

auto[1]

1163

1

T7

8

T20

8

T10

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T7

1

T20

1

T10

3

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T7

2

T165

1

T34

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T165

1

T43

1

T34

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T165

1

T45

2

T292

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T165

2

T43

2

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T7

1

T20

1

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T43

2

T34

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T165

1

T43

1

T290

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T165

1

T34

1

T45

2

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T20

1

T34

1

T45

2

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T7

1

T20

3

T10

3

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T43

2

T34

2

T45

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T7

2

T10

1

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T20

1

T34

2

T284

2

auto[1]

from_0to1

auto[1]

auto[0]

83

1

T7

1

T20

3

T10

2

auto[1]

from_0to1

auto[1]

auto[1]

92

1

T20

1

T10

1

T165

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1167

1

T7

9

T20

5

T10

7

auto[1]

1160

1

T7

11

T20

15

T10

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T7

6

T20

4

T10

4

from_0to1

565

1

T7

5

T20

5

T10

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1166

1

T7

8

T20

10

T10

11

auto[1]

1161

1

T7

12

T20

10

T10

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1205

1

T7

12

T20

14

T10

11

auto[1]

1122

1

T7

8

T20

6

T10

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T43

1

T34

2

T45

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T165

1

T43

1

T34

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T7

1

T165

1

T43

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T7

2

T45

1

T290

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T7

1

T20

2

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T165

2

T43

1

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

100

1

T7

1

T10

1

T43

3

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T7

1

T165

1

T34

2

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T7

1

T20

2

T43

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T7

1

T165

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T7

1

T20

1

T10

2

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T20

1

T10

2

T165

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T20

1

T34

2

T45

1

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T7

1

T10

1

T34

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T7

1

T20

2

T10

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T45

1

T292

1

T372

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T7

8

T20

6

T10

10

auto[1]

1187

1

T7

12

T20

14

T10

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

571

1

T7

6

T20

4

T10

3

from_0to1

578

1

T7

6

T20

4

T10

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1173

1

T7

13

T20

8

T10

11

auto[1]

1154

1

T7

7

T20

12

T10

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T7

9

T20

10

T10

10

auto[1]

1187

1

T7

11

T20

10

T10

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T20

1

T10

1

T290

1

auto[0]

from_1to0

auto[0]

auto[1]

94

1

T7

2

T20

2

T165

2

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T7

1

T34

2

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T10

1

T43

1

T34

2

auto[0]

from_0to1

auto[0]

auto[0]

80

1

T165

1

T43

1

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T7

1

T43

1

T34

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T165

1

T43

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

83

1

T7

1

T10

2

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T10

1

T165

1

T43

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T7

2

T43

1

T34

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T7

1

T165

3

T34

2

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T20

1

T43

1

T45

3

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T7

2

T20

2

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T7

1

T165

1

T34

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T7

1

T20

2

T34

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T10

1

T165

2

T34

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T7

10

T20

9

T10

9

auto[1]

1177

1

T7

10

T20

11

T10

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

570

1

T7

5

T20

5

T10

5

from_0to1

564

1

T7

6

T20

5

T10

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1218

1

T7

11

T20

12

T10

15

auto[1]

1109

1

T7

9

T20

8

T10

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T7

11

T20

11

T10

13

auto[1]

1181

1

T7

9

T20

9

T10

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T7

1

T20

1

T10

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T10

1

T165

1

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T165

1

T34

1

T292

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T7

1

T20

1

T34

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T20

1

T43

3

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T10

1

T34

3

T45

3

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T7

2

T20

1

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T20

1

T10

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

83

1

T10

1

T165

1

T43

2

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T7

2

T20

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T20

2

T10

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T7

1

T10

1

T43

1

auto[1]

from_0to1

auto[0]

auto[0]

80

1

T7

1

T20

1

T10

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T7

2

T20

1

T290

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T7

1

T10

1

T165

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T165

1

T34

1

T45

1