Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113545

1

T5

11

T6

2

T7

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136737	1			T5	8		T6	9		T7	62
values[0x0]	62969	1			T5	6		T6	2		T7	24
values[0x1]	63305	1			T5	3		T6	2		T7	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	120754	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142257

1

T5

11

T6

3

T7

64

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	789	1			T7	1		T21	1		T14	5
valid_sources[0x01]	1142	1			T7	1		T14	3		T3	10
valid_sources[0x02]	983	1			T6	1		T7	2		T14	4
valid_sources[0x03]	1087	1			T7	2		T14	4		T3	5
valid_sources[0x04]	928	1			T7	1		T14	7		T3	2
valid_sources[0x05]	1882	1			T7	3		T14	5		T3	2
valid_sources[0x06]	1076	1			T14	3		T3	2		T20	1
valid_sources[0x07]	1797	1			T14	3		T3	4		T4	1
valid_sources[0x08]	1110	1			T7	2		T21	2		T14	5
valid_sources[0x09]	872	1			T14	9		T3	4		T4	1
valid_sources[0x0a]	766	1			T7	3		T21	2		T14	3
valid_sources[0x0b]	842	1			T14	4		T3	6		T20	1
valid_sources[0x0c]	895	1			T21	1		T14	7		T3	1
valid_sources[0x0d]	1178	1			T21	1		T14	3		T3	5
valid_sources[0x0e]	774	1			T14	3		T3	5		T9	2
valid_sources[0x0f]	838	1			T14	3		T3	7		T20	1
valid_sources[0x10]	866	1			T7	1		T14	6		T3	5
valid_sources[0x11]	936	1			T14	8		T3	5		T20	1
valid_sources[0x12]	792	1			T21	1		T14	5		T3	3
valid_sources[0x13]	720	1			T14	12		T3	4		T20	2
valid_sources[0x14]	873	1			T14	2		T3	5		T4	1
valid_sources[0x15]	903	1			T7	1		T14	2		T3	7
valid_sources[0x16]	1540	1			T14	6		T3	7		T4	1
valid_sources[0x17]	752	1			T7	1		T14	3		T3	4
valid_sources[0x18]	820	1			T3	7		T4	9		T9	17
valid_sources[0x19]	1332	1			T7	1		T14	2		T3	3
valid_sources[0x1a]	938	1			T14	6		T3	6		T20	1
valid_sources[0x1b]	915	1			T7	1		T14	2		T3	3
valid_sources[0x1c]	873	1			T14	2		T3	8		T19	1
valid_sources[0x1d]	921	1			T7	1		T14	1		T3	8
valid_sources[0x1e]	800	1			T14	5		T3	3		T4	2
valid_sources[0x1f]	865	1			T21	2		T14	4		T3	2
valid_sources[0x20]	788	1			T7	1		T14	6		T3	4
valid_sources[0x21]	935	1			T7	1		T14	5		T3	8
valid_sources[0x22]	1168	1			T14	1		T3	4		T20	1
valid_sources[0x23]	754	1			T14	6		T3	2		T20	1
valid_sources[0x24]	880	1			T21	2		T14	1		T3	6
valid_sources[0x25]	940	1			T14	4		T3	7		T4	3
valid_sources[0x26]	766	1			T21	2		T14	3		T3	1
valid_sources[0x27]	1125	1			T14	1		T3	8		T20	1
valid_sources[0x28]	892	1			T14	3		T3	2		T4	1
valid_sources[0x29]	870	1			T14	4		T3	7		T4	1
valid_sources[0x2a]	1266	1			T21	3		T14	2		T3	2
valid_sources[0x2b]	970	1			T7	1		T14	2		T3	1
valid_sources[0x2c]	819	1			T7	1		T21	1		T3	4
valid_sources[0x2d]	1544	1			T5	6		T6	2		T7	1
valid_sources[0x2e]	996	1			T14	5		T20	1		T4	2
valid_sources[0x2f]	1511	1			T14	4		T3	8		T4	2
valid_sources[0x30]	970	1			T14	1		T3	5		T4	1
valid_sources[0x31]	871	1			T14	7		T3	4		T4	3
valid_sources[0x32]	1094	1			T14	8		T3	2		T4	3
valid_sources[0x33]	963	1			T7	1		T14	5		T3	5
valid_sources[0x34]	869	1			T14	5		T3	7		T4	2
valid_sources[0x35]	1106	1			T21	3		T14	4		T3	4
valid_sources[0x36]	1024	1			T7	1		T14	4		T3	3
valid_sources[0x37]	989	1			T14	3		T3	1		T20	2
valid_sources[0x38]	871	1			T14	2		T3	2		T20	1
valid_sources[0x39]	1861	1			T14	1		T3	4		T4	3
valid_sources[0x3a]	945	1			T21	1		T14	6		T20	1
valid_sources[0x3b]	905	1			T14	5		T4	1		T47	2
valid_sources[0x3c]	946	1			T7	1		T14	2		T3	3
valid_sources[0x3d]	914	1			T14	1		T3	1		T19	1
valid_sources[0x3e]	1186	1			T7	2		T14	6		T3	4
valid_sources[0x3f]	825	1			T6	3		T14	4		T4	1
valid_sources[0x40]	927	1			T14	5		T3	8		T4	2
valid_sources[0x41]	735	1			T14	6		T3	1		T4	5
valid_sources[0x42]	851	1			T14	7		T3	8		T20	2
valid_sources[0x43]	996	1			T7	1		T14	4		T3	4
valid_sources[0x44]	905	1			T21	1		T14	7		T19	1
valid_sources[0x45]	1109	1			T14	3		T3	4		T4	1
valid_sources[0x46]	829	1			T21	1		T14	2		T4	5
valid_sources[0x47]	767	1			T14	4		T3	3		T4	3
valid_sources[0x48]	904	1			T7	1		T21	1		T14	3
valid_sources[0x49]	885	1			T14	3		T3	3		T4	3
valid_sources[0x4a]	806	1			T14	4		T3	5		T20	1
valid_sources[0x4b]	989	1			T7	1		T14	3		T3	2
valid_sources[0x4c]	892	1			T14	2		T3	4		T4	7
valid_sources[0x4d]	796	1			T21	2		T14	4		T3	2
valid_sources[0x4e]	780	1			T14	1		T3	1		T4	3
valid_sources[0x4f]	1126	1			T14	1		T3	5		T4	3
valid_sources[0x50]	2195	1			T14	7		T3	3		T18	1
valid_sources[0x51]	1007	1			T14	5		T3	5		T16	26
valid_sources[0x52]	980	1			T1	4		T14	1		T3	3
valid_sources[0x53]	1237	1			T7	1		T14	5		T3	2
valid_sources[0x54]	987	1			T14	7		T3	4		T20	2
valid_sources[0x55]	1844	1			T14	4		T3	4		T4	1
valid_sources[0x56]	991	1			T1	2		T14	4		T3	2
valid_sources[0x57]	965	1			T7	2		T14	1		T3	3
valid_sources[0x58]	1424	1			T14	3		T3	6		T20	1
valid_sources[0x59]	1008	1			T14	6		T3	3		T19	1
valid_sources[0x5a]	1055	1			T14	3		T3	5		T4	5
valid_sources[0x5b]	693	1			T7	1		T14	3		T3	5
valid_sources[0x5c]	878	1			T14	9		T3	3		T4	3
valid_sources[0x5d]	1027	1			T7	1		T14	4		T3	4
valid_sources[0x5e]	1038	1			T7	1		T14	1		T3	8
valid_sources[0x5f]	1329	1			T14	2		T3	4		T4	1
valid_sources[0x60]	898	1			T21	1		T22	63		T14	2
valid_sources[0x61]	1739	1			T14	7		T3	3		T20	1
valid_sources[0x62]	836	1			T7	1		T14	3		T3	3
valid_sources[0x63]	2040	1			T7	1		T14	2		T3	5
valid_sources[0x64]	839	1			T14	1		T3	3		T56	1
valid_sources[0x65]	973	1			T14	3		T3	7		T19	1
valid_sources[0x66]	1084	1			T7	1		T14	4		T3	1
valid_sources[0x67]	891	1			T1	5		T14	7		T19	1
valid_sources[0x68]	887	1			T14	4		T3	2		T17	1
valid_sources[0x69]	1048	1			T14	3		T3	2		T20	2
valid_sources[0x6a]	994	1			T7	2		T21	3		T14	6
valid_sources[0x6b]	1114	1			T7	1		T14	3		T3	1
valid_sources[0x6c]	983	1			T14	3		T3	2		T20	1
valid_sources[0x6d]	944	1			T14	4		T3	1		T19	1
valid_sources[0x6e]	990	1			T14	4		T3	8		T20	1
valid_sources[0x6f]	872	1			T14	1		T3	2		T20	1
valid_sources[0x70]	839	1			T7	1		T14	3		T3	6
valid_sources[0x71]	1010	1			T6	2		T7	2		T1	2
valid_sources[0x72]	858	1			T7	1		T14	3		T3	4
valid_sources[0x73]	1826	1			T7	1		T14	3		T3	1
valid_sources[0x74]	822	1			T7	1		T14	1		T3	4
valid_sources[0x75]	1067	1			T14	2		T3	3		T20	1
valid_sources[0x76]	955	1			T14	2		T3	2		T19	1
valid_sources[0x77]	935	1			T7	1		T21	1		T14	6
valid_sources[0x78]	932	1			T14	2		T3	3		T20	1
valid_sources[0x79]	1313	1			T21	1		T14	1		T3	1
valid_sources[0x7a]	896	1			T14	2		T3	2		T20	2
valid_sources[0x7b]	1679	1			T14	2		T3	2		T20	1
valid_sources[0x7c]	1283	1			T14	2		T3	2		T4	2
valid_sources[0x7d]	830	1			T14	3		T3	7		T20	2
valid_sources[0x7e]	882	1			T5	7		T14	2		T4	3
valid_sources[0x7f]	786	1			T14	1		T3	4		T4	5
valid_sources[0x80]	857	1			T7	2		T14	2		T3	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61379

1

T5

4

T7

34

T21

1

values[0x0]

all_enables

biggest_size

30700

1

T5

5

T6

1

T7

7

values[0x1]

all_enables

biggest_size

21466

1

T5

2

T6

1

T7

10