Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	90.48		100.00	100.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T15,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T5,T15,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T15,T29,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T15,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T29,T49
0	1	Covered	T34,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T29,T49
0	1	Covered	T15,T29,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T29,T49
1	-	Covered	T15,T29,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T15,T29
DetectSt	168	Covered	T15,T29,T49
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T15,T29,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T29,T49
DebounceSt->IdleSt	163	Covered	T5,T44,T50
DetectSt->IdleSt	186	Covered	T34,T117
DetectSt->StableSt	191	Covered	T15,T29,T49
IdleSt->DebounceSt	148	Covered	T5,T15,T29
StableSt->IdleSt	206	Covered	T15,T29,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T15,T29
0	1	Covered	T5,T15,T29
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T29,T49
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T15,T29
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T29,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T44,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T15,T29
DetectSt	-	-	-	-	1	-	-	Covered	T34,T117
DetectSt	-	-	-	-	0	1	-	Covered	T15,T29,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T29,T49
StableSt	-	-	-	-	-	-	0	Covered	T15,T29,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	267	0	0
CntIncr_A	7107910	145011	0	0
CntNoWrap_A	7107910	6478228	0	0
DetectStDropOut_A	7107910	3	0	0
DetectedOut_A	7107910	796	0	0
DetectedPulseOut_A	7107910	118	0	0
DisabledIdleSt_A	7107910	6327164	0	0
DisabledNoDetection_A	7107910	6329460	0	0
EnterDebounceSt_A	7107910	150	0	0
EnterDetectSt_A	7107910	121	0	0
EnterStableSt_A	7107910	118	0	0
PulseIsPulse_A	7107910	118	0	0
StayInStableSt	7107910	678	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	6884	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	118	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	267	0	0
T1	1274	0	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T5	737	2	0	0
T6	837	0	0	0
T7	506	0	0	0
T14	13580	0	0	0
T15	751	2	0	0
T21	522	0	0	0
T22	522	0	0	0
T29	0	2	0	0
T34	0	10	0	0
T44	0	5	0	0
T45	0	4	0	0
T49	0	2	0	0
T50	0	3	0	0
T51	0	4	0	0
T52	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	145011	0	0
T1	1274	0	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T5	737	116	0	0
T6	837	0	0	0
T7	506	0	0	0
T14	13580	0	0	0
T15	751	69	0	0
T21	522	0	0	0
T22	522	0	0	0
T29	0	96	0	0
T34	0	340	0	0
T44	0	134	0	0
T45	0	80	0	0
T49	0	21	0	0
T50	0	148	0	0
T51	0	96	0	0
T52	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478228	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	334	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	348	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3	0	0
T34	38912	2	0	0
T42	735	0	0	0
T44	23649	0	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T117	0	1	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	796	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T8	483	0	0	0
T15	751	9	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	3	0	0
T34	0	18	0	0
T44	0	17	0	0
T45	0	14	0	0
T49	0	3	0	0
T50	0	8	0	0
T51	0	19	0	0
T126	0	9	0	0
T127	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	118	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T8	483	0	0	0
T15	751	1	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	1	0	0
T34	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T126	0	1	0	0
T127	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6327164	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	145	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	238	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6329460	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	145	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	239	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	150	0	0
T1	1274	0	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T5	737	2	0	0
T6	837	0	0	0
T7	506	0	0	0
T14	13580	0	0	0
T15	751	1	0	0
T21	522	0	0	0
T22	522	0	0	0
T29	0	1	0	0
T34	0	5	0	0
T44	0	3	0	0
T45	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	121	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T8	483	0	0	0
T15	751	1	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	1	0	0
T34	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T126	0	1	0	0
T127	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	118	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T8	483	0	0	0
T15	751	1	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	1	0	0
T34	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T126	0	1	0	0
T127	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	118	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T8	483	0	0	0
T15	751	1	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	1	0	0
T34	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T126	0	1	0	0
T127	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	678	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T8	483	0	0	0
T15	751	8	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	2	0	0
T34	0	15	0	0
T44	0	15	0	0
T45	0	12	0	0
T49	0	2	0	0
T50	0	7	0	0
T51	0	17	0	0
T126	0	8	0	0
T127	0	11	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6884	0	0
T1	1274	5	0	0
T2	15403	29	0	0
T3	13128	29	0	0
T5	737	3	0	0
T6	837	4	0	0
T7	506	4	0	0
T14	13580	26	0	0
T15	751	3	0	0
T21	522	6	0	0
T22	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	118	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T8	483	0	0	0
T15	751	1	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	1	0	0
T34	0	3	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T126	0	1	0	0
T127	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T12,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T12,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T12,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T26
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T12,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T26,T45
0	1	Covered	T1,T45,T59
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T26,T45
0	1	Unreachable
1	0	Covered	T12,T26,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T26
DetectSt	168	Covered	T1,T12,T26
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T12,T26,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T26
DebounceSt->IdleSt	163	Covered	T1,T60,T52
DetectSt->IdleSt	186	Covered	T1,T45,T59
DetectSt->StableSt	191	Covered	T12,T26,T45
IdleSt->DebounceSt	148	Covered	T1,T12,T26
StableSt->IdleSt	206	Covered	T12,T26,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T26
0	1	Covered	T1,T12,T26
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T26
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T26
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T60,T99
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T26
DetectSt	-	-	-	-	1	-	-	Covered	T1,T45,T59
DetectSt	-	-	-	-	0	1	-	Covered	T12,T26,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T26,T45
StableSt	-	-	-	-	-	-	0	Covered	T12,T26,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	186	0	0
CntIncr_A	7107910	128995	0	0
CntNoWrap_A	7107910	6478309	0	0
DetectStDropOut_A	7107910	22	0	0
DetectedOut_A	7107910	353582	0	0
DetectedPulseOut_A	7107910	49	0	0
DisabledIdleSt_A	7107910	5311593	0	0
DisabledNoDetection_A	7107910	5313934	0	0
EnterDebounceSt_A	7107910	115	0	0
EnterDetectSt_A	7107910	71	0	0
EnterStableSt_A	7107910	49	0	0
PulseIsPulse_A	7107910	49	0	0
StayInStableSt	7107910	353533	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	6884	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_sticky_sva.StableStDropOut_A	7107910	650404	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	186	0	0
T1	1274	8	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	4	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	2	0	0
T45	0	12	0	0
T52	0	2	0	0
T59	0	6	0	0
T60	0	7	0	0
T61	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	128995	0	0
T1	1274	175	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	120	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	68	0	0
T45	0	156	0	0
T52	0	56	0	0
T59	0	33	0	0
T60	0	320	0	0
T61	0	37761	0	0
T72	0	70	0	0
T73	0	41	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478309	0	0
T1	1274	865	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	22	0	0
T1	1274	3	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T45	0	4	0	0
T59	0	2	0	0
T60	0	2	0	0
T100	0	3	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	2	0	0
T136	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	353582	0	0
T12	1165	141	0	0
T13	3751	0	0	0
T26	0	193	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	272	0	0
T59	0	1	0	0
T60	0	163	0	0
T61	0	134307	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	8	0	0
T73	0	75	0	0
T88	402	0	0	0
T102	0	107	0	0
T128	0	190	0	0
T131	636	0	0	0
T132	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	49	0	0
T12	1165	2	0	0
T13	3751	0	0	0
T26	0	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T88	402	0	0	0
T102	0	2	0	0
T128	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5311593	0	0
T1	1274	29	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5313934	0	0
T1	1274	30	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	115	0	0
T1	1274	5	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	2	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T45	0	6	0	0
T52	0	2	0	0
T59	0	3	0	0
T60	0	4	0	0
T61	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	71	0	0
T1	1274	3	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	2	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T45	0	6	0	0
T59	0	3	0	0
T60	0	3	0	0
T61	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T128	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	49	0	0
T12	1165	2	0	0
T13	3751	0	0	0
T26	0	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T88	402	0	0	0
T102	0	2	0	0
T128	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	49	0	0
T12	1165	2	0	0
T13	3751	0	0	0
T26	0	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	2	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T88	402	0	0	0
T102	0	2	0	0
T128	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	353533	0	0
T12	1165	139	0	0
T13	3751	0	0	0
T26	0	192	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	270	0	0
T60	0	162	0	0
T61	0	134306	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	7	0	0
T73	0	74	0	0
T88	402	0	0	0
T102	0	105	0	0
T128	0	189	0	0
T129	0	336	0	0
T131	636	0	0	0
T132	426	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6884	0	0
T1	1274	5	0	0
T2	15403	29	0	0
T3	13128	29	0	0
T5	737	3	0	0
T6	837	4	0	0
T7	506	4	0	0
T14	13580	26	0	0
T15	751	3	0	0
T21	522	6	0	0
T22	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	650404	0	0
T12	1165	90	0	0
T13	3751	0	0	0
T26	0	52	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	319	0	0
T59	0	75	0	0
T60	0	123	0	0
T61	0	77	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	88	0	0
T73	0	119774	0	0
T88	402	0	0	0
T102	0	72	0	0
T128	0	171	0	0
T131	636	0	0	0
T132	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T6,T7,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T21
1	1	Covered	T6,T7,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T12,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T12,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T12,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T26
1	0	Covered	T6,T7,T21
1	1	Covered	T1,T12,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T26,T59
0	1	Covered	T12,T61,T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T26,T59
0	1	Unreachable
1	0	Covered	T1,T26,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T26
DetectSt	168	Covered	T1,T12,T26
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T26,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T26
DebounceSt->IdleSt	163	Covered	T45,T61,T52
DetectSt->IdleSt	186	Covered	T12,T61,T102
DetectSt->StableSt	191	Covered	T1,T26,T59
IdleSt->DebounceSt	148	Covered	T1,T12,T26
StableSt->IdleSt	206	Covered	T1,T26,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T26
0	1	Covered	T1,T12,T26
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T26
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T61,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T26
DetectSt	-	-	-	-	1	-	-	Covered	T12,T61,T102
DetectSt	-	-	-	-	0	1	-	Covered	T1,T26,T59
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T26,T59
StableSt	-	-	-	-	-	-	0	Covered	T1,T26,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	176	0	0
CntIncr_A	7107910	91917	0	0
CntNoWrap_A	7107910	6478319	0	0
DetectStDropOut_A	7107910	17	0	0
DetectedOut_A	7107910	221558	0	0
DetectedPulseOut_A	7107910	44	0	0
DisabledIdleSt_A	7107910	5311593	0	0
DisabledNoDetection_A	7107910	5313934	0	0
EnterDebounceSt_A	7107910	115	0	0
EnterDetectSt_A	7107910	61	0	0
EnterStableSt_A	7107910	44	0	0
PulseIsPulse_A	7107910	44	0	0
StayInStableSt	7107910	221514	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_sticky_sva.StableStDropOut_A	7107910	177528	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	176	0	0
T1	1274	2	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	6	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	2	0	0
T45	0	10	0	0
T52	0	2	0	0
T59	0	2	0	0
T60	0	4	0	0
T61	0	5	0	0
T72	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	91917	0	0
T1	1274	94	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	249	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	25	0	0
T45	0	535	0	0
T52	0	56	0	0
T59	0	37	0	0
T60	0	124	0	0
T61	0	63	0	0
T72	0	80	0	0
T73	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478319	0	0
T1	1274	871	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	17	0	0
T12	1165	3	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T61	0	2	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T88	402	0	0	0
T102	0	2	0	0
T129	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0
T137	0	3	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	3	0	0
T141	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	221558	0	0
T1	1274	616	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	50	0	0
T59	0	125	0	0
T60	0	455	0	0
T72	0	60	0	0
T73	0	119	0	0
T99	0	46	0	0
T128	0	242	0	0
T129	0	17	0	0
T130	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	44	0	0
T1	1274	1	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T99	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5311593	0	0
T1	1274	29	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5313934	0	0
T1	1274	30	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	115	0	0
T1	1274	1	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	3	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T45	0	10	0	0
T52	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	3	0	0
T72	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T1	1274	1	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	3	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T102	0	2	0	0
T128	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	44	0	0
T1	1274	1	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T99	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	44	0	0
T1	1274	1	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T59	0	1	0	0
T60	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T99	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	221514	0	0
T1	1274	615	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	49	0	0
T59	0	124	0	0
T60	0	453	0	0
T72	0	59	0	0
T73	0	118	0	0
T99	0	45	0	0
T128	0	241	0	0
T129	0	16	0	0
T130	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	177528	0	0
T1	1274	120	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	232	0	0
T59	0	90	0	0
T60	0	130	0	0
T72	0	28	0	0
T73	0	119694	0	0
T99	0	46	0	0
T128	0	121	0	0
T129	0	41	0	0
T130	0	321	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T6,T7,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T12,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T12,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T12,T26,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T26
1	0	Covered	T6,T7,T21
1	1	Covered	T1,T12,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T26,T45
0	1	Covered	T99,T100,T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T26,T45
0	1	Unreachable
1	0	Covered	T12,T26,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T12,T26
DetectSt	168	Covered	T12,T26,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T12,T26,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T26,T45
DebounceSt->IdleSt	163	Covered	T1,T52,T103
DetectSt->IdleSt	186	Covered	T99,T100,T101
DetectSt->StableSt	191	Covered	T12,T26,T45
IdleSt->DebounceSt	148	Covered	T1,T12,T26
StableSt->IdleSt	206	Covered	T12,T26,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T12,T26
0	1	Covered	T1,T12,T26
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T26,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T12,T26
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T26,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T103,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T12,T26
DetectSt	-	-	-	-	1	-	-	Covered	T99,T100,T101
DetectSt	-	-	-	-	0	1	-	Covered	T12,T26,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T26,T45
StableSt	-	-	-	-	-	-	0	Covered	T12,T26,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	158	0	0
CntIncr_A	7107910	88708	0	0
CntNoWrap_A	7107910	6478337	0	0
DetectStDropOut_A	7107910	7	0	0
DetectedOut_A	7107910	300937	0	0
DetectedPulseOut_A	7107910	52	0	0
DisabledIdleSt_A	7107910	5311593	0	0
DisabledNoDetection_A	7107910	5313934	0	0
EnterDebounceSt_A	7107910	99	0	0
EnterDetectSt_A	7107910	59	0	0
EnterStableSt_A	7107910	52	0	0
PulseIsPulse_A	7107910	52	0	0
StayInStableSt	7107910	300885	0	0
gen_high_event_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_sticky_sva.StableStDropOut_A	7107910	773721	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	158	0	0
T1	1274	5	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	4	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	2	0	0
T45	0	4	0	0
T52	0	2	0	0
T59	0	2	0	0
T60	0	4	0	0
T61	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	88708	0	0
T1	1274	80	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	194	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	10	0	0
T45	0	114	0	0
T52	0	57	0	0
T59	0	53	0	0
T60	0	114	0	0
T61	0	58	0	0
T72	0	26	0	0
T73	0	35784	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478337	0	0
T1	1274	868	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	7	0	0
T99	618	1	0	0
T100	0	2	0	0
T101	0	2	0	0
T130	6472	0	0	0
T137	1110	0	0	0
T142	0	2	0	0
T143	1771	0	0	0
T144	723	0	0	0
T145	417	0	0	0
T146	522	0	0	0
T147	423	0	0	0
T148	423	0	0	0
T149	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	300937	0	0
T12	1165	110	0	0
T13	3751	0	0	0
T26	0	14	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	754	0	0
T59	0	175	0	0
T60	0	406	0	0
T61	0	196	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	4	0	0
T73	0	84072	0	0
T88	402	0	0	0
T102	0	91	0	0
T128	0	317	0	0
T131	636	0	0	0
T132	426	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	52	0	0
T12	1165	2	0	0
T13	3751	0	0	0
T26	0	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T88	402	0	0	0
T102	0	2	0	0
T128	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5311593	0	0
T1	1274	29	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5313934	0	0
T1	1274	30	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	99	0	0
T1	1274	5	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T12	0	2	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T45	0	2	0	0
T52	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	59	0	0
T12	1165	2	0	0
T13	3751	0	0	0
T26	0	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T88	402	0	0	0
T102	0	2	0	0
T128	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	52	0	0
T12	1165	2	0	0
T13	3751	0	0	0
T26	0	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T88	402	0	0	0
T102	0	2	0	0
T128	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	52	0	0
T12	1165	2	0	0
T13	3751	0	0	0
T26	0	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	2	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T88	402	0	0	0
T102	0	2	0	0
T128	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	300885	0	0
T12	1165	108	0	0
T13	3751	0	0	0
T26	0	13	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	752	0	0
T59	0	174	0	0
T60	0	404	0	0
T61	0	195	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	3	0	0
T73	0	84071	0	0
T88	402	0	0	0
T102	0	89	0	0
T128	0	316	0	0
T131	636	0	0	0
T132	426	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	773721	0	0
T12	1165	57	0	0
T13	3751	0	0	0
T26	0	302	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T45	0	291	0	0
T59	0	41	0	0
T60	0	211	0	0
T61	0	171910	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T72	0	154	0	0
T73	0	35	0	0
T88	402	0	0	0
T102	0	118	0	0
T128	0	60	0	0
T131	636	0	0	0
T132	426	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T34,T44,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T34,T44,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T34,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T39,T34
1	0	Covered	T5,T6,T7
1	1	Covered	T34,T44,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T44,T45
0	1	Not Covered
1	0	Covered	T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T44,T45
0	1	Covered	T34,T45,T150
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T44,T45
1	-	Covered	T34,T45,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T44,T45
DetectSt	168	Covered	T34,T44,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T34,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T44,T45
DebounceSt->IdleSt	163	Covered	T151,T94
DetectSt->IdleSt	186	Covered	T52
DetectSt->StableSt	191	Covered	T34,T44,T45
IdleSt->DebounceSt	148	Covered	T34,T44,T45
StableSt->IdleSt	206	Covered	T34,T44,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T44,T45
0	1	Covered	T34,T44,T45
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T34,T44,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T44,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T44,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T151
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T44,T45
DetectSt	-	-	-	-	1	-	-	Covered	T52
DetectSt	-	-	-	-	0	1	-	Covered	T34,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T45,T150
StableSt	-	-	-	-	-	-	0	Covered	T34,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	86	0	0
CntIncr_A	7107910	107670	0	0
CntNoWrap_A	7107910	6478409	0	0
DetectStDropOut_A	7107910	0	0	0
DetectedOut_A	7107910	71614	0	0
DetectedPulseOut_A	7107910	41	0	0
DisabledIdleSt_A	7107910	6116019	0	0
DisabledNoDetection_A	7107910	6118308	0	0
EnterDebounceSt_A	7107910	44	0	0
EnterDetectSt_A	7107910	42	0	0
EnterStableSt_A	7107910	41	0	0
PulseIsPulse_A	7107910	41	0	0
StayInStableSt	7107910	71550	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	86	0	0
T34	38912	2	0	0
T42	735	0	0	0
T44	23649	2	0	0
T45	0	4	0	0
T52	0	2	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	2	0	0
T152	0	2	0	0
T153	0	4	0	0
T154	0	2	0	0
T155	0	4	0	0
T156	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	107670	0	0
T34	38912	95	0	0
T42	735	0	0	0
T44	23649	514	0	0
T45	0	68	0	0
T52	0	17	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	93	0	0
T152	0	37	0	0
T153	0	103	0	0
T154	0	36	0	0
T155	0	200	0	0
T156	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478409	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	71614	0	0
T34	38912	10	0	0
T42	735	0	0	0
T44	23649	38	0	0
T45	0	214	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	39	0	0
T152	0	39	0	0
T153	0	148	0	0
T154	0	114	0	0
T155	0	303	0	0
T156	0	83	0	0
T157	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	41	0	0
T34	38912	1	0	0
T42	735	0	0	0
T44	23649	1	0	0
T45	0	2	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6116019	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6118308	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	44	0	0
T34	38912	1	0	0
T42	735	0	0	0
T44	23649	1	0	0
T45	0	2	0	0
T52	0	1	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	42	0	0
T34	38912	1	0	0
T42	735	0	0	0
T44	23649	1	0	0
T45	0	2	0	0
T52	0	1	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	41	0	0
T34	38912	1	0	0
T42	735	0	0	0
T44	23649	1	0	0
T45	0	2	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	41	0	0
T34	38912	1	0	0
T42	735	0	0	0
T44	23649	1	0	0
T45	0	2	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	71550	0	0
T34	38912	9	0	0
T42	735	0	0	0
T44	23649	36	0	0
T45	0	211	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T150	0	38	0	0
T152	0	37	0	0
T153	0	144	0	0
T154	0	112	0	0
T155	0	300	0	0
T156	0	80	0	0
T157	0	46	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	18	0	0
T34	38912	1	0	0
T42	735	0	0	0
T44	23649	0	0	0
T45	0	1	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T133	0	1	0	0
T150	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T28,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T40
1	0	Covered	T7,T21,T22
1	1	Covered	T10,T28,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T34
0	1	Covered	T10,T133,T158
1	0	Covered	T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T34
0	1	Covered	T40,T34,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T40,T34
1	-	Covered	T40,T34,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T40
DetectSt	168	Covered	T10,T40,T34
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T40,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T40,T34
DebounceSt->IdleSt	163	Covered	T28,T112,T159
DetectSt->IdleSt	186	Covered	T10,T52,T133
DetectSt->StableSt	191	Covered	T10,T40,T34
IdleSt->DebounceSt	148	Covered	T10,T28,T40
StableSt->IdleSt	206	Covered	T10,T40,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T40,T34
0	1	Covered	T10,T28,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T40,T34
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T40,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T112,T159,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T40
DetectSt	-	-	-	-	1	-	-	Covered	T10,T52,T133
DetectSt	-	-	-	-	0	1	-	Covered	T10,T40,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T34,T45
StableSt	-	-	-	-	-	-	0	Covered	T10,T40,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	145	0	0
CntIncr_A	7107910	165764	0	0
CntNoWrap_A	7107910	6478350	0	0
DetectStDropOut_A	7107910	4	0	0
DetectedOut_A	7107910	5479	0	0
DetectedPulseOut_A	7107910	65	0	0
DisabledIdleSt_A	7107910	6079124	0	0
DisabledNoDetection_A	7107910	6081409	0	0
EnterDebounceSt_A	7107910	76	0	0
EnterDetectSt_A	7107910	70	0	0
EnterStableSt_A	7107910	65	0	0
PulseIsPulse_A	7107910	65	0	0
StayInStableSt	7107910	5387	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	2525	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	145	0	0
T10	6167	4	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	4	0	0
T38	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T45	0	4	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	4	0	0
T153	0	2	0	0
T163	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	165764	0	0
T10	6167	72	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	55	0	0
T33	18496	0	0	0
T34	0	190	0	0
T38	0	55	0	0
T40	0	144	0	0
T41	0	41	0	0
T45	0	170	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	120	0	0
T153	0	50	0	0
T163	0	130	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478350	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	4	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T133	0	1	0	0
T158	0	1	0	0
T164	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5479	0	0
T10	6167	38	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	88	0	0
T38	0	276	0	0
T40	0	78	0	0
T41	0	84	0	0
T45	0	74	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	78	0	0
T153	0	21	0	0
T154	0	43	0	0
T163	0	147	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	65	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T163	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6079124	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6081409	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	76	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	1	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	2	0	0
T153	0	1	0	0
T163	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	70	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	2	0	0
T153	0	1	0	0
T163	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	65	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T163	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	65	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	2	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T163	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5387	0	0
T10	6167	36	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	85	0	0
T38	0	274	0	0
T40	0	75	0	0
T41	0	83	0	0
T45	0	72	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	75	0	0
T153	0	20	0	0
T154	0	42	0	0
T163	0	144	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	2525	0	0
T1	1274	0	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T7	506	6	0	0
T10	0	17	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	5	0	0
T17	422	1	0	0
T18	0	3	0	0
T19	0	4	0	0
T20	0	4	0	0
T21	522	4	0	0
T22	522	6	0	0
T54	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	38	0	0
T34	0	1	0	0
T36	23875	0	0	0
T40	1075	1	0	0
T41	0	1	0	0
T43	1977	0	0	0
T45	0	2	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T150	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0
T163	0	1	0	0
T165	502	0	0	0