Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T39,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T13,T39,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T39,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T13,T39,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T45
0	1	Covered	T166
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T45
0	1	Covered	T13,T39,T153
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T39,T45
1	-	Covered	T13,T39,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T39,T45
DetectSt	168	Covered	T13,T39,T45
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T39,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T39,T45
DebounceSt->IdleSt	163	Covered	T163,T94
DetectSt->IdleSt	186	Covered	T166
DetectSt->StableSt	191	Covered	T13,T39,T45
IdleSt->DebounceSt	148	Covered	T13,T39,T45
StableSt->IdleSt	206	Covered	T13,T39,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T39,T45
0	1	Covered	T13,T39,T45
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T39,T45
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T39,T45
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T39,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T163
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T39,T45
DetectSt	-	-	-	-	1	-	-	Covered	T166
DetectSt	-	-	-	-	0	1	-	Covered	T13,T39,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T39,T153
StableSt	-	-	-	-	-	-	0	Covered	T13,T39,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	104	0	0
CntIncr_A	7107910	199116	0	0
CntNoWrap_A	7107910	6478391	0	0
DetectStDropOut_A	7107910	1	0	0
DetectedOut_A	7107910	163857	0	0
DetectedPulseOut_A	7107910	50	0	0
DisabledIdleSt_A	7107910	5891060	0	0
DisabledNoDetection_A	7107910	5893342	0	0
EnterDebounceSt_A	7107910	53	0	0
EnterDetectSt_A	7107910	51	0	0
EnterStableSt_A	7107910	50	0	0
PulseIsPulse_A	7107910	50	0	0
StayInStableSt	7107910	163779	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	104	0	0
T13	3751	4	0	0
T33	18496	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T45	0	2	0	0
T52	0	2	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	4	0	0
T154	0	2	0	0
T163	0	1	0	0
T166	0	4	0	0
T167	745	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	199116	0	0
T13	3751	132	0	0
T33	18496	0	0	0
T37	0	65	0	0
T38	0	55	0	0
T39	0	72	0	0
T45	0	85	0	0
T52	0	17	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	100	0	0
T154	0	36	0	0
T163	0	65	0	0
T166	0	138	0	0
T167	745	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478391	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1	0	0
T166	1042	1	0	0
T168	494	0	0	0
T169	18997	0	0	0
T170	402	0	0	0
T171	555	0	0	0
T172	732	0	0	0
T173	5468	0	0	0
T174	583	0	0	0
T175	423	0	0	0
T176	641	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	163857	0	0
T13	3751	161	0	0
T33	18496	0	0	0
T37	0	42	0	0
T38	0	100	0	0
T39	0	43	0	0
T45	0	170	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	249	0	0
T154	0	174	0	0
T156	0	189	0	0
T166	0	144	0	0
T167	745	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	50	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T167	745	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5891060	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5893342	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	53	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T163	0	1	0	0
T166	0	2	0	0
T167	745	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	51	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T156	0	1	0	0
T166	0	2	0	0
T167	745	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	50	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T167	745	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	50	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T154	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T167	745	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	163779	0	0
T13	3751	158	0	0
T33	18496	0	0	0
T37	0	40	0	0
T38	0	98	0	0
T39	0	42	0	0
T45	0	168	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	192	0	0
T153	0	246	0	0
T154	0	173	0	0
T156	0	188	0	0
T166	0	142	0	0
T167	745	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	21	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T39	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T112	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T159	0	1	0	0
T167	745	0	0	0
T177	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T28,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T40
1	0	Covered	T7,T21,T22
1	1	Covered	T10,T28,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T43
0	1	Covered	T177,T178,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T43
0	1	Covered	T40,T44,T42
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T40,T43
1	-	Covered	T40,T44,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T40
DetectSt	168	Covered	T10,T40,T43
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T40,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T40,T43
DebounceSt->IdleSt	163	Covered	T28,T151,T112
DetectSt->IdleSt	186	Covered	T177,T178,T179
DetectSt->StableSt	191	Covered	T10,T40,T43
IdleSt->DebounceSt	148	Covered	T10,T28,T40
StableSt->IdleSt	206	Covered	T10,T40,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T40,T43
0	1	Covered	T10,T28,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T40,T43
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T40,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T112,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T40
DetectSt	-	-	-	-	1	-	-	Covered	T177,T178,T179
DetectSt	-	-	-	-	0	1	-	Covered	T10,T40,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T44,T42
StableSt	-	-	-	-	-	-	0	Covered	T10,T40,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	115	0	0
CntIncr_A	7107910	151580	0	0
CntNoWrap_A	7107910	6478380	0	0
DetectStDropOut_A	7107910	3	0	0
DetectedOut_A	7107910	20437	0	0
DetectedPulseOut_A	7107910	52	0	0
DisabledIdleSt_A	7107910	6193212	0	0
DisabledNoDetection_A	7107910	6195507	0	0
EnterDebounceSt_A	7107910	61	0	0
EnterDetectSt_A	7107910	55	0	0
EnterStableSt_A	7107910	52	0	0
PulseIsPulse_A	7107910	52	0	0
StayInStableSt	7107910	20364	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	2873	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	115	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	2	0	0
T153	0	6	0	0
T163	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	151580	0	0
T10	6167	36	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	54	0	0
T33	18496	0	0	0
T38	0	55	0	0
T40	0	72	0	0
T42	0	46	0	0
T43	0	73	0	0
T44	0	514	0	0
T45	0	85	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	37	0	0
T163	0	130	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478380	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3	0	0
T134	1222	0	0	0
T177	7675	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T181	404	0	0	0
T182	10258	0	0	0
T183	4509	0	0	0
T184	9782	0	0	0
T185	501	0	0	0
T186	1493	0	0	0
T187	502	0	0	0
T188	2827	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	20437	0	0
T10	6167	123	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	40	0	0
T40	0	42	0	0
T42	0	25	0	0
T43	0	45	0	0
T44	0	249	0	0
T45	0	40	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	28	0	0
T153	0	100	0	0
T163	0	214	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	52	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T163	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6193212	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6195507	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	1	0	0
T33	18496	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T163	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	55	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T163	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	52	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T163	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	52	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T163	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	20364	0	0
T10	6167	121	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	39	0	0
T40	0	41	0	0
T42	0	24	0	0
T43	0	43	0	0
T44	0	248	0	0
T45	0	39	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	27	0	0
T153	0	97	0	0
T163	0	211	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	2873	0	0
T1	1274	0	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T7	506	4	0	0
T10	0	15	0	0
T14	13580	0	0	0
T15	751	0	0	0
T16	521	4	0	0
T17	422	4	0	0
T18	0	4	0	0
T19	0	5	0	0
T20	0	6	0	0
T21	522	5	0	0
T22	522	6	0	0
T56	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	30	0	0
T36	23875	0	0	0
T38	0	1	0	0
T40	1075	1	0	0
T42	0	1	0	0
T43	1977	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T154	0	1	0	0
T163	0	1	0	0
T165	502	0	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T6,T7,T21

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T21
1	1	Covered	T6,T7,T21

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T40,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T40,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T40,T44
1	0	Covered	T6,T7,T21
1	1	Covered	T10,T40,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T44
0	1	Covered	T133,T160,T190
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T40,T44
0	1	Covered	T10,T40,T45
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T40,T44
1	-	Covered	T10,T40,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T40,T44
DetectSt	168	Covered	T10,T40,T44
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T40,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T40,T44
DebounceSt->IdleSt	163	Covered	T191,T94,T192
DetectSt->IdleSt	186	Covered	T133,T160,T190
DetectSt->StableSt	191	Covered	T10,T40,T44
IdleSt->DebounceSt	148	Covered	T10,T40,T44
StableSt->IdleSt	206	Covered	T10,T40,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T40,T44
0	1	Covered	T10,T40,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T40,T44
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T40,T44
IdleSt	0	-	-	-	-	-	-	Covered	T6,T7,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T40,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T191,T192,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T40,T44
DetectSt	-	-	-	-	1	-	-	Covered	T133,T160,T190
DetectSt	-	-	-	-	0	1	-	Covered	T10,T40,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T10,T40,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	128	0	0
CntIncr_A	7107910	178215	0	0
CntNoWrap_A	7107910	6478367	0	0
DetectStDropOut_A	7107910	4	0	0
DetectedOut_A	7107910	5113	0	0
DetectedPulseOut_A	7107910	57	0	0
DisabledIdleSt_A	7107910	6151456	0	0
DisabledNoDetection_A	7107910	6153754	0	0
EnterDebounceSt_A	7107910	67	0	0
EnterDetectSt_A	7107910	61	0	0
EnterStableSt_A	7107910	57	0	0
PulseIsPulse_A	7107910	57	0	0
StayInStableSt	7107910	5031	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	128	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	2	0	0
T153	0	6	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	178215	0	0
T10	6167	36	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	65	0	0
T40	0	144	0	0
T41	0	41	0	0
T44	0	514	0	0
T45	0	85	0	0
T48	12421	0	0	0
T52	0	17	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	37	0	0
T153	0	153	0	0
T189	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478367	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	4	0	0
T115	21055	0	0	0
T133	2729	1	0	0
T160	0	2	0	0
T190	0	1	0	0
T193	3485	0	0	0
T194	673	0	0	0
T195	424	0	0	0
T196	421	0	0	0
T197	587	0	0	0
T198	454	0	0	0
T199	402	0	0	0
T200	946	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5113	0	0
T10	6167	85	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	26	0	0
T40	0	64	0	0
T41	0	85	0	0
T44	0	39	0	0
T45	0	41	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	105	0	0
T153	0	310	0	0
T189	0	247	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	57	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6151456	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6153754	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	67	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	57	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	57	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	1	0	0
T153	0	3	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5031	0	0
T10	6167	84	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	25	0	0
T40	0	62	0	0
T41	0	84	0	0
T44	0	37	0	0
T45	0	40	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T152	0	103	0	0
T153	0	306	0	0
T189	0	246	0	0
T201	0	102	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	31	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T103	0	1	0	0
T151	0	1	0	0
T153	0	2	0	0
T189	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T7,T21
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T21
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T42,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T40,T42,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T42,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T40,T43
1	0	Covered	T6,T7,T21
1	1	Covered	T40,T42,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T42,T41
0	1	Covered	T40,T154,T156
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T42,T41
1	-	Covered	T40,T154,T156

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T42,T41
DetectSt	168	Covered	T40,T42,T41
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T40,T42,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T42,T41
DebounceSt->IdleSt	163	Covered	T38,T203,T94
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T40,T42,T41
IdleSt->DebounceSt	148	Covered	T40,T42,T41
StableSt->IdleSt	206	Covered	T40,T52,T154

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T42,T41
0	1	Covered	T40,T42,T41
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T42,T41
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T42,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T42,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T42,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T40,T42,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T52,T154
StableSt	-	-	-	-	-	-	0	Covered	T40,T42,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	93	0	0
CntIncr_A	7107910	129074	0	0
CntNoWrap_A	7107910	6478402	0	0
DetectStDropOut_A	7107910	0	0	0
DetectedOut_A	7107910	56457	0	0
DetectedPulseOut_A	7107910	45	0	0
DisabledIdleSt_A	7107910	6127920	0	0
DisabledNoDetection_A	7107910	6130204	0	0
EnterDebounceSt_A	7107910	48	0	0
EnterDetectSt_A	7107910	45	0	0
EnterStableSt_A	7107910	45	0	0
PulseIsPulse_A	7107910	45	0	0
StayInStableSt	7107910	56391	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	6395	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	93	0	0
T36	23875	0	0	0
T38	0	1	0	0
T40	1075	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	1977	0	0	0
T52	0	2	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	2	0	0
T154	0	4	0	0
T156	0	2	0	0
T165	502	0	0	0
T189	0	2	0	0
T202	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	129074	0	0
T36	23875	0	0	0
T38	0	55	0	0
T40	1075	144	0	0
T41	0	41	0	0
T42	0	46	0	0
T43	1977	0	0	0
T52	0	17	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	29	0	0
T154	0	72	0	0
T156	0	29	0	0
T165	502	0	0	0
T189	0	72	0	0
T202	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478402	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	56457	0	0
T36	23875	0	0	0
T40	1075	80	0	0
T41	0	202	0	0
T42	0	38	0	0
T43	1977	0	0	0
T52	0	2	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	70	0	0
T154	0	86	0	0
T156	0	76	0	0
T165	502	0	0	0
T189	0	40	0	0
T202	0	69	0	0
T204	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	45	0	0
T36	23875	0	0	0
T40	1075	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	1977	0	0	0
T52	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T165	502	0	0	0
T189	0	1	0	0
T202	0	1	0	0
T204	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6127920	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6130204	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	48	0	0
T36	23875	0	0	0
T38	0	1	0	0
T40	1075	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	1977	0	0	0
T52	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T165	502	0	0	0
T189	0	1	0	0
T202	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	45	0	0
T36	23875	0	0	0
T40	1075	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	1977	0	0	0
T52	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T165	502	0	0	0
T189	0	1	0	0
T202	0	1	0	0
T204	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	45	0	0
T36	23875	0	0	0
T40	1075	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	1977	0	0	0
T52	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T165	502	0	0	0
T189	0	1	0	0
T202	0	1	0	0
T204	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	45	0	0
T36	23875	0	0	0
T40	1075	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	1977	0	0	0
T52	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T165	502	0	0	0
T189	0	1	0	0
T202	0	1	0	0
T204	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	56391	0	0
T36	23875	0	0	0
T40	1075	77	0	0
T41	0	200	0	0
T42	0	36	0	0
T43	1977	0	0	0
T52	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T151	0	68	0	0
T154	0	83	0	0
T156	0	75	0	0
T165	502	0	0	0
T189	0	38	0	0
T202	0	67	0	0
T204	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6395	0	0
T1	1274	5	0	0
T2	15403	31	0	0
T3	13128	34	0	0
T6	837	4	0	0
T7	506	4	0	0
T14	13580	24	0	0
T15	751	0	0	0
T16	521	5	0	0
T18	0	2	0	0
T21	522	4	0	0
T22	522	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	23	0	0
T36	23875	0	0	0
T40	1075	1	0	0
T43	1977	0	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T101	0	1	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T133	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T160	0	1	0	0
T165	502	0	0	0
T178	0	1	0	0
T191	0	1	0	0
T205	0	1	0	0
T206	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T21,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T21,T22
1	1	Covered	T7,T21,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T28,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T39
1	0	Covered	T7,T21,T22
1	1	Covered	T10,T28,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T39,T40
0	1	Covered	T34,T38
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T39,T40
0	1	Covered	T39,T40,T45
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T39,T40
1	-	Covered	T39,T40,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T39
DetectSt	168	Covered	T10,T39,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T39,T40
DebounceSt->IdleSt	163	Covered	T28,T45,T41
DetectSt->IdleSt	186	Covered	T34,T38
DetectSt->StableSt	191	Covered	T10,T39,T40
IdleSt->DebounceSt	148	Covered	T10,T28,T39
StableSt->IdleSt	206	Covered	T10,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T39,T40
0	1	Covered	T10,T28,T39
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T39,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T39
IdleSt	0	-	-	-	-	-	-	Covered	T7,T21,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T45,T41,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T39
DetectSt	-	-	-	-	1	-	-	Covered	T34,T38
DetectSt	-	-	-	-	0	1	-	Covered	T10,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T40,T45
StableSt	-	-	-	-	-	-	0	Covered	T10,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	133	0	0
CntIncr_A	7107910	83985	0	0
CntNoWrap_A	7107910	6478362	0	0
DetectStDropOut_A	7107910	2	0	0
DetectedOut_A	7107910	22543	0	0
DetectedPulseOut_A	7107910	61	0	0
DisabledIdleSt_A	7107910	6058044	0	0
DisabledNoDetection_A	7107910	6060332	0	0
EnterDebounceSt_A	7107910	71	0	0
EnterDetectSt_A	7107910	63	0	0
EnterStableSt_A	7107910	61	0	0
PulseIsPulse_A	7107910	61	0	0
StayInStableSt	7107910	22457	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	133	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	4	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	5	0	0
T45	0	5	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	6	0	0
T163	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	83985	0	0
T10	6167	36	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	54	0	0
T33	18496	0	0	0
T34	0	190	0	0
T38	0	55	0	0
T39	0	144	0	0
T40	0	144	0	0
T41	0	123	0	0
T45	0	153	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	153	0	0
T163	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478362	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	2	0	0
T34	38912	1	0	0
T38	0	1	0	0
T42	735	0	0	0
T44	23649	0	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	22543	0	0
T10	6167	161	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	48	0	0
T39	0	60	0	0
T40	0	331	0	0
T41	0	45	0	0
T45	0	416	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	247	0	0
T163	0	64	0	0
T166	0	313	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	0	2	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	3	0	0
T163	0	1	0	0
T166	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6058044	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6060332	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	71	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	1	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	3	0	0
T45	0	3	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	3	0	0
T163	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	63	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	0	2	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	3	0	0
T163	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	0	2	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	3	0	0
T163	0	1	0	0
T166	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	0	2	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	3	0	0
T163	0	1	0	0
T166	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	22457	0	0
T10	6167	159	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	46	0	0
T39	0	57	0	0
T40	0	329	0	0
T41	0	42	0	0
T45	0	413	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	244	0	0
T163	0	62	0	0
T166	0	310	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	35	0	0
T26	3078	0	0	0
T27	490	0	0	0
T39	810	1	0	0
T40	1075	2	0	0
T41	0	1	0	0
T45	0	1	0	0
T49	676	0	0	0
T57	65601	0	0	0
T89	406	0	0	0
T125	483	0	0	0
T150	0	1	0	0
T153	0	3	0	0
T154	0	1	0	0
T155	0	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T207	546	0	0	0
T208	425	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T21,T22
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T21,T22
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T13,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T13,T39
1	0	Covered	T7,T21,T22
1	1	Covered	T13,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T40
0	1	Covered	T178
1	0	Covered	T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T40
0	1	Covered	T13,T39,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T39,T40
1	-	Covered	T13,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T39,T40
DetectSt	168	Covered	T13,T39,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T39,T40
DebounceSt->IdleSt	163	Covered	T209,T94
DetectSt->IdleSt	186	Covered	T52,T178
DetectSt->StableSt	191	Covered	T13,T39,T40
IdleSt->DebounceSt	148	Covered	T13,T39,T40
StableSt->IdleSt	206	Covered	T13,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T39,T40
0	1	Covered	T13,T39,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T39,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T209
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T52,T178
DetectSt	-	-	-	-	0	1	-	Covered	T13,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T13,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	78	0	0
CntIncr_A	7107910	7018	0	0
CntNoWrap_A	7107910	6478417	0	0
DetectStDropOut_A	7107910	1	0	0
DetectedOut_A	7107910	6241	0	0
DetectedPulseOut_A	7107910	36	0	0
DisabledIdleSt_A	7107910	6438718	0	0
DisabledNoDetection_A	7107910	6441009	0	0
EnterDebounceSt_A	7107910	40	0	0
EnterDetectSt_A	7107910	38	0	0
EnterStableSt_A	7107910	36	0	0
PulseIsPulse_A	7107910	36	0	0
StayInStableSt	7107910	6187	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	6025	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	78	0	0
T13	3751	6	0	0
T33	18496	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	4	0	0
T52	0	2	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	6	0	0
T166	0	2	0	0
T167	745	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	7018	0	0
T13	3751	196	0	0
T33	18496	0	0	0
T38	0	55	0	0
T39	0	72	0	0
T40	0	144	0	0
T42	0	46	0	0
T44	0	514	0	0
T45	0	130	0	0
T52	0	17	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	153	0	0
T166	0	69	0	0
T167	745	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478417	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1	0	0
T101	13298	0	0	0
T178	7628	1	0	0
T210	15660	0	0	0
T211	1315	0	0	0
T212	508	0	0	0
T213	447	0	0	0
T214	14743	0	0	0
T215	450	0	0	0
T216	422	0	0	0
T217	674	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6241	0	0
T13	3751	534	0	0
T33	18496	0	0	0
T38	0	43	0	0
T39	0	122	0	0
T40	0	44	0	0
T42	0	110	0	0
T44	0	553	0	0
T45	0	86	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T150	0	44	0	0
T153	0	190	0	0
T166	0	111	0	0
T167	745	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	36	0	0
T13	3751	3	0	0
T33	18496	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T150	0	1	0	0
T153	0	3	0	0
T166	0	1	0	0
T167	745	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6438718	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6441009	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	40	0	0
T13	3751	3	0	0
T33	18496	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	3	0	0
T166	0	1	0	0
T167	745	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	38	0	0
T13	3751	3	0	0
T33	18496	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	3	0	0
T166	0	1	0	0
T167	745	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	36	0	0
T13	3751	3	0	0
T33	18496	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T150	0	1	0	0
T153	0	3	0	0
T166	0	1	0	0
T167	745	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	36	0	0
T13	3751	3	0	0
T33	18496	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	2	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T150	0	1	0	0
T153	0	3	0	0
T166	0	1	0	0
T167	745	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6187	0	0
T13	3751	530	0	0
T33	18496	0	0	0
T38	0	41	0	0
T39	0	121	0	0
T40	0	41	0	0
T42	0	108	0	0
T44	0	551	0	0
T45	0	82	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T150	0	43	0	0
T153	0	185	0	0
T166	0	110	0	0
T167	745	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6025	0	0
T1	1274	0	0	0
T2	15403	24	0	0
T3	13128	32	0	0
T7	506	3	0	0
T14	13580	31	0	0
T15	751	0	0	0
T16	521	6	0	0
T17	422	4	0	0
T18	0	3	0	0
T19	0	6	0	0
T21	522	4	0	0
T22	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	18	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T156	0	1	0	0
T166	0	1	0	0
T167	745	0	0	0
T205	0	1	0	0
T218	0	1	0	0