Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T21,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T21,T22
1	1	Covered	T7,T21,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T28,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T13
1	0	Covered	T7,T21,T22
1	1	Covered	T10,T28,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T34
0	1	Covered	T219
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T34
0	1	Covered	T10,T13,T34
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T13,T34
1	-	Covered	T10,T13,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T13
DetectSt	168	Covered	T10,T13,T34
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T13,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T13,T34
DebounceSt->IdleSt	163	Covered	T28,T13,T163
DetectSt->IdleSt	186	Covered	T219
DetectSt->StableSt	191	Covered	T10,T13,T34
IdleSt->DebounceSt	148	Covered	T10,T28,T13
StableSt->IdleSt	206	Covered	T10,T13,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T13,T34
0	1	Covered	T10,T28,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T34
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T13
IdleSt	0	-	-	-	-	-	-	Covered	T7,T21,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T13,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T163,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T13
DetectSt	-	-	-	-	1	-	-	Covered	T219
DetectSt	-	-	-	-	0	1	-	Covered	T10,T13,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T13,T34
StableSt	-	-	-	-	-	-	0	Covered	T10,T13,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	133	0	0
CntIncr_A	7107910	100246	0	0
CntNoWrap_A	7107910	6478362	0	0
DetectStDropOut_A	7107910	1	0	0
DetectedOut_A	7107910	106678	0	0
DetectedPulseOut_A	7107910	61	0	0
DisabledIdleSt_A	7107910	6211152	0	0
DisabledNoDetection_A	7107910	6213443	0	0
EnterDebounceSt_A	7107910	72	0	0
EnterDetectSt_A	7107910	62	0	0
EnterStableSt_A	7107910	61	0	0
PulseIsPulse_A	7107910	61	0	0
StayInStableSt	7107910	106591	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	133	0	0
T10	6167	4	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	7	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T41	0	4	0	0
T44	0	4	0	0
T45	0	2	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T163	0	2	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	100246	0	0
T10	6167	72	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	260	0	0
T28	2151	54	0	0
T33	18496	0	0	0
T34	0	95	0	0
T38	0	55	0	0
T41	0	82	0	0
T44	0	1028	0	0
T45	0	34	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T163	0	130	0	0
T189	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478362	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1	0	0
T97	15787	0	0	0
T159	319949	0	0	0
T206	34073	0	0	0
T219	17025	1	0	0
T221	454	0	0	0
T222	486	0	0	0
T223	492	0	0	0
T224	275548	0	0	0
T225	8404	0	0	0
T226	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	106678	0	0
T10	6167	116	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	191	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	460	0	0
T38	0	24	0	0
T41	0	119	0	0
T44	0	844	0	0
T45	0	102	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T166	0	112	0	0
T189	0	174	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T166	0	1	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6211152	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6213443	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	72	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	4	0	0
T28	2151	1	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T163	0	2	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	62	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T166	0	1	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T166	0	1	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T166	0	1	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	106591	0	0
T10	6167	113	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	187	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	459	0	0
T38	0	23	0	0
T41	0	117	0	0
T44	0	841	0	0
T45	0	101	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T166	0	111	0	0
T189	0	173	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	34	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	2	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T150	0	1	0	0
T166	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T21,T22
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T21,T22
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T13,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T44,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T43
1	0	Covered	T7,T21,T22
1	1	Covered	T10,T13,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T41,T38
0	1	Covered	T44
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T41,T38
0	1	Covered	T13,T41,T156
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T41,T38
1	-	Covered	T13,T41,T156

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T13,T44
DetectSt	168	Covered	T13,T44,T41
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T41,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T44,T41
DebounceSt->IdleSt	163	Covered	T10,T94
DetectSt->IdleSt	186	Covered	T44
DetectSt->StableSt	191	Covered	T13,T41,T38
IdleSt->DebounceSt	148	Covered	T10,T13,T44
StableSt->IdleSt	206	Covered	T13,T41,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T13,T44
0	1	Covered	T10,T13,T44
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T44,T41
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T13,T44
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T44,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T10
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T13,T44
DetectSt	-	-	-	-	1	-	-	Covered	T44
DetectSt	-	-	-	-	0	1	-	Covered	T13,T41,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T41,T52
StableSt	-	-	-	-	-	-	0	Covered	T13,T41,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	62	0	0
CntIncr_A	7107910	118526	0	0
CntNoWrap_A	7107910	6478433	0	0
DetectStDropOut_A	7107910	1	0	0
DetectedOut_A	7107910	21215	0	0
DetectedPulseOut_A	7107910	29	0	0
DisabledIdleSt_A	7107910	6150780	0	0
DisabledNoDetection_A	7107910	6153077	0	0
EnterDebounceSt_A	7107910	32	0	0
EnterDetectSt_A	7107910	30	0	0
EnterStableSt_A	7107910	29	0	0
PulseIsPulse_A	7107910	29	0	0
StayInStableSt	7107910	21172	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	6036	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	62	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	2	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	2	0	0
T41	0	4	0	0
T44	0	2	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T151	0	2	0	0
T156	0	2	0	0
T205	0	2	0	0
T218	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	118526	0	0
T10	6167	36	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	64	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	55	0	0
T41	0	82	0	0
T44	0	514	0	0
T48	12421	0	0	0
T52	0	17	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T151	0	29	0	0
T156	0	29	0	0
T205	0	89	0	0
T218	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478433	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1	0	0
T42	735	0	0	0
T44	23649	1	0	0
T45	19610	0	0	0
T71	23293	0	0	0
T104	5016	0	0	0
T120	676	0	0	0
T121	13980	0	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	21215	0	0
T13	3751	145	0	0
T33	18496	0	0	0
T38	0	195	0	0
T41	0	126	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T101	0	37	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	140	0	0
T156	0	44	0	0
T167	745	0	0	0
T178	0	174	0	0
T205	0	226	0	0
T218	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	29	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T101	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	1	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T205	0	1	0	0
T218	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6150780	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6153077	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	32	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T151	0	1	0	0
T156	0	1	0	0
T205	0	1	0	0
T218	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	30	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T44	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	1	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T205	0	1	0	0
T218	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	29	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T101	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	1	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T205	0	1	0	0
T218	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	29	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T38	0	1	0	0
T41	0	2	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T101	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	1	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T205	0	1	0	0
T218	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	21172	0	0
T13	3751	144	0	0
T33	18496	0	0	0
T38	0	193	0	0
T41	0	123	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T101	0	36	0	0
T131	636	0	0	0
T132	426	0	0	0
T151	0	138	0	0
T156	0	43	0	0
T167	745	0	0	0
T178	0	171	0	0
T205	0	225	0	0
T218	0	27	0	0
T219	0	159	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6036	0	0
T1	1274	0	0	0
T2	15403	28	0	0
T3	13128	27	0	0
T7	506	5	0	0
T14	13580	31	0	0
T15	751	0	0	0
T16	521	2	0	0
T17	422	4	0	0
T18	0	3	0	0
T19	0	6	0	0
T21	522	3	0	0
T22	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	14	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T41	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T101	0	1	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T7,T21,T22

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T7,T21,T22
1	1	Covered	T7,T21,T22

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T28,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T13
1	0	Covered	T7,T21,T22
1	1	Covered	T10,T28,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T40
0	1	Covered	T41,T205,T227
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T40,T43
0	1	Covered	T10,T13,T40
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T40,T43
1	-	Covered	T10,T13,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T13
DetectSt	168	Covered	T10,T13,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T13,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T13,T40
DebounceSt->IdleSt	163	Covered	T10,T28,T151
DetectSt->IdleSt	186	Covered	T41,T205,T227
DetectSt->StableSt	191	Covered	T10,T13,T40
IdleSt->DebounceSt	148	Covered	T10,T28,T13
StableSt->IdleSt	206	Covered	T10,T13,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T13,T40
0	1	Covered	T10,T28,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T13
IdleSt	0	-	-	-	-	-	-	Covered	T7,T21,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T13,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T151,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T13
DetectSt	-	-	-	-	1	-	-	Covered	T41,T205,T227
DetectSt	-	-	-	-	0	1	-	Covered	T10,T13,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T13,T40
StableSt	-	-	-	-	-	-	0	Covered	T13,T40,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	141	0	0
CntIncr_A	7107910	182402	0	0
CntNoWrap_A	7107910	6478354	0	0
DetectStDropOut_A	7107910	3	0	0
DetectedOut_A	7107910	190535	0	0
DetectedPulseOut_A	7107910	64	0	0
DisabledIdleSt_A	7107910	5813652	0	0
DisabledNoDetection_A	7107910	5815941	0	0
EnterDebounceSt_A	7107910	75	0	0
EnterDetectSt_A	7107910	67	0	0
EnterStableSt_A	7107910	64	0	0
PulseIsPulse_A	7107910	64	0	0
StayInStableSt	7107910	190446	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	141	0	0
T10	6167	3	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	6	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T41	0	6	0	0
T43	0	2	0	0
T44	0	4	0	0
T45	0	2	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	182402	0	0
T10	6167	72	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	194	0	0
T28	2151	54	0	0
T33	18496	0	0	0
T34	0	95	0	0
T37	0	65	0	0
T40	0	144	0	0
T41	0	123	0	0
T43	0	73	0	0
T44	0	1028	0	0
T45	0	85	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478354	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3	0	0
T35	20676	0	0	0
T37	609	0	0	0
T41	822	1	0	0
T59	698	0	0	0
T105	15176	0	0	0
T205	0	1	0	0
T227	0	1	0	0
T228	453	0	0	0
T229	426	0	0	0
T230	35491	0	0	0
T231	22850	0	0	0
T232	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	190535	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	368	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	139	0	0
T37	0	27	0	0
T38	0	177	0	0
T40	0	44	0	0
T41	0	44	0	0
T43	0	134	0	0
T44	0	288	0	0
T45	0	30	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	64	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5813652	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5815941	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	75	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	1	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	67	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	64	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	64	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	190446	0	0
T13	3751	365	0	0
T33	18496	0	0	0
T34	0	138	0	0
T37	0	26	0	0
T38	0	176	0	0
T40	0	41	0	0
T41	0	41	0	0
T43	0	132	0	0
T44	0	285	0	0
T45	0	29	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T167	745	0	0	0
T189	0	173	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	38	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T21,T22
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T21,T22
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T13,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T13,T39
1	0	Covered	T7,T21,T22
1	1	Covered	T13,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T40
0	1	Covered	T205
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T39,T40
0	1	Covered	T13,T40,T44
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T39,T40
1	-	Covered	T13,T40,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T39,T40
DetectSt	168	Covered	T13,T39,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T39,T40
DebounceSt->IdleSt	163	Covered	T94,T233
DetectSt->IdleSt	186	Covered	T205
DetectSt->StableSt	191	Covered	T13,T39,T40
IdleSt->DebounceSt	148	Covered	T13,T39,T40
StableSt->IdleSt	206	Covered	T13,T40,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T39,T40
0	1	Covered	T13,T39,T40
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T39,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T233
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T205
DetectSt	-	-	-	-	0	1	-	Covered	T13,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T40,T44
StableSt	-	-	-	-	-	-	0	Covered	T13,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	80	0	0
CntIncr_A	7107910	67755	0	0
CntNoWrap_A	7107910	6478415	0	0
DetectStDropOut_A	7107910	1	0	0
DetectedOut_A	7107910	123118	0	0
DetectedPulseOut_A	7107910	38	0	0
DisabledIdleSt_A	7107910	6054825	0	0
DisabledNoDetection_A	7107910	6057110	0	0
EnterDebounceSt_A	7107910	41	0	0
EnterDetectSt_A	7107910	39	0	0
EnterStableSt_A	7107910	38	0	0
PulseIsPulse_A	7107910	38	0	0
StayInStableSt	7107910	123060	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	6086	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	80	0	0
T13	3751	4	0	0
T33	18496	0	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	0	8	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	4	0	0
T163	0	2	0	0
T167	745	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	67755	0	0
T13	3751	128	0	0
T33	18496	0	0	0
T34	0	95	0	0
T38	0	55	0	0
T39	0	72	0	0
T40	0	72	0	0
T42	0	46	0	0
T44	0	514	0	0
T45	0	198	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	100	0	0
T163	0	65	0	0
T167	745	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478415	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1	0	0
T205	1080	1	0	0
T234	508	0	0	0
T235	413	0	0	0
T236	503	0	0	0
T237	19990	0	0	0
T238	422	0	0	0
T239	15405	0	0	0
T240	42981	0	0	0
T241	2612	0	0	0
T242	40829	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	123118	0	0
T13	3751	253	0	0
T33	18496	0	0	0
T34	0	368	0	0
T38	0	43	0	0
T39	0	234	0	0
T40	0	173	0	0
T42	0	197	0	0
T44	0	555	0	0
T45	0	425	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	102	0	0
T163	0	173	0	0
T167	745	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	38	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	4	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T163	0	1	0	0
T167	745	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6054825	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6057110	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	41	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	4	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T163	0	1	0	0
T167	745	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	39	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	4	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T163	0	1	0	0
T167	745	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	38	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	4	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T163	0	1	0	0
T167	745	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	38	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	4	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	2	0	0
T163	0	1	0	0
T167	745	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	123060	0	0
T13	3751	250	0	0
T33	18496	0	0	0
T34	0	366	0	0
T38	0	41	0	0
T39	0	232	0	0
T40	0	172	0	0
T42	0	195	0	0
T44	0	554	0	0
T45	0	418	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	99	0	0
T163	0	171	0	0
T167	745	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6086	0	0
T1	1274	0	0	0
T2	15403	23	0	0
T3	13128	34	0	0
T7	506	6	0	0
T14	13580	33	0	0
T15	751	0	0	0
T16	521	6	0	0
T17	422	2	0	0
T18	0	2	0	0
T19	0	7	0	0
T21	522	4	0	0
T22	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	17	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T40	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T153	0	1	0	0
T159	0	1	0	0
T166	0	1	0	0
T167	745	0	0	0
T177	0	1	0	0
T205	0	1	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T10,T28,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T10,T13,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T13
1	0	Covered	T5,T6,T7
1	1	Covered	T10,T28,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T40
0	1	Covered	T38,T243,T244
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T40
0	1	Covered	T40,T42,T45
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T13,T40
1	-	Covered	T40,T42,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T13
DetectSt	168	Covered	T10,T13,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T10,T13,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T13,T40
DebounceSt->IdleSt	163	Covered	T28,T13,T156
DetectSt->IdleSt	186	Covered	T38,T243,T244
DetectSt->StableSt	191	Covered	T10,T13,T40
IdleSt->DebounceSt	148	Covered	T10,T28,T13
StableSt->IdleSt	206	Covered	T10,T13,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T13,T40
0	1	Covered	T10,T28,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T13,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T13,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T156,T245
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T13
DetectSt	-	-	-	-	1	-	-	Covered	T38,T243,T244
DetectSt	-	-	-	-	0	1	-	Covered	T10,T13,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T42,T45
StableSt	-	-	-	-	-	-	0	Covered	T10,T13,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	141	0	0
CntIncr_A	7107910	125818	0	0
CntNoWrap_A	7107910	6478354	0	0
DetectStDropOut_A	7107910	3	0	0
DetectedOut_A	7107910	134312	0	0
DetectedPulseOut_A	7107910	64	0	0
DisabledIdleSt_A	7107910	5832609	0	0
DisabledNoDetection_A	7107910	5834893	0	0
EnterDebounceSt_A	7107910	75	0	0
EnterDetectSt_A	7107910	67	0	0
EnterStableSt_A	7107910	64	0	0
PulseIsPulse_A	7107910	64	0	0
StayInStableSt	7107910	134215	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	141	0	0
T10	6167	2	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	3	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	4	0	0
T45	0	8	0	0
T48	12421	0	0	0
T52	0	2	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	4	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	125818	0	0
T10	6167	36	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	128	0	0
T28	2151	55	0	0
T33	18496	0	0	0
T38	0	55	0	0
T40	0	72	0	0
T41	0	82	0	0
T42	0	92	0	0
T45	0	198	0	0
T48	12421	0	0	0
T52	0	17	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	103	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478354	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3	0	0
T38	740	1	0	0
T51	739	0	0	0
T73	120332	0	0	0
T109	5766	0	0	0
T153	31873	0	0	0
T189	841	0	0	0
T243	0	1	0	0
T244	0	1	0	0
T246	15340	0	0	0
T247	409	0	0	0
T248	496	0	0	0
T249	802	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	134312	0	0
T10	6167	39	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	53	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T40	0	122	0	0
T41	0	44	0	0
T42	0	77	0	0
T45	0	793	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	221	0	0
T166	0	564	0	0
T176	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	64	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	2	0	0
T166	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5832609	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5834893	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	75	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	2	0	0
T28	2151	1	0	0
T33	18496	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	67	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	2	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	64	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	2	0	0
T166	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	64	0	0
T10	6167	1	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	1	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	4	0	0
T48	12421	0	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	2	0	0
T166	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	134215	0	0
T10	6167	37	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	51	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T40	0	121	0	0
T41	0	41	0	0
T42	0	74	0	0
T45	0	786	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T67	422	0	0	0
T153	0	217	0	0
T154	0	112	0	0
T166	0	562	0	0
T176	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	30	0	0
T36	23875	0	0	0
T40	1075	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	1977	0	0	0
T45	0	1	0	0
T55	39872	0	0	0
T58	20539	0	0	0
T87	2110	0	0	0
T118	29218	0	0	0
T119	422	0	0	0
T125	483	0	0	0
T155	0	2	0	0
T158	0	1	0	0
T165	502	0	0	0
T178	0	1	0	0
T205	0	2	0	0
T219	0	1	0	0
T222	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T34,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T13,T34,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T13,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T39,T34
1	0	Covered	T5,T6,T7
1	1	Covered	T13,T34,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T37,T38
0	1	Covered	T219,T79
1	0	Covered	T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T37,T38
0	1	Covered	T13,T156,T205
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T37,T38
1	-	Covered	T13,T156,T205

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T34,T37
DetectSt	168	Covered	T13,T37,T38
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T13,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T37,T38
DebounceSt->IdleSt	163	Covered	T34,T94
DetectSt->IdleSt	186	Covered	T52,T219,T79
DetectSt->StableSt	191	Covered	T13,T37,T38
IdleSt->DebounceSt	148	Covered	T13,T34,T37
StableSt->IdleSt	206	Covered	T13,T156,T205

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T34,T37
0	1	Covered	T13,T34,T37
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T37,T38
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T34,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T94
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T34
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T34,T37
DetectSt	-	-	-	-	1	-	-	Covered	T52,T219,T79
DetectSt	-	-	-	-	0	1	-	Covered	T13,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T156,T205
StableSt	-	-	-	-	-	-	0	Covered	T13,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	80	0	0
CntIncr_A	7107910	2621	0	0
CntNoWrap_A	7107910	6478415	0	0
DetectStDropOut_A	7107910	2	0	0
DetectedOut_A	7107910	3141	0	0
DetectedPulseOut_A	7107910	36	0	0
DisabledIdleSt_A	7107910	6206432	0	0
DisabledNoDetection_A	7107910	6208712	0	0
EnterDebounceSt_A	7107910	41	0	0
EnterDetectSt_A	7107910	39	0	0
EnterStableSt_A	7107910	36	0	0
PulseIsPulse_A	7107910	36	0	0
StayInStableSt	7107910	3086	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7107910	6884	0	0
gen_low_level_sva.LowLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	80	0	0
T13	3751	4	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T52	0	2	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	2	0	0
T167	745	0	0	0
T178	0	4	0	0
T203	0	4	0	0
T205	0	4	0	0
T245	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	2621	0	0
T13	3751	130	0	0
T33	18496	0	0	0
T34	0	95	0	0
T37	0	65	0	0
T38	0	55	0	0
T52	0	17	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	29	0	0
T167	745	0	0	0
T178	0	167	0	0
T203	0	116	0	0
T205	0	178	0	0
T245	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6478415	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	2	0	0
T79	0	1	0	0
T97	15787	0	0	0
T159	319949	0	0	0
T206	34073	0	0	0
T219	17025	1	0	0
T221	454	0	0	0
T222	486	0	0	0
T223	492	0	0	0
T224	275548	0	0	0
T225	8404	0	0	0
T226	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3141	0	0
T13	3751	211	0	0
T33	18496	0	0	0
T37	0	42	0	0
T38	0	43	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	188	0	0
T167	745	0	0	0
T178	0	165	0	0
T203	0	95	0	0
T205	0	87	0	0
T224	0	94	0	0
T245	0	49	0	0
T250	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	36	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T203	0	2	0	0
T205	0	2	0	0
T224	0	1	0	0
T245	0	1	0	0
T250	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6206432	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6208712	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	41	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T203	0	2	0	0
T205	0	2	0	0
T245	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	39	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T52	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T203	0	2	0	0
T205	0	2	0	0
T245	0	1	0	0
T250	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	36	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T203	0	2	0	0
T205	0	2	0	0
T224	0	1	0	0
T245	0	1	0	0
T250	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	36	0	0
T13	3751	2	0	0
T33	18496	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	1	0	0
T167	745	0	0	0
T178	0	2	0	0
T203	0	2	0	0
T205	0	2	0	0
T224	0	1	0	0
T245	0	1	0	0
T250	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3086	0	0
T13	3751	208	0	0
T33	18496	0	0	0
T37	0	40	0	0
T38	0	41	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	187	0	0
T167	745	0	0	0
T178	0	162	0	0
T203	0	93	0	0
T205	0	84	0	0
T224	0	93	0	0
T245	0	47	0	0
T250	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6884	0	0
T1	1274	5	0	0
T2	15403	29	0	0
T3	13128	29	0	0
T5	737	3	0	0
T6	837	4	0	0
T7	506	4	0	0
T14	13580	26	0	0
T15	751	3	0	0
T21	522	6	0	0
T22	522	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	17	0	0
T13	3751	1	0	0
T33	18496	0	0	0
T67	422	0	0	0
T68	3566	0	0	0
T69	15630	0	0	0
T70	9939	0	0	0
T88	402	0	0	0
T131	636	0	0	0
T132	426	0	0	0
T156	0	1	0	0
T160	0	1	0	0
T167	745	0	0	0
T178	0	1	0	0
T191	0	1	0	0
T203	0	2	0	0
T205	0	1	0	0
T206	0	3	0	0
T224	0	1	0	0
T251	0	1	0	0