Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T14,T2,T3
1	1	Covered	T14,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T3
0	1	Covered	T47,T48,T104
1	0	Covered	T2,T48,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T3,T9
0	1	Covered	T14,T3,T9
1	0	Covered	T52,T96,T94

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T3,T9
1	-	Covered	T14,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T3
DetectSt	168	Covered	T14,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T3
DebounceSt->IdleSt	163	Covered	T52,T252,T253
DetectSt->IdleSt	186	Covered	T2,T47,T48
DetectSt->StableSt	191	Covered	T14,T3,T9
IdleSt->DebounceSt	148	Covered	T14,T2,T3
StableSt->IdleSt	206	Covered	T14,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T3
0	1	Covered	T14,T2,T3
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T47,T48
DetectSt	-	-	-	-	0	1	-	Covered	T14,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T14,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T14,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	2951	0	0
CntIncr_A	7107910	117693	0	0
CntNoWrap_A	7107910	6475544	0	0
DetectStDropOut_A	7107910	407	0	0
DetectedOut_A	7107910	76267	0	0
DetectedPulseOut_A	7107910	849	0	0
DisabledIdleSt_A	7107910	5972229	0	0
DisabledNoDetection_A	7107910	5974370	0	0
EnterDebounceSt_A	7107910	1490	0	0
EnterDetectSt_A	7107910	1462	0	0
EnterStableSt_A	7107910	849	0	0
PulseIsPulse_A	7107910	849	0	0
StayInStableSt	7107910	75308	0	0
gen_high_event_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	725	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	2951	0	0
T2	15403	16	0	0
T3	13128	44	0	0
T4	35865	0	0	0
T9	0	42	0	0
T14	13580	50	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	28	0	0
T47	0	26	0	0
T48	0	50	0	0
T69	0	18	0	0
T70	0	4	0	0
T71	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	117693	0	0
T2	15403	404	0	0
T3	13128	1100	0	0
T4	35865	0	0	0
T9	0	1386	0	0
T14	13580	1275	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	840	0	0
T47	0	852	0	0
T48	0	1349	0	0
T69	0	477	0	0
T70	0	120	0	0
T71	0	592	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6475544	0	0
T1	1274	873	0	0
T2	15403	14963	0	0
T3	13128	12666	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13107	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	407	0	0
T10	6167	0	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T47	5919	13	0	0
T48	12421	19	0	0
T52	0	1	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T104	0	28	0	0
T105	0	5	0	0
T106	0	3	0	0
T107	0	9	0	0
T108	0	16	0	0
T109	0	25	0	0
T110	0	27	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	76267	0	0
T2	15403	0	0	0
T3	13128	302	0	0
T4	35865	0	0	0
T9	0	2924	0	0
T14	13580	1847	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	147	0	0
T69	0	377	0	0
T70	0	42	0	0
T231	0	2341	0	0
T254	0	83	0	0
T255	0	1226	0	0
T256	0	1789	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	849	0	0
T2	15403	0	0	0
T3	13128	22	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	25	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	14	0	0
T69	0	9	0	0
T70	0	2	0	0
T231	0	28	0	0
T254	0	1	0	0
T255	0	19	0	0
T256	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5972229	0	0
T1	1274	873	0	0
T2	15403	12247	0	0
T3	13128	9536	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	8365	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5974370	0	0
T1	1274	874	0	0
T2	15403	12251	0	0
T3	13128	9539	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	8366	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1490	0	0
T2	15403	8	0	0
T3	13128	22	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	25	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	14	0	0
T47	0	13	0	0
T48	0	25	0	0
T69	0	9	0	0
T70	0	2	0	0
T71	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1462	0	0
T2	15403	8	0	0
T3	13128	22	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	25	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	14	0	0
T47	0	13	0	0
T48	0	25	0	0
T69	0	9	0	0
T70	0	2	0	0
T71	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	849	0	0
T2	15403	0	0	0
T3	13128	22	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	25	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	14	0	0
T69	0	9	0	0
T70	0	2	0	0
T231	0	28	0	0
T254	0	1	0	0
T255	0	19	0	0
T256	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	849	0	0
T2	15403	0	0	0
T3	13128	22	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	25	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	14	0	0
T69	0	9	0	0
T70	0	2	0	0
T231	0	28	0	0
T254	0	1	0	0
T255	0	19	0	0
T256	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	75308	0	0
T2	15403	0	0	0
T3	13128	280	0	0
T4	35865	0	0	0
T9	0	2894	0	0
T14	13580	1820	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	133	0	0
T69	0	368	0	0
T70	0	40	0	0
T231	0	2308	0	0
T254	0	81	0	0
T255	0	1207	0	0
T256	0	1776	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	725	0	0
T2	15403	0	0	0
T3	13128	22	0	0
T4	35865	0	0	0
T9	0	12	0	0
T14	13580	23	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	14	0	0
T69	0	9	0	0
T70	0	2	0	0
T231	0	23	0	0
T255	0	19	0	0
T256	0	13	0	0
T257	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T14,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T3,T4
1	0	Covered	T14,T2,T3
1	1	Covered	T14,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T3,T4
0	1	Covered	T36,T58,T45
1	0	Covered	T52,T94

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T3,T4
0	1	Covered	T3,T4,T8
1	0	Covered	T94

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T3,T4
1	-	Covered	T3,T4,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T3,T4
DetectSt	168	Covered	T14,T3,T4
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T3,T4
DebounceSt->IdleSt	163	Covered	T14,T46,T11
DetectSt->IdleSt	186	Covered	T36,T58,T45
DetectSt->StableSt	191	Covered	T14,T3,T4
IdleSt->DebounceSt	148	Covered	T14,T3,T4
StableSt->IdleSt	206	Covered	T14,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T3,T4
0	1	Covered	T14,T3,T4
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T3,T4
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T14,T46,T11
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T36,T58,T45
DetectSt	-	-	-	-	0	1	-	Covered	T14,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T14,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T3,T4,T8
StableSt	-	-	-	-	-	-	0	Covered	T14,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	994	0	0
CntIncr_A	7107910	50833	0	0
CntNoWrap_A	7107910	6477501	0	0
DetectStDropOut_A	7107910	63	0	0
DetectedOut_A	7107910	17355	0	0
DetectedPulseOut_A	7107910	394	0	0
DisabledIdleSt_A	7107910	6069149	0	0
DisabledNoDetection_A	7107910	6070712	0	0
EnterDebounceSt_A	7107910	536	0	0
EnterDetectSt_A	7107910	461	0	0
EnterStableSt_A	7107910	394	0	0
PulseIsPulse_A	7107910	394	0	0
StayInStableSt	7107910	16928	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	360	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	994	0	0
T2	15403	0	0	0
T3	13128	2	0	0
T4	35865	4	0	0
T8	0	2	0	0
T9	0	10	0	0
T10	0	2	0	0
T11	0	7	0	0
T14	13580	5	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	2	0	0
T46	0	8	0	0
T54	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	50833	0	0
T2	15403	0	0	0
T3	13128	56	0	0
T4	35865	198	0	0
T8	0	25	0	0
T9	0	320	0	0
T10	0	25	0	0
T11	0	515	0	0
T14	13580	143	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	25	0	0
T46	0	521	0	0
T54	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6477501	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12708	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13152	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	63	0	0
T34	38912	0	0	0
T36	23875	4	0	0
T43	1977	0	0	0
T44	23649	0	0	0
T45	0	4	0	0
T52	0	1	0	0
T58	20539	4	0	0
T71	23293	0	0	0
T87	2110	0	0	0
T111	0	9	0	0
T112	0	1	0	0
T113	0	4	0	0
T114	0	1	0	0
T115	0	11	0	0
T116	0	2	0	0
T118	29218	0	0	0
T119	422	0	0	0
T120	676	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	17355	0	0
T2	15403	0	0	0
T3	13128	59	0	0
T4	35865	172	0	0
T8	0	3	0	0
T9	0	391	0	0
T10	0	3	0	0
T11	0	69	0	0
T14	13580	177	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	3	0	0
T46	0	18	0	0
T125	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	394	0	0
T2	15403	0	0	0
T3	13128	1	0	0
T4	35865	2	0	0
T8	0	1	0	0
T9	0	5	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	13580	2	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T46	0	3	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6069149	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12408	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	11312	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6070712	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12412	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	11314	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	536	0	0
T2	15403	0	0	0
T3	13128	1	0	0
T4	35865	2	0	0
T8	0	1	0	0
T9	0	5	0	0
T10	0	1	0	0
T11	0	4	0	0
T14	13580	3	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T46	0	5	0	0
T54	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	461	0	0
T2	15403	0	0	0
T3	13128	1	0	0
T4	35865	2	0	0
T8	0	1	0	0
T9	0	5	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	13580	2	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T46	0	3	0	0
T125	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	394	0	0
T2	15403	0	0	0
T3	13128	1	0	0
T4	35865	2	0	0
T8	0	1	0	0
T9	0	5	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	13580	2	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T46	0	3	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	394	0	0
T2	15403	0	0	0
T3	13128	1	0	0
T4	35865	2	0	0
T8	0	1	0	0
T9	0	5	0	0
T10	0	1	0	0
T11	0	3	0	0
T14	13580	2	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T46	0	3	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	16928	0	0
T2	15403	0	0	0
T3	13128	58	0	0
T4	35865	170	0	0
T8	0	2	0	0
T9	0	383	0	0
T10	0	2	0	0
T11	0	66	0	0
T14	13580	173	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	2	0	0
T46	0	15	0	0
T125	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	360	0	0
T3	13128	1	0	0
T4	35865	2	0	0
T8	483	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T11	0	3	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T26	0	1	0	0
T29	36296	0	0	0
T46	0	3	0	0
T84	405	0	0	0
T118	0	8	0	0
T125	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T14,T2,T3
1	1	Covered	T14,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T3
0	1	Covered	T47,T48,T104
1	0	Covered	T14,T48,T105

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
1	0	Covered	T258

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T9
1	-	Covered	T2,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T3
DetectSt	168	Covered	T14,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T3
DebounceSt->IdleSt	163	Covered	T52,T252,T253
DetectSt->IdleSt	186	Covered	T14,T47,T48
DetectSt->StableSt	191	Covered	T2,T3,T9
IdleSt->DebounceSt	148	Covered	T14,T2,T3
StableSt->IdleSt	206	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T3
0	1	Covered	T14,T2,T3
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T14,T47,T48
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	3006	0	0
CntIncr_A	7107910	123933	0	0
CntNoWrap_A	7107910	6475489	0	0
DetectStDropOut_A	7107910	394	0	0
DetectedOut_A	7107910	81527	0	0
DetectedPulseOut_A	7107910	847	0	0
DisabledIdleSt_A	7107910	5964525	0	0
DisabledNoDetection_A	7107910	5966682	0	0
EnterDebounceSt_A	7107910	1518	0	0
EnterDetectSt_A	7107910	1489	0	0
EnterStableSt_A	7107910	847	0	0
PulseIsPulse_A	7107910	847	0	0
StayInStableSt	7107910	80586	0	0
gen_high_event_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	752	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3006	0	0
T2	15403	44	0	0
T3	13128	60	0	0
T4	35865	0	0	0
T9	0	18	0	0
T14	13580	16	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	24	0	0
T47	0	42	0	0
T48	0	62	0	0
T69	0	26	0	0
T70	0	28	0	0
T71	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	123933	0	0
T2	15403	1056	0	0
T3	13128	1140	0	0
T4	35865	0	0	0
T9	0	702	0	0
T14	13580	469	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	564	0	0
T47	0	1392	0	0
T48	0	1682	0	0
T69	0	1092	0	0
T70	0	1022	0	0
T71	0	912	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6475489	0	0
T1	1274	873	0	0
T2	15403	14935	0	0
T3	13128	12650	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13141	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	394	0	0
T10	6167	0	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T13	3751	0	0	0
T28	2151	0	0	0
T33	18496	0	0	0
T47	5919	21	0	0
T48	12421	25	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T104	0	12	0	0
T105	0	5	0	0
T106	0	12	0	0
T107	0	9	0	0
T108	0	6	0	0
T109	0	16	0	0
T257	0	8	0	0
T259	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	81527	0	0
T2	15403	1573	0	0
T3	13128	1417	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	771	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	436	0	0
T69	0	475	0	0
T70	0	1118	0	0
T71	0	1697	0	0
T230	0	1617	0	0
T231	0	1202	0	0
T255	0	1609	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	847	0	0
T2	15403	22	0	0
T3	13128	30	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	9	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	12	0	0
T69	0	13	0	0
T70	0	14	0	0
T71	0	12	0	0
T230	0	13	0	0
T231	0	24	0	0
T255	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5964525	0	0
T1	1274	873	0	0
T2	15403	10726	0	0
T3	13128	8825	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	10038	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5966682	0	0
T1	1274	874	0	0
T2	15403	10727	0	0
T3	13128	8826	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	10041	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1518	0	0
T2	15403	22	0	0
T3	13128	30	0	0
T4	35865	0	0	0
T9	0	9	0	0
T14	13580	8	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	12	0	0
T47	0	21	0	0
T48	0	31	0	0
T69	0	13	0	0
T70	0	14	0	0
T71	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1489	0	0
T2	15403	22	0	0
T3	13128	30	0	0
T4	35865	0	0	0
T9	0	9	0	0
T14	13580	8	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	12	0	0
T47	0	21	0	0
T48	0	31	0	0
T69	0	13	0	0
T70	0	14	0	0
T71	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	847	0	0
T2	15403	22	0	0
T3	13128	30	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	9	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	12	0	0
T69	0	13	0	0
T70	0	14	0	0
T71	0	12	0	0
T230	0	13	0	0
T231	0	24	0	0
T255	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	847	0	0
T2	15403	22	0	0
T3	13128	30	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	9	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	12	0	0
T69	0	13	0	0
T70	0	14	0	0
T71	0	12	0	0
T230	0	13	0	0
T231	0	24	0	0
T255	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	80586	0	0
T2	15403	1548	0	0
T3	13128	1385	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	762	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	423	0	0
T69	0	461	0	0
T70	0	1104	0	0
T71	0	1682	0	0
T230	0	1599	0	0
T231	0	1174	0	0
T255	0	1581	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	752	0	0
T2	15403	19	0	0
T3	13128	28	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	9	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	11	0	0
T69	0	12	0	0
T70	0	14	0	0
T71	0	9	0	0
T230	0	8	0	0
T231	0	20	0	0
T255	0	28	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T14,T2,T3
1	1	Covered	T2,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T46,T58,T45
1	0	Covered	T52,T94

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T4,T11,T33
1	0	Covered	T96,T94

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T4,T11,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T4
DetectSt	168	Covered	T2,T3,T4
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T4
DebounceSt->IdleSt	163	Covered	T46,T55,T44
DetectSt->IdleSt	186	Covered	T46,T58,T45
DetectSt->StableSt	191	Covered	T2,T3,T4
IdleSt->DebounceSt	148	Covered	T2,T3,T4
StableSt->IdleSt	206	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T55,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T46,T58,T45
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T4,T11,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	840	0	0
CntIncr_A	7107910	50003	0	0
CntNoWrap_A	7107910	6477655	0	0
DetectStDropOut_A	7107910	61	0	0
DetectedOut_A	7107910	13288	0	0
DetectedPulseOut_A	7107910	331	0	0
DisabledIdleSt_A	7107910	6066273	0	0
DisabledNoDetection_A	7107910	6067903	0	0
EnterDebounceSt_A	7107910	446	0	0
EnterDetectSt_A	7107910	397	0	0
EnterStableSt_A	7107910	331	0	0
PulseIsPulse_A	7107910	331	0	0
StayInStableSt	7107910	12921	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	840	0	0
T2	15403	6	0	0
T3	13128	4	0	0
T4	35865	10	0	0
T8	483	0	0	0
T11	0	6	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	2	0	0
T46	0	13	0	0
T55	0	29	0	0
T69	0	2	0	0
T70	0	14	0	0
T118	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	50003	0	0
T2	15403	240	0	0
T3	13128	82	0	0
T4	35865	850	0	0
T8	483	0	0	0
T11	0	351	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	48	0	0
T46	0	905	0	0
T55	0	1902	0	0
T69	0	64	0	0
T70	0	392	0	0
T118	0	248	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6477655	0	0
T1	1274	873	0	0
T2	15403	14973	0	0
T3	13128	12706	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	61	0	0
T9	28549	0	0	0
T10	6167	0	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T28	2151	0	0	0
T45	0	3	0	0
T46	12086	6	0	0
T47	5919	0	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T58	0	1	0	0
T112	0	1	0	0
T113	0	5	0	0
T114	0	2	0	0
T116	0	1	0	0
T260	0	7	0	0
T261	0	6	0	0
T262	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	13288	0	0
T2	15403	189	0	0
T3	13128	145	0	0
T4	35865	77	0	0
T8	483	0	0	0
T11	0	160	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	96	0	0
T34	0	199	0	0
T55	0	801	0	0
T69	0	103	0	0
T70	0	362	0	0
T118	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	331	0	0
T2	15403	3	0	0
T3	13128	2	0	0
T4	35865	5	0	0
T8	483	0	0	0
T11	0	3	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	1	0	0
T34	0	6	0	0
T55	0	14	0	0
T69	0	1	0	0
T70	0	7	0	0
T118	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6066273	0	0
T1	1274	873	0	0
T2	15403	13409	0	0
T3	13128	11295	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6067903	0	0
T1	1274	874	0	0
T2	15403	13411	0	0
T3	13128	11297	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	446	0	0
T2	15403	3	0	0
T3	13128	2	0	0
T4	35865	5	0	0
T8	483	0	0	0
T11	0	3	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	1	0	0
T46	0	7	0	0
T55	0	15	0	0
T69	0	1	0	0
T70	0	7	0	0
T118	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	397	0	0
T2	15403	3	0	0
T3	13128	2	0	0
T4	35865	5	0	0
T8	483	0	0	0
T11	0	3	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	1	0	0
T46	0	6	0	0
T55	0	14	0	0
T69	0	1	0	0
T70	0	7	0	0
T118	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	331	0	0
T2	15403	3	0	0
T3	13128	2	0	0
T4	35865	5	0	0
T8	483	0	0	0
T11	0	3	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	1	0	0
T34	0	6	0	0
T55	0	14	0	0
T69	0	1	0	0
T70	0	7	0	0
T118	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	331	0	0
T2	15403	3	0	0
T3	13128	2	0	0
T4	35865	5	0	0
T8	483	0	0	0
T11	0	3	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	1	0	0
T34	0	6	0	0
T55	0	14	0	0
T69	0	1	0	0
T70	0	7	0	0
T118	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	12921	0	0
T2	15403	183	0	0
T3	13128	141	0	0
T4	35865	72	0	0
T8	483	0	0	0
T11	0	157	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	95	0	0
T34	0	193	0	0
T55	0	787	0	0
T69	0	101	0	0
T70	0	355	0	0
T118	0	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	292	0	0
T4	35865	5	0	0
T8	483	0	0	0
T9	28549	0	0	0
T10	6167	0	0	0
T11	0	3	0	0
T29	36296	0	0	0
T33	0	1	0	0
T34	0	6	0	0
T35	0	7	0	0
T44	0	5	0	0
T46	12086	0	0	0
T47	5919	0	0	0
T53	4430	0	0	0
T55	0	14	0	0
T56	610	0	0	0
T70	0	7	0	0
T84	405	0	0	0
T118	0	1	0	0
T121	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T14,T2,T3
1	1	Covered	T14,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T3
0	1	Covered	T3,T47,T48
1	0	Covered	T2,T3,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T9,T33
0	1	Covered	T14,T9,T33
1	0	Covered	T263

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T9,T33
1	-	Covered	T14,T9,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T3
DetectSt	168	Covered	T14,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T9,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T3
DebounceSt->IdleSt	163	Covered	T52,T252,T253
DetectSt->IdleSt	186	Covered	T2,T3,T47
DetectSt->StableSt	191	Covered	T14,T9,T33
IdleSt->DebounceSt	148	Covered	T14,T2,T3
StableSt->IdleSt	206	Covered	T14,T9,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T3
0	1	Covered	T14,T2,T3
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T3,T47
DetectSt	-	-	-	-	0	1	-	Covered	T14,T9,T33
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T14,T9,T33
StableSt	-	-	-	-	-	-	0	Covered	T14,T9,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	2862	0	0
CntIncr_A	7107910	115022	0	0
CntNoWrap_A	7107910	6475633	0	0
DetectStDropOut_A	7107910	457	0	0
DetectedOut_A	7107910	75485	0	0
DetectedPulseOut_A	7107910	776	0	0
DisabledIdleSt_A	7107910	5971292	0	0
DisabledNoDetection_A	7107910	5973437	0	0
EnterDebounceSt_A	7107910	1441	0	0
EnterDetectSt_A	7107910	1421	0	0
EnterStableSt_A	7107910	776	0	0
PulseIsPulse_A	7107910	776	0	0
StayInStableSt	7107910	74602	0	0
gen_high_event_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	668	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	2862	0	0
T2	15403	2	0	0
T3	13128	30	0	0
T4	35865	0	0	0
T9	0	42	0	0
T14	13580	22	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	54	0	0
T47	0	54	0	0
T48	0	6	0	0
T69	0	26	0	0
T70	0	50	0	0
T71	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	115022	0	0
T2	15403	50	0	0
T3	13128	829	0	0
T4	35865	0	0	0
T9	0	1260	0	0
T14	13580	528	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	1728	0	0
T47	0	1779	0	0
T48	0	161	0	0
T69	0	637	0	0
T70	0	1987	0	0
T71	0	1474	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6475633	0	0
T1	1274	873	0	0
T2	15403	14977	0	0
T3	13128	12680	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13135	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	457	0	0
T3	13128	2	0	0
T4	35865	0	0	0
T8	483	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T29	36296	0	0	0
T47	0	27	0	0
T48	0	3	0	0
T70	0	8	0	0
T84	405	0	0	0
T104	0	29	0	0
T106	0	17	0	0
T107	0	22	0	0
T257	0	3	0	0
T259	0	9	0	0
T264	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	75485	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T9	0	3050	0	0
T14	13580	425	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	2264	0	0
T69	0	589	0	0
T71	0	1607	0	0
T105	0	1864	0	0
T230	0	1450	0	0
T231	0	862	0	0
T255	0	1240	0	0
T256	0	402	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	776	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	11	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	27	0	0
T69	0	13	0	0
T71	0	22	0	0
T105	0	30	0	0
T230	0	15	0	0
T231	0	9	0	0
T255	0	24	0	0
T256	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5971292	0	0
T1	1274	873	0	0
T2	15403	12249	0	0
T3	13128	9748	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	9719	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5973437	0	0
T1	1274	874	0	0
T2	15403	12253	0	0
T3	13128	9751	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	9721	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1441	0	0
T2	15403	1	0	0
T3	13128	15	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	11	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	27	0	0
T47	0	27	0	0
T48	0	3	0	0
T69	0	13	0	0
T70	0	25	0	0
T71	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1421	0	0
T2	15403	1	0	0
T3	13128	15	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	11	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	27	0	0
T47	0	27	0	0
T48	0	3	0	0
T69	0	13	0	0
T70	0	25	0	0
T71	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	776	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	11	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	27	0	0
T69	0	13	0	0
T71	0	22	0	0
T105	0	30	0	0
T230	0	15	0	0
T231	0	9	0	0
T255	0	24	0	0
T256	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	776	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T9	0	21	0	0
T14	13580	11	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	27	0	0
T69	0	13	0	0
T71	0	22	0	0
T105	0	30	0	0
T230	0	15	0	0
T231	0	9	0	0
T255	0	24	0	0
T256	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	74602	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T9	0	3020	0	0
T14	13580	413	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	2233	0	0
T69	0	576	0	0
T71	0	1579	0	0
T105	0	1831	0	0
T230	0	1432	0	0
T231	0	850	0	0
T255	0	1216	0	0
T256	0	372	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	668	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T9	0	12	0	0
T14	13580	10	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	23	0	0
T69	0	13	0	0
T71	0	16	0	0
T105	0	27	0	0
T230	0	12	0	0
T231	0	6	0	0
T255	0	24	0	0
T256	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T4,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T14,T4,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T4,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T4,T9
1	0	Covered	T14,T2,T3
1	1	Covered	T14,T4,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T4,T9
0	1	Covered	T121,T52,T261
1	0	Covered	T52,T94

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T4,T9
0	1	Covered	T4,T9,T11
1	0	Covered	T95,T97,T94

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T4,T9
1	-	Covered	T4,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T4,T9
DetectSt	168	Covered	T14,T4,T9
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T4,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T4,T9
DebounceSt->IdleSt	163	Covered	T4,T55,T36
DetectSt->IdleSt	186	Covered	T121,T52,T261
DetectSt->StableSt	191	Covered	T14,T4,T9
IdleSt->DebounceSt	148	Covered	T14,T4,T9
StableSt->IdleSt	206	Covered	T14,T4,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T4,T9
0	1	Covered	T14,T4,T9
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T4,T9
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T4,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T4,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T55,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T4,T9
DetectSt	-	-	-	-	1	-	-	Covered	T121,T52,T261
DetectSt	-	-	-	-	0	1	-	Covered	T14,T4,T9
DetectSt	-	-	-	-	0	0	-	Covered	T14,T4,T9
StableSt	-	-	-	-	-	-	1	Covered	T4,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T14,T4,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	854	0	0
CntIncr_A	7107910	46165	0	0
CntNoWrap_A	7107910	6477641	0	0
DetectStDropOut_A	7107910	40	0	0
DetectedOut_A	7107910	16991	0	0
DetectedPulseOut_A	7107910	358	0	0
DisabledIdleSt_A	7107910	6085240	0	0
DisabledNoDetection_A	7107910	6086875	0	0
EnterDebounceSt_A	7107910	453	0	0
EnterDetectSt_A	7107910	401	0	0
EnterStableSt_A	7107910	358	0	0
PulseIsPulse_A	7107910	358	0	0
StayInStableSt	7107910	16586	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	854	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	25	0	0
T9	0	12	0	0
T11	0	6	0	0
T14	13580	2	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	8	0	0
T34	0	8	0	0
T36	0	1	0	0
T55	0	29	0	0
T58	0	16	0	0
T118	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	46165	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	1390	0	0
T9	0	480	0	0
T11	0	264	0	0
T14	13580	78	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	324	0	0
T34	0	510	0	0
T36	0	45	0	0
T55	0	1496	0	0
T58	0	329	0	0
T118	0	1086	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6477641	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13155	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	40	0	0
T41	822	0	0	0
T45	19610	0	0	0
T52	0	1	0	0
T62	488	0	0	0
T63	495	0	0	0
T104	5016	0	0	0
T121	13980	7	0	0
T122	524	0	0	0
T123	445	0	0	0
T124	448	0	0	0
T206	0	1	0	0
T219	0	5	0	0
T261	0	1	0	0
T265	0	3	0	0
T266	0	2	0	0
T267	0	1	0	0
T268	0	1	0	0
T269	0	1	0	0
T270	438	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	16991	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	927	0	0
T9	0	375	0	0
T11	0	247	0	0
T14	13580	64	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	245	0	0
T34	0	113	0	0
T44	0	241	0	0
T55	0	1207	0	0
T58	0	42	0	0
T118	0	159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	358	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	12	0	0
T9	0	6	0	0
T11	0	3	0	0
T14	13580	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T44	0	7	0	0
T55	0	14	0	0
T58	0	7	0	0
T118	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6085240	0	0
T1	1274	873	0	0
T2	15403	14979	0	0
T3	13128	12710	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	12733	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6086875	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	12736	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	453	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	13	0	0
T9	0	6	0	0
T11	0	3	0	0
T14	13580	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T36	0	1	0	0
T55	0	15	0	0
T58	0	9	0	0
T118	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	401	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	12	0	0
T9	0	6	0	0
T11	0	3	0	0
T14	13580	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T44	0	7	0	0
T55	0	14	0	0
T58	0	7	0	0
T118	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	358	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	12	0	0
T9	0	6	0	0
T11	0	3	0	0
T14	13580	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T44	0	7	0	0
T55	0	14	0	0
T58	0	7	0	0
T118	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	358	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	12	0	0
T9	0	6	0	0
T11	0	3	0	0
T14	13580	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T44	0	7	0	0
T55	0	14	0	0
T58	0	7	0	0
T118	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	16586	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	915	0	0
T9	0	369	0	0
T11	0	244	0	0
T14	13580	62	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	241	0	0
T34	0	109	0	0
T44	0	234	0	0
T55	0	1193	0	0
T58	0	35	0	0
T118	0	155	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	308	0	0
T4	35865	12	0	0
T8	483	0	0	0
T9	28549	6	0	0
T10	6167	0	0	0
T11	0	3	0	0
T29	36296	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T44	0	7	0	0
T45	0	4	0	0
T46	12086	0	0	0
T47	5919	0	0	0
T53	4430	0	0	0
T55	0	14	0	0
T56	610	0	0	0
T58	0	7	0	0
T84	405	0	0	0
T118	0	4	0	0