Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T14,T2,T3
1	1	Covered	T14,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T3
0	1	Covered	T14,T47,T104
1	0	Covered	T14,T33,T259

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
1	0	Covered	T98,T271

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T9
1	-	Covered	T2,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T3
DetectSt	168	Covered	T14,T2,T3
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T3
DebounceSt->IdleSt	163	Covered	T52,T252,T253
DetectSt->IdleSt	186	Covered	T14,T47,T33
DetectSt->StableSt	191	Covered	T2,T3,T9
IdleSt->DebounceSt	148	Covered	T14,T2,T3
StableSt->IdleSt	206	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T2,T3
0	1	Covered	T14,T2,T3
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T3
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T14,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T252,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T14,T47,T33
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	3013	0	0
CntIncr_A	7107910	121177	0	0
CntNoWrap_A	7107910	6475482	0	0
DetectStDropOut_A	7107910	462	0	0
DetectedOut_A	7107910	73817	0	0
DetectedPulseOut_A	7107910	749	0	0
DisabledIdleSt_A	7107910	5973372	0	0
DisabledNoDetection_A	7107910	5975524	0	0
EnterDebounceSt_A	7107910	1521	0	0
EnterDetectSt_A	7107910	1492	0	0
EnterStableSt_A	7107910	749	0	0
PulseIsPulse_A	7107910	749	0	0
StayInStableSt	7107910	72968	0	0
gen_high_event_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	622	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	3013	0	0
T2	15403	48	0	0
T3	13128	50	0	0
T4	35865	0	0	0
T9	0	2	0	0
T14	13580	54	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	24	0	0
T47	0	54	0	0
T48	0	12	0	0
T69	0	44	0	0
T70	0	56	0	0
T71	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	121177	0	0
T2	15403	1176	0	0
T3	13128	1300	0	0
T4	35865	0	0	0
T9	0	72	0	0
T14	13580	1577	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	827	0	0
T47	0	1779	0	0
T48	0	318	0	0
T69	0	1650	0	0
T70	0	1428	0	0
T71	0	1166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6475482	0	0
T1	1274	873	0	0
T2	15403	14931	0	0
T3	13128	12660	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13103	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	462	0	0
T2	15403	0	0	0
T3	13128	0	0	0
T4	35865	0	0	0
T14	13580	12	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T47	0	27	0	0
T52	0	1	0	0
T104	0	12	0	0
T106	0	6	0	0
T107	0	22	0	0
T108	0	5	0	0
T109	0	14	0	0
T110	0	29	0	0
T259	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	73817	0	0
T2	15403	694	0	0
T3	13128	1198	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	27	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T48	0	1025	0	0
T69	0	2320	0	0
T70	0	2082	0	0
T71	0	1915	0	0
T105	0	1283	0	0
T230	0	2799	0	0
T231	0	1949	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	749	0	0
T2	15403	24	0	0
T3	13128	25	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T48	0	6	0	0
T69	0	22	0	0
T70	0	28	0	0
T71	0	22	0	0
T105	0	29	0	0
T230	0	27	0	0
T231	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5973372	0	0
T1	1274	873	0	0
T2	15403	11574	0	0
T3	13128	8615	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	10042	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	5975524	0	0
T1	1274	874	0	0
T2	15403	11577	0	0
T3	13128	8616	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	10045	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1521	0	0
T2	15403	24	0	0
T3	13128	25	0	0
T4	35865	0	0	0
T9	0	1	0	0
T14	13580	27	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	12	0	0
T47	0	27	0	0
T48	0	6	0	0
T69	0	22	0	0
T70	0	28	0	0
T71	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	1492	0	0
T2	15403	24	0	0
T3	13128	25	0	0
T4	35865	0	0	0
T9	0	1	0	0
T14	13580	27	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T33	0	12	0	0
T47	0	27	0	0
T48	0	6	0	0
T69	0	22	0	0
T70	0	28	0	0
T71	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	749	0	0
T2	15403	24	0	0
T3	13128	25	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T48	0	6	0	0
T69	0	22	0	0
T70	0	28	0	0
T71	0	22	0	0
T105	0	29	0	0
T230	0	27	0	0
T231	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	749	0	0
T2	15403	24	0	0
T3	13128	25	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T48	0	6	0	0
T69	0	22	0	0
T70	0	28	0	0
T71	0	22	0	0
T105	0	29	0	0
T230	0	27	0	0
T231	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	72968	0	0
T2	15403	669	0	0
T3	13128	1171	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	26	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T48	0	1016	0	0
T69	0	2296	0	0
T70	0	2053	0	0
T71	0	1887	0	0
T105	0	1251	0	0
T230	0	2764	0	0
T231	0	1916	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	622	0	0
T2	15403	23	0	0
T3	13128	23	0	0
T4	35865	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T48	0	3	0	0
T69	0	20	0	0
T70	0	27	0	0
T71	0	16	0	0
T105	0	26	0	0
T230	0	19	0	0
T231	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T3
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T14,T2,T3
1	1	Covered	T2,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T46,T34,T153
1	0	Covered	T52,T94

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T4,T11
1	0	Covered	T94,T272

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T4
1	-	Covered	T2,T4,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T4
DetectSt	168	Covered	T2,T3,T4
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T4
DebounceSt->IdleSt	163	Covered	T11,T36,T34
DetectSt->IdleSt	186	Covered	T46,T34,T153
DetectSt->StableSt	191	Covered	T2,T3,T4
IdleSt->DebounceSt	148	Covered	T2,T3,T4
StableSt->IdleSt	206	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T94
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T36,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T46,T34,T153
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7107910	930	0	0
CntIncr_A	7107910	55360	0	0
CntNoWrap_A	7107910	6477565	0	0
DetectStDropOut_A	7107910	64	0	0
DetectedOut_A	7107910	16253	0	0
DetectedPulseOut_A	7107910	373	0	0
DisabledIdleSt_A	7107910	6082318	0	0
DisabledNoDetection_A	7107910	6083947	0	0
EnterDebounceSt_A	7107910	490	0	0
EnterDetectSt_A	7107910	441	0	0
EnterStableSt_A	7107910	373	0	0
PulseIsPulse_A	7107910	373	0	0
StayInStableSt	7107910	15851	0	0
gen_high_level_sva.HighLevelEvent_A	7107910	6480837	0	0
gen_not_sticky_sva.StableStDropOut_A	7107910	341	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	930	0	0
T2	15403	2	0	0
T3	13128	2	0	0
T4	35865	14	0	0
T8	483	0	0	0
T11	0	9	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	22	0	0
T46	0	6	0	0
T48	0	6	0	0
T55	0	10	0	0
T69	0	4	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	55360	0	0
T2	15403	51	0	0
T3	13128	57	0	0
T4	35865	1253	0	0
T8	483	0	0	0
T11	0	714	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	1179	0	0
T46	0	422	0	0
T48	0	252	0	0
T55	0	635	0	0
T69	0	166	0	0
T70	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6477565	0	0
T1	1274	873	0	0
T2	15403	14977	0	0
T3	13128	12708	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	64	0	0
T9	28549	0	0	0
T10	6167	0	0	0
T11	15285	0	0	0
T12	1165	0	0	0
T28	2151	0	0	0
T34	0	2	0	0
T46	12086	3	0	0
T47	5919	0	0	0
T48	12421	0	0	0
T53	4430	0	0	0
T54	2359	0	0	0
T111	0	3	0	0
T113	0	3	0	0
T114	0	3	0	0
T116	0	1	0	0
T153	0	4	0	0
T266	0	6	0	0
T273	0	4	0	0
T274	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	16253	0	0
T2	15403	93	0	0
T3	13128	57	0	0
T4	35865	48	0	0
T8	483	0	0	0
T11	0	41	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	119	0	0
T48	0	166	0	0
T55	0	302	0	0
T69	0	168	0	0
T70	0	52	0	0
T118	0	92	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	373	0	0
T2	15403	1	0	0
T3	13128	1	0	0
T4	35865	7	0	0
T8	483	0	0	0
T11	0	4	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	9	0	0
T48	0	3	0	0
T55	0	5	0	0
T69	0	2	0	0
T70	0	1	0	0
T118	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6082318	0	0
T1	1274	873	0	0
T2	15403	14286	0	0
T3	13128	11514	0	0
T5	737	336	0	0
T6	837	436	0	0
T7	506	105	0	0
T14	13580	13157	0	0
T15	751	350	0	0
T21	522	121	0	0
T22	522	121	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6083947	0	0
T1	1274	874	0	0
T2	15403	14290	0	0
T3	13128	11516	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	490	0	0
T2	15403	1	0	0
T3	13128	1	0	0
T4	35865	7	0	0
T8	483	0	0	0
T11	0	5	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	13	0	0
T46	0	3	0	0
T48	0	3	0	0
T55	0	5	0	0
T69	0	2	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	441	0	0
T2	15403	1	0	0
T3	13128	1	0	0
T4	35865	7	0	0
T8	483	0	0	0
T11	0	4	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	9	0	0
T46	0	3	0	0
T48	0	3	0	0
T55	0	5	0	0
T69	0	2	0	0
T70	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	373	0	0
T2	15403	1	0	0
T3	13128	1	0	0
T4	35865	7	0	0
T8	483	0	0	0
T11	0	4	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	9	0	0
T48	0	3	0	0
T55	0	5	0	0
T69	0	2	0	0
T70	0	1	0	0
T118	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	373	0	0
T2	15403	1	0	0
T3	13128	1	0	0
T4	35865	7	0	0
T8	483	0	0	0
T11	0	4	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	9	0	0
T48	0	3	0	0
T55	0	5	0	0
T69	0	2	0	0
T70	0	1	0	0
T118	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	15851	0	0
T2	15403	92	0	0
T3	13128	55	0	0
T4	35865	41	0	0
T8	483	0	0	0
T11	0	37	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T36	0	110	0	0
T48	0	160	0	0
T55	0	297	0	0
T69	0	164	0	0
T70	0	50	0	0
T118	0	88	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	6480837	0	0
T1	1274	874	0	0
T2	15403	14984	0	0
T3	13128	12714	0	0
T5	737	337	0	0
T6	837	437	0	0
T7	506	106	0	0
T14	13580	13161	0	0
T15	751	351	0	0
T21	522	122	0	0
T22	522	122	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7107910	341	0	0
T2	15403	1	0	0
T3	13128	0	0	0
T4	35865	7	0	0
T8	483	0	0	0
T11	0	4	0	0
T15	751	0	0	0
T16	521	0	0	0
T17	422	0	0	0
T18	426	0	0	0
T19	525	0	0	0
T20	502	0	0	0
T34	0	9	0	0
T36	0	9	0	0
T44	0	7	0	0
T55	0	5	0	0
T58	0	1	0	0
T118	0	4	0	0
T121	0	4	0	0