Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1140985895	11600	0	0
auto_block_debounce_ctl_rd_A	1140985895	1311	0	0
auto_block_out_ctl_rd_A	1140985895	2108	0	0
com_det_ctl_0_rd_A	1140985895	3390	0	0
com_det_ctl_1_rd_A	1140985895	3760	0	0
com_det_ctl_2_rd_A	1140985895	3572	0	0
com_det_ctl_3_rd_A	1140985895	3630	0	0
com_out_ctl_0_rd_A	1140985895	4100	0	0
com_out_ctl_1_rd_A	1140985895	4144	0	0
com_out_ctl_2_rd_A	1140985895	4562	0	0
com_out_ctl_3_rd_A	1140985895	4282	0	0
com_pre_det_ctl_0_rd_A	1140985895	903	0	0
com_pre_det_ctl_1_rd_A	1140985895	1045	0	0
com_pre_det_ctl_2_rd_A	1140985895	1059	0	0
com_pre_det_ctl_3_rd_A	1140985895	848	0	0
com_pre_sel_ctl_0_rd_A	1140985895	4337	0	0
com_pre_sel_ctl_1_rd_A	1140985895	4588	0	0
com_pre_sel_ctl_2_rd_A	1140985895	4505	0	0
com_pre_sel_ctl_3_rd_A	1140985895	4203	0	0
com_sel_ctl_0_rd_A	1140985895	4411	0	0
com_sel_ctl_1_rd_A	1140985895	4447	0	0
com_sel_ctl_2_rd_A	1140985895	4354	0	0
com_sel_ctl_3_rd_A	1140985895	4312	0	0
ec_rst_ctl_rd_A	1140985895	2207	0	0
intr_enable_rd_A	1140985895	1594	0	0
key_intr_ctl_rd_A	1140985895	3469	0	0
key_intr_debounce_ctl_rd_A	1140985895	913	0	0
key_invert_ctl_rd_A	1140985895	4333	0	0
pin_allowed_ctl_rd_A	1140985895	6479	0	0
pin_out_ctl_rd_A	1140985895	4340	0	0
pin_out_value_rd_A	1140985895	4350	0	0
regwen_rd_A	1140985895	1099	0	0
ulp_ac_debounce_ctl_rd_A	1140985895	1017	0	0
ulp_ctl_rd_A	1140985895	926	0	0
ulp_lid_debounce_ctl_rd_A	1140985895	1069	0	0
ulp_pwrb_debounce_ctl_rd_A	1140985895	1036	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	11600	0	0
T10	151106	5	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	14	0	0
T33	231195	0	0	0
T34	0	25	0	0
T45	0	14	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T61	0	7	0	0
T67	202536	0	0	0
T129	0	23	0	0
T152	0	14	0	0
T153	0	4	0	0
T154	0	6	0	0
T276	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1311	0	0
T10	151106	16	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T44	0	5	0	0
T48	869544	0	0	0
T51	0	10	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T126	0	11	0	0
T127	0	7	0	0
T129	0	18	0	0
T153	0	5	0	0
T154	0	9	0	0
T276	0	22	0	0
T277	0	16	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	2108	0	0
T10	151106	19	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T44	0	14	0	0
T48	869544	0	0	0
T51	0	2	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T126	0	11	0	0
T127	0	9	0	0
T129	0	32	0	0
T154	0	9	0	0
T276	0	18	0	0
T277	0	12	0	0
T278	0	16	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	3390	0	0
T9	356874	57	0	0
T10	151106	13	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	25	0	0
T36	0	37	0	0
T44	0	72	0	0
T46	296116	58	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	11	0	0
T118	0	55	0	0
T230	0	62	0	0
T231	0	51	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	3760	0	0
T9	356874	61	0	0
T10	151106	17	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	18	0	0
T36	0	37	0	0
T44	0	70	0	0
T46	296116	85	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	34	0	0
T118	0	76	0	0
T230	0	69	0	0
T231	0	53	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	3572	0	0
T9	356874	54	0	0
T10	151106	15	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	42	0	0
T36	0	54	0	0
T44	0	52	0	0
T46	296116	48	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	17	0	0
T118	0	63	0	0
T230	0	65	0	0
T231	0	57	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	3630	0	0
T9	356874	49	0	0
T10	151106	19	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	34	0	0
T36	0	42	0	0
T44	0	62	0	0
T46	296116	79	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	23	0	0
T118	0	62	0	0
T230	0	74	0	0
T231	0	86	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4100	0	0
T9	356874	34	0	0
T10	151106	23	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	40	0	0
T36	0	56	0	0
T44	0	63	0	0
T46	296116	58	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	5	0	0
T118	0	79	0	0
T230	0	47	0	0
T231	0	63	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4144	0	0
T9	356874	70	0	0
T10	151106	21	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	47	0	0
T36	0	29	0	0
T44	0	79	0	0
T46	296116	67	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	15	0	0
T118	0	58	0	0
T230	0	64	0	0
T231	0	64	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4562	0	0
T9	356874	70	0	0
T10	151106	25	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	35	0	0
T36	0	40	0	0
T44	0	66	0	0
T46	296116	81	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	25	0	0
T118	0	68	0	0
T230	0	68	0	0
T231	0	65	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4282	0	0
T9	356874	50	0	0
T10	151106	11	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	84	0	0
T36	0	40	0	0
T44	0	58	0	0
T46	296116	76	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	19	0	0
T118	0	63	0	0
T230	0	56	0	0
T231	0	68	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	903	0	0
T10	151106	25	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T116	0	22	0	0
T129	0	10	0	0
T154	0	6	0	0
T161	0	34	0	0
T276	0	9	0	0
T277	0	5	0	0
T279	0	9	0	0
T280	0	18	0	0
T281	0	23	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1045	0	0
T10	151106	20	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T116	0	23	0	0
T129	0	5	0	0
T153	0	5	0	0
T154	0	11	0	0
T161	0	31	0	0
T276	0	15	0	0
T277	0	22	0	0
T280	0	26	0	0
T281	0	20	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1059	0	0
T10	151106	17	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T116	0	27	0	0
T129	0	13	0	0
T153	0	8	0	0
T154	0	3	0	0
T161	0	23	0	0
T276	0	34	0	0
T277	0	18	0	0
T279	0	17	0	0
T280	0	21	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	848	0	0
T10	151106	24	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T116	0	24	0	0
T129	0	13	0	0
T153	0	7	0	0
T154	0	15	0	0
T161	0	2	0	0
T276	0	15	0	0
T277	0	6	0	0
T279	0	15	0	0
T280	0	27	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4337	0	0
T9	356874	33	0	0
T10	151106	7	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	41	0	0
T36	0	49	0	0
T44	0	72	0	0
T46	296116	81	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	8	0	0
T118	0	80	0	0
T230	0	62	0	0
T231	0	46	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4588	0	0
T9	356874	68	0	0
T10	151106	16	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	24	0	0
T36	0	54	0	0
T44	0	68	0	0
T46	296116	75	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	23	0	0
T118	0	61	0	0
T230	0	60	0	0
T231	0	58	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4505	0	0
T9	356874	57	0	0
T10	151106	20	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	53	0	0
T36	0	30	0	0
T44	0	64	0	0
T46	296116	60	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	1	0	0
T118	0	76	0	0
T230	0	58	0	0
T231	0	76	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4203	0	0
T9	356874	41	0	0
T10	151106	12	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	23	0	0
T36	0	33	0	0
T44	0	68	0	0
T46	296116	90	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	32	0	0
T118	0	61	0	0
T230	0	71	0	0
T231	0	72	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4411	0	0
T9	356874	77	0	0
T10	151106	24	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	33	0	0
T36	0	44	0	0
T44	0	60	0	0
T46	296116	81	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	15	0	0
T118	0	69	0	0
T230	0	71	0	0
T231	0	59	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4447	0	0
T9	356874	62	0	0
T10	151106	17	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	19	0	0
T36	0	53	0	0
T44	0	83	0	0
T46	296116	62	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	37	0	0
T118	0	60	0	0
T230	0	75	0	0
T231	0	60	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4354	0	0
T9	356874	84	0	0
T10	151106	24	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	17	0	0
T36	0	11	0	0
T44	0	63	0	0
T46	296116	77	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	15	0	0
T118	0	63	0	0
T230	0	66	0	0
T231	0	61	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4312	0	0
T9	356874	48	0	0
T10	151106	17	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T28	106489	0	0	0
T33	0	47	0	0
T36	0	44	0	0
T44	0	63	0	0
T46	296116	91	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T70	0	16	0	0
T118	0	72	0	0
T230	0	42	0	0
T231	0	74	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	2207	0	0
T9	356874	26	0	0
T10	151106	17	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T33	0	6	0	0
T36	0	7	0	0
T46	296116	19	0	0
T47	769454	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T56	152790	2	0	0
T70	0	9	0	0
T118	0	50	0	0
T167	0	1	0	0
T207	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1594	0	0
T10	151106	10	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T26	0	16	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T129	0	5	0	0
T153	0	2	0	0
T154	0	13	0	0
T276	0	21	0	0
T277	0	14	0	0
T279	0	12	0	0
T282	0	17	0	0
T283	0	14	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	3469	0	0
T10	151106	25	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T44	0	7	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T129	0	15	0	0
T150	0	4	0	0
T153	0	5	0	0
T154	0	6	0	0
T163	0	1	0	0
T201	0	4	0	0
T276	0	27	0	0
T284	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	913	0	0
T10	151106	29	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T116	0	19	0	0
T129	0	3	0	0
T154	0	12	0	0
T161	0	8	0	0
T276	0	21	0	0
T277	0	18	0	0
T279	0	11	0	0
T280	0	23	0	0
T281	0	16	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4333	0	0
T10	151106	59	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T26	0	21	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T44	0	81	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T64	0	52	0	0
T66	0	49	0	0
T67	202536	0	0	0
T153	0	30	0	0
T168	0	48	0	0
T248	0	45	0	0
T285	0	79	0	0
T286	0	49	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	6479	0	0
T1	54561	0	0	0
T2	184841	0	0	0
T3	597335	0	0	0
T7	53168	24	0	0
T10	0	86	0	0
T14	251243	0	0	0
T15	372246	0	0	0
T16	250697	0	0	0
T17	205040	0	0	0
T21	250550	0	0	0
T22	261075	0	0	0
T129	0	88	0	0
T154	0	38	0	0
T165	0	68	0	0
T276	0	25	0	0
T277	0	25	0	0
T282	0	79	0	0
T284	0	63	0	0
T287	0	64	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4340	0	0
T1	54561	0	0	0
T2	184841	0	0	0
T3	597335	0	0	0
T7	53168	32	0	0
T10	0	84	0	0
T14	251243	0	0	0
T15	372246	0	0	0
T16	250697	0	0	0
T17	205040	0	0	0
T21	250550	0	0	0
T22	261075	0	0	0
T129	0	95	0	0
T153	0	4	0	0
T154	0	59	0	0
T165	0	63	0	0
T276	0	16	0	0
T277	0	18	0	0
T282	0	66	0	0
T284	0	76	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	4350	0	0
T1	54561	0	0	0
T2	184841	0	0	0
T3	597335	0	0	0
T7	53168	57	0	0
T10	0	73	0	0
T14	251243	0	0	0
T15	372246	0	0	0
T16	250697	0	0	0
T17	205040	0	0	0
T21	250550	0	0	0
T22	261075	0	0	0
T129	0	99	0	0
T154	0	41	0	0
T165	0	71	0	0
T276	0	30	0	0
T277	0	22	0	0
T282	0	70	0	0
T284	0	52	0	0
T287	0	72	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1099	0	0
T10	151106	16	0	0
T11	275131	0	0	0
T12	253273	0	0	0
T13	138071	0	0	0
T28	106489	0	0	0
T33	231195	0	0	0
T48	869544	0	0	0
T53	288008	0	0	0
T54	116811	0	0	0
T67	202536	0	0	0
T116	0	16	0	0
T129	0	9	0	0
T153	0	2	0	0
T154	0	17	0	0
T161	0	20	0	0
T276	0	13	0	0
T277	0	18	0	0
T279	0	14	0	0
T280	0	16	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1017	0	0
T1	54561	1	0	0
T2	184841	0	0	0
T3	597335	0	0	0
T6	50380	8	0	0
T7	53168	0	0	0
T10	0	24	0	0
T14	251243	0	0	0
T15	372246	0	0	0
T16	250697	0	0	0
T21	250550	0	0	0
T22	261075	0	0	0
T26	0	7	0	0
T129	0	16	0	0
T153	0	4	0	0
T154	0	9	0	0
T276	0	27	0	0
T277	0	16	0	0
T288	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	926	0	0
T1	54561	5	0	0
T2	184841	0	0	0
T3	597335	0	0	0
T6	50380	9	0	0
T7	53168	0	0	0
T10	0	11	0	0
T14	251243	0	0	0
T15	372246	0	0	0
T16	250697	0	0	0
T21	250550	0	0	0
T22	261075	0	0	0
T129	0	24	0	0
T154	0	13	0	0
T276	0	19	0	0
T277	0	13	0	0
T279	0	7	0	0
T288	0	7	0	0
T289	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1069	0	0
T1	54561	0	0	0
T2	184841	0	0	0
T3	597335	0	0	0
T6	50380	4	0	0
T7	53168	0	0	0
T10	0	13	0	0
T14	251243	0	0	0
T15	372246	0	0	0
T16	250697	0	0	0
T21	250550	0	0	0
T22	261075	0	0	0
T26	0	7	0	0
T129	0	25	0	0
T154	0	9	0	0
T276	0	29	0	0
T277	0	15	0	0
T279	0	10	0	0
T288	0	9	0	0
T289	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1140985895	1036	0	0
T1	54561	0	0	0
T2	184841	0	0	0
T3	597335	0	0	0
T6	50380	1	0	0
T7	53168	0	0	0
T10	0	14	0	0
T14	251243	0	0	0
T15	372246	0	0	0
T16	250697	0	0	0
T21	250550	0	0	0
T22	261075	0	0	0
T26	0	6	0	0
T129	0	25	0	0
T153	0	6	0	0
T154	0	5	0	0
T276	0	14	0	0
T277	0	17	0	0
T288	0	24	0	0
T289	0	1	0	0