Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2094

1

T3

1

T6

1

T7

2

auto[1]

576

1

T5

7

T7

7

T28

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1967

1

T3

1

T5

4

T6

1

auto[1]

703

1

T5

3

T7

1

T28

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2090

1

T3

1

T5

4

T6

1

auto[1]

580

1

T5

3

T7

5

T11

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1972

1

T5

3

T7

5

T28

8

auto[1]

698

1

T3

1

T5

4

T6

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2453

1

T3

1

T5

7

T6

1

auto[1]

217

1

T23

14

T41

7

T42

21

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2408

1

T3

1

T5

7

T6

1

auto[1]

262

1

T42

6

T242

2

T243

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2396

1

T3

1

T5

7

T6

1

auto[1]

274

1

T23

19

T179

6

T243

19

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2439

1

T3

1

T5

7

T6

1

auto[1]

231

1

T23

7

T41

2

T242

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2454

1

T3

1

T5

7

T6

1

auto[1]

216

1

T23

5

T41

10

T42

7

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2035

1

T5

4

T7

5

T11

1

auto[1]

635

1

T3

1

T5

3

T6

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	964	1			T3	1		T5	7		T6	1
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	42	1			T41	7		T42	8		T328	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	58	1			T41	8		T103	2		T138	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	34	1			T42	7		T43	1		T335	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	40	1			T95	3		T137	1		T342	6
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	21	1			T348	1		T337	3		T339	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	30	1			T41	2		T242	6		T244	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T339	3		T349	3		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	76	1			T243	16		T245	2		T260	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	28	1			T23	2		T179	3		T350	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	23	1			T138	3		T351	11		T352	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T353	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	38	1			T179	3		T354	11		T355	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	8	1			T23	2		T356	6		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T351	2		T357	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	53	1			T244	9		T260	4		T327	12
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	40	1			T42	6		T260	2		T137	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	24	1			T244	6		T358	8		T328	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	2	1			T242	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	48	1			T245	1		T358	16		T327	8
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T243	1		T359	3		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	45	1			T244	6		T339	2		T359	7
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	10	1			T243	3		T360	1		T240	6
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T335	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T350	3		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	10	1			T138	2		T356	8		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

96

1

T81

10

T179

3

T222

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

102

1

T23

2

T81

12

T182

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

77

1

T7

4

T244

6

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

116

1

T26

9

T268

12

T89

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

78

1

T5

4

T39

1

T89

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

56

1

T3

1

T6

1

T26

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T28

4

T89

1

T248

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

112

1

T48

1

T102

9

T244

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T41

2

T110

4

T103

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T109

6

T110

9

T361

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

42

1

T48

1

T258

2

T244

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

70

1

T7

2

T11

1

T41

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T7

2

T260

4

T362

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

38

1

T26

3

T42

6

T268

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T270

2

T363

1

T336

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

172

1

T28

8

T41

8

T42

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

62

1

T222

7

T94

4

T260

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T81

2

T258

6

T109

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T39

1

T338

5

T264

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

115

1

T42

7

T43

1

T102

10

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T81

2

T243

8

T264

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T182

5

T243

8

T88

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T182

4

T331

1

T364

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T102

4

T109

6

T244

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T7

1

T109

3

T333

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T338

2

T96

4

T269

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T5

3

T137

1

T272

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T182

5

T88

2

T138

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T189

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T248

1

T269

2

T365

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T266

1

T363

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded