Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T3

28

T6

41

T62

11

auto[1]

1077

1

T3

32

T6

39

T62

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T3

17

T6

22

T62

7

from_0to1

527

1

T3

17

T6

21

T62

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T3

30

T6

42

T62

11

auto[1]

1081

1

T3

30

T6

38

T62

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T3

38

T6

41

T62

13

auto[1]

1108

1

T3

22

T6

39

T62

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T3

3

T6

5

T38

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T3

2

T6

3

T107

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T3

1

T6

5

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T3

1

T62

3

T129

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T3

1

T6

3

T62

3

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T3

1

T6

2

T63

3

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T3

4

T6

3

T62

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T3

3

T6

3

T62

2

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T3

3

T6

2

T62

3

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T3

1

T6

2

T63

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T3

3

T6

2

T62

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T3

3

T6

3

T107

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T3

3

T6

4

T63

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T3

1

T6

2

T107

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T3

2

T6

3

T37

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T3

2

T6

1

T62

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T3

39

T6

40

T62

7

auto[1]

1014

1

T3

21

T6

40

T62

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

512

1

T3

14

T6

20

T62

6

from_0to1

523

1

T3

14

T6

21

T62

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1028

1

T3

26

T6

36

T62

6

auto[1]

1133

1

T3

34

T6

44

T62

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1082

1

T3

31

T6

38

T62

10

auto[1]

1079

1

T3

29

T6

42

T62

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T3

3

T6

4

T62

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T3

1

T6

5

T107

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T3

3

T6

2

T62

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T3

1

T6

2

T62

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T3

2

T107

1

T37

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T3

3

T6

2

T246

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T3

3

T6

1

T62

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T3

2

T6

4

T63

2

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T3

2

T62

2

T107

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T3

2

T6

2

T107

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T3

2

T6

5

T63

2

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T62

1

T37

1

T256

5

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T3

1

T6

4

T107

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T3

1

T6

5

T107

2

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T3

1

T62

2

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T3

1

T6

5

T62

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T3

25

T6

38

T62

6

auto[1]

1084

1

T3

35

T6

42

T62

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

507

1

T3

13

T6

18

T62

5

from_0to1

514

1

T3

14

T6

18

T62

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T3

31

T6

48

T62

9

auto[1]

1036

1

T3

29

T6

32

T62

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T3

27

T6

45

T62

7

auto[1]

1098

1

T3

33

T6

35

T62

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T3

1

T6

2

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

79

1

T3

1

T6

4

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T3

1

T6

1

T129

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T3

3

T6

1

T107

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T3

4

T6

3

T107

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T3

1

T6

1

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T3

2

T6

2

T38

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T3

2

T6

1

T62

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T3

1

T6

5

T129

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T3

1

T6

2

T62

3

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T3

2

T6

3

T62

2

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T3

3

T63

2

T107

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T3

4

T6

3

T107

1

auto[1]

from_0to1

auto[0]

auto[1]

75

1

T6

3

T62

2

T38

4

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T6

3

T62

1

T63

3

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T3

1

T6

2

T62

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1085

1

T3

24

T6

41

T62

9

auto[1]

1076

1

T3

36

T6

39

T62

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T3

14

T6

24

T62

5

from_0to1

534

1

T3

13

T6

24

T62

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T3

30

T6

41

T62

10

auto[1]

1065

1

T3

30

T6

39

T62

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T3

27

T6

37

T62

7

auto[1]

1121

1

T3

33

T6

43

T62

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T3

3

T6

2

T62

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T6

5

T62

2

T107

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T6

2

T246

2

T274

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T3

1

T6

6

T107

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T3

2

T6

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T3

2

T6

1

T63

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T3

2

T6

1

T107

3

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T3

1

T6

2

T62

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T3

3

T6

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T3

1

T6

4

T62

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T3

3

T6

2

T378

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T3

3

T6

1

T63

2

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T3

1

T6

6

T62

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T3

2

T6

6

T62

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T3

1

T6

3

T62

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T3

2

T6

4

T62

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T3

31

T6

44

T62

15

auto[1]

1023

1

T3

29

T6

36

T62

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

523

1

T3

13

T6

23

T62

6

from_0to1

528

1

T3

14

T6

23

T62

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117

1

T3

32

T6

46

T62

10

auto[1]

1044

1

T3

28

T6

34

T62

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T3

33

T6

38

T62

11

auto[1]

1086

1

T3

27

T6

42

T62

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T6

2

T62

2

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T6

3

T63

1

T107

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T3

1

T6

5

T62

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T3

3

T6

1

T62

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T3

2

T6

8

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T3

2

T6

3

T62

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T3

1

T6

2

T62

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T3

3

T62

2

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T3

3

T6

4

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T3

4

T6

2

T246

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T3

1

T6

2

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T3

1

T6

4

T62

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T3

2

T6

1

T38

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T3

1

T6

5

T62

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T3

1

T6

1

T107

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T3

2

T6

3

T62

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T3

28

T6

47

T62

10

auto[1]

1077

1

T3

32

T6

33

T62

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

518

1

T3

17

T6

18

T62

5

from_0to1

521

1

T3

16

T6

19

T62

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T3

27

T6

46

T62

15

auto[1]

1102

1

T3

33

T6

34

T62

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T3

31

T6

42

T62

11

auto[1]

1089

1

T3

29

T6

38

T62

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T3

2

T6

2

T62

2

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T3

2

T6

2

T62

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T3

3

T6

4

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T3

1

T6

4

T63

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T3

2

T6

6

T62

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T3

4

T6

5

T63

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T3

1

T6

1

T62

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T3

2

T6

1

T273

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T3

4

T6

4

T62

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T3

1

T62

1

T107

4

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T3

2

T6

2

T37

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T3

2

T246

1

T273

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T3

1

T6

2

T62

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T3

1

T6

3

T62

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T3

2

T6

1

T62

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T3

3

T107

1

T129

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T3

33

T6

41

T62

9

auto[1]

1105

1

T3

27

T6

39

T62

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T3

13

T6

17

T62

5

from_0to1

512

1

T3

13

T6

17

T62

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T3

33

T6

40

T62

7

auto[1]

1027

1

T3

27

T6

40

T62

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T3

32

T6

43

T62

10

auto[1]

1080

1

T3

28

T6

37

T62

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T3

5

T6

2

T246

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T3

1

T6

3

T107

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T3

2

T6

4

T62

2

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T3

2

T6

2

T62

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T3

3

T6

4

T37

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T3

3

T63

2

T107

2

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T3

1

T6

2

T62

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T3

3

T6

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T3

1

T6

2

T37

2

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T3

1

T6

2

T62

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T3

1

T6

2

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T62

1

T129

1

T38

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T3

1

T63

1

T246

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T3

2

T6

1

T62

1

auto[1]

from_0to1

auto[1]

auto[0]

53

1

T6

4

T63

1

T107

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T6

5

T62

2

T378

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T3

31

T6

36

T62

9

auto[1]

1084

1

T3

29

T6

44

T62

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

522

1

T3

15

T6

22

T62

6

from_0to1

526

1

T3

15

T6

23

T62

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T3

30

T6

37

T62

9

auto[1]

1072

1

T3

30

T6

43

T62

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T3

32

T6

33

T62

9

auto[1]

1132

1

T3

28

T6

47

T62

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T3

3

T6

1

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T3

5

T6

6

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T3

1

T62

1

T63

2

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T3

1

T6

3

T62

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T3

1

T6

1

T107

2

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T3

2

T6

4

T63

1

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T3

2

T6

1

T107

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T3

2

T6

3

T62

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T3

1

T6

2

T129

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T3

1

T6

3

T62

3

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T3

2

T6

3

T62

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T3

1

T6

4

T246

2

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T3

1

T6

6

T62

3

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T3

2

T6

2

T63

2

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T3

2

T107

1

T37

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T3

3

T6

6

T129

1