Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157277	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120765

1

T1

16

T2

10

T4

120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143524	1			T1	20		T2	18		T4	3
values[0x0]	66940	1			T1	3		T2	2		T4	218
values[0x1]	67578	1			T1	11		T2	8		T4	205

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150268

1

T1

19

T2

15

T4

150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	811	1			T4	3		T12	2		T6	7
valid_sources[0x01]	995	1			T4	3		T12	2		T6	6
valid_sources[0x02]	1020	1			T12	10		T11	3		T28	1
valid_sources[0x03]	922	1			T4	2		T6	1		T7	5
valid_sources[0x04]	828	1			T4	1		T12	2		T6	3
valid_sources[0x05]	836	1			T4	2		T6	7		T21	5
valid_sources[0x06]	872	1			T12	5		T6	14		T84	1
valid_sources[0x07]	1090	1			T4	4		T12	1		T6	4
valid_sources[0x08]	867	1			T4	2		T6	8		T7	3
valid_sources[0x09]	1378	1			T4	2		T12	4		T6	2
valid_sources[0x0a]	917	1			T6	3		T7	1		T54	2
valid_sources[0x0b]	1024	1			T3	20		T6	6		T21	3
valid_sources[0x0c]	1026	1			T4	2		T12	7		T6	5
valid_sources[0x0d]	1010	1			T4	2		T12	1		T6	5
valid_sources[0x0e]	826	1			T4	1		T6	7		T7	1
valid_sources[0x0f]	953	1			T4	3		T12	6		T6	5
valid_sources[0x10]	955	1			T4	1		T6	6		T7	6
valid_sources[0x11]	921	1			T4	2		T12	7		T6	5
valid_sources[0x12]	1909	1			T4	3		T12	2		T6	2
valid_sources[0x13]	772	1			T12	3		T6	8		T7	8
valid_sources[0x14]	932	1			T12	2		T6	9		T7	3
valid_sources[0x15]	1629	1			T4	4		T12	3		T6	4
valid_sources[0x16]	804	1			T4	3		T6	8		T11	3
valid_sources[0x17]	846	1			T6	5		T7	2		T10	2
valid_sources[0x18]	1241	1			T4	2		T12	5		T6	10
valid_sources[0x19]	927	1			T12	5		T6	5		T7	3
valid_sources[0x1a]	1776	1			T4	4		T6	6		T11	3
valid_sources[0x1b]	1354	1			T4	1		T12	6		T6	5
valid_sources[0x1c]	1092	1			T1	34		T4	2		T12	3
valid_sources[0x1d]	995	1			T4	1		T6	2		T11	1
valid_sources[0x1e]	1085	1			T4	1		T12	5		T6	6
valid_sources[0x1f]	1041	1			T4	2		T12	28		T6	1
valid_sources[0x20]	885	1			T4	1		T12	3		T6	6
valid_sources[0x21]	1053	1			T4	2		T12	3		T14	103
valid_sources[0x22]	974	1			T4	3		T12	6		T6	2
valid_sources[0x23]	980	1			T4	2		T12	1		T3	20
valid_sources[0x24]	967	1			T4	2		T6	7		T7	2
valid_sources[0x25]	909	1			T4	1		T6	9		T7	1
valid_sources[0x26]	963	1			T4	1		T12	15		T6	5
valid_sources[0x27]	925	1			T4	1		T12	3		T6	8
valid_sources[0x28]	877	1			T4	2		T12	15		T6	6
valid_sources[0x29]	2189	1			T4	3		T12	5		T6	7
valid_sources[0x2a]	826	1			T4	4		T6	3		T7	2
valid_sources[0x2b]	943	1			T4	2		T12	2		T6	1
valid_sources[0x2c]	865	1			T4	1		T6	7		T210	2
valid_sources[0x2d]	1017	1			T4	3		T12	4		T6	5
valid_sources[0x2e]	981	1			T4	2		T6	5		T7	1
valid_sources[0x2f]	863	1			T3	2		T6	7		T8	1
valid_sources[0x30]	1120	1			T4	2		T12	2		T6	5
valid_sources[0x31]	972	1			T12	8		T6	2		T7	2
valid_sources[0x32]	938	1			T12	10		T6	3		T7	6
valid_sources[0x33]	908	1			T4	2		T12	5		T6	5
valid_sources[0x34]	918	1			T4	4		T12	3		T6	8
valid_sources[0x35]	892	1			T4	1		T12	7		T6	4
valid_sources[0x36]	2617	1			T4	1		T12	2		T6	2
valid_sources[0x37]	2002	1			T4	3		T12	4		T6	2
valid_sources[0x38]	874	1			T4	4		T6	2		T11	1
valid_sources[0x39]	1610	1			T6	3		T7	2		T54	1
valid_sources[0x3a]	999	1			T4	1		T6	6		T7	3
valid_sources[0x3b]	875	1			T4	3		T12	4		T6	6
valid_sources[0x3c]	882	1			T4	2		T12	6		T6	5
valid_sources[0x3d]	968	1			T4	2		T6	5		T7	4
valid_sources[0x3e]	795	1			T4	2		T12	5		T6	3
valid_sources[0x3f]	1734	1			T4	1		T3	222		T6	5
valid_sources[0x40]	978	1			T4	1		T12	1		T6	4
valid_sources[0x41]	953	1			T6	3		T52	5		T7	2
valid_sources[0x42]	2644	1			T4	5		T5	487		T6	4
valid_sources[0x43]	936	1			T12	9		T6	10		T11	5
valid_sources[0x44]	1307	1			T4	2		T12	11		T6	7
valid_sources[0x45]	969	1			T4	3		T12	5		T6	10
valid_sources[0x46]	922	1			T4	1		T12	2		T6	4
valid_sources[0x47]	970	1			T4	4		T6	9		T7	2
valid_sources[0x48]	1070	1			T4	2		T12	5		T11	2
valid_sources[0x49]	920	1			T4	1		T12	9		T6	3
valid_sources[0x4a]	1011	1			T4	3		T12	3		T6	4
valid_sources[0x4b]	1256	1			T4	5		T12	2		T6	6
valid_sources[0x4c]	895	1			T12	3		T6	10		T54	2
valid_sources[0x4d]	857	1			T4	1		T6	4		T7	5
valid_sources[0x4e]	864	1			T4	3		T12	1		T6	2
valid_sources[0x4f]	1022	1			T4	2		T6	7		T7	9
valid_sources[0x50]	828	1			T4	2		T12	3		T6	4
valid_sources[0x51]	1039	1			T4	1		T12	3		T6	7
valid_sources[0x52]	1125	1			T6	4		T85	3		T54	1
valid_sources[0x53]	1120	1			T4	2		T12	2		T6	2
valid_sources[0x54]	1287	1			T12	5		T6	1		T84	1
valid_sources[0x55]	1450	1			T4	2		T12	4		T6	6
valid_sources[0x56]	869	1			T4	5		T12	2		T6	5
valid_sources[0x57]	1007	1			T4	3		T6	5		T7	1
valid_sources[0x58]	908	1			T12	2		T6	4		T7	1
valid_sources[0x59]	944	1			T4	1		T12	1		T3	20
valid_sources[0x5a]	1009	1			T4	3		T12	1		T13	2
valid_sources[0x5b]	1007	1			T4	1		T12	2		T6	2
valid_sources[0x5c]	1024	1			T4	1		T12	3		T6	4
valid_sources[0x5d]	796	1			T4	1		T12	5		T6	6
valid_sources[0x5e]	946	1			T6	1		T7	3		T21	2
valid_sources[0x5f]	1057	1			T6	3		T7	1		T28	1
valid_sources[0x60]	1081	1			T12	2		T6	3		T83	1
valid_sources[0x61]	1025	1			T6	4		T7	8		T11	3
valid_sources[0x62]	965	1			T4	4		T12	15		T6	4
valid_sources[0x63]	809	1			T4	2		T12	3		T6	7
valid_sources[0x64]	1209	1			T4	3		T12	7		T6	6
valid_sources[0x65]	868	1			T4	3		T12	4		T6	5
valid_sources[0x66]	2033	1			T12	5		T6	4		T7	1
valid_sources[0x67]	968	1			T4	2		T6	6		T9	4
valid_sources[0x68]	888	1			T12	1		T6	3		T54	10
valid_sources[0x69]	1041	1			T4	5		T12	3		T15	3
valid_sources[0x6a]	927	1			T6	7		T21	7		T28	3
valid_sources[0x6b]	1021	1			T4	2		T6	5		T54	1
valid_sources[0x6c]	1131	1			T4	1		T6	4		T54	5
valid_sources[0x6d]	1105	1			T12	9		T6	4		T7	4
valid_sources[0x6e]	918	1			T6	4		T54	8		T28	1
valid_sources[0x6f]	921	1			T4	1		T12	1		T6	6
valid_sources[0x70]	822	1			T4	1		T12	5		T6	6
valid_sources[0x71]	876	1			T4	1		T12	2		T6	3
valid_sources[0x72]	984	1			T4	1		T12	2		T3	20
valid_sources[0x73]	1018	1			T12	3		T6	8		T7	3
valid_sources[0x74]	1777	1			T4	2		T12	2		T6	5
valid_sources[0x75]	999	1			T4	2		T12	5		T6	3
valid_sources[0x76]	1043	1			T4	2		T12	8		T6	2
valid_sources[0x77]	1083	1			T4	2		T12	3		T6	5
valid_sources[0x78]	1029	1			T4	2		T12	3		T6	5
valid_sources[0x79]	937	1			T4	6		T12	2		T6	6
valid_sources[0x7a]	812	1			T4	2		T12	3		T6	5
valid_sources[0x7b]	866	1			T4	1		T12	6		T6	4
valid_sources[0x7c]	834	1			T12	5		T6	4		T8	1
valid_sources[0x7d]	1181	1			T12	6		T6	5		T7	3
valid_sources[0x7e]	1771	1			T12	2		T6	3		T7	2
valid_sources[0x7f]	979	1			T12	3		T15	2		T6	10
valid_sources[0x80]	1088	1			T4	3		T12	2		T6	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65632

1

T1

12

T2

9

T4

3

values[0x0]

all_enables

biggest_size

32278

1

T1

1

T4

78

T12

100

values[0x1]

all_enables

biggest_size

22855

1

T1

3

T2

1

T4

39