Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T22,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T22,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T22,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T22,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T22,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T22,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T22,T11
0	1	Covered	T3,T22,T11
1	0	Covered	T70,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T22,T11
1	-	Covered	T3,T22,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T22,T11
DetectSt	168	Covered	T3,T22,T11
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T22,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T22,T11
DebounceSt->IdleSt	163	Covered	T48,T50,T94
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T22,T11
IdleSt->DebounceSt	148	Covered	T3,T22,T11
StableSt->IdleSt	206	Covered	T3,T22,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T22,T11
0	1	Covered	T3,T22,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T22,T11
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T22,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T22,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T50,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T22,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T22,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T22,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T22,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	273	0	0
CntIncr_A	8886315	199319	0	0
CntNoWrap_A	8886315	8213827	0	0
DetectStDropOut_A	8886315	0	0	0
DetectedOut_A	8886315	834	0	0
DetectedPulseOut_A	8886315	124	0	0
DisabledIdleSt_A	8886315	8008330	0	0
DisabledNoDetection_A	8886315	8010713	0	0
EnterDebounceSt_A	8886315	153	0	0
EnterDetectSt_A	8886315	124	0	0
EnterStableSt_A	8886315	124	0	0
PulseIsPulse_A	8886315	124	0	0
StayInStableSt	8886315	709	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	7043	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	121	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	273	0	0
T3	12717	4	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	6	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	4	0	0
T29	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	5	0	0
T50	0	3	0	0
T51	0	4	0	0
T52	79762	0	0	0
T53	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	199319	0	0
T3	12717	105	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	191	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	61	0	0
T29	0	28	0	0
T45	0	13	0	0
T46	0	95	0	0
T47	0	96	0	0
T48	0	165	0	0
T50	0	104	0	0
T51	0	133	0	0
T52	79762	0	0	0
T53	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213827	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5870	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	834	0	0
T3	12717	16	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	16	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	15	0	0
T29	0	4	0	0
T45	0	9	0	0
T46	0	2	0	0
T47	0	11	0	0
T48	0	17	0	0
T50	0	5	0	0
T51	0	16	0	0
T52	79762	0	0	0
T53	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	124	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	2	0	0
T29	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8008330	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5662	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8010713	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5686	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	153	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	2	0	0
T29	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	124	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	2	0	0
T29	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	124	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	2	0	0
T29	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	124	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	2	0	0
T29	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	709	0	0
T3	12717	14	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	13	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	13	0	0
T29	0	2	0	0
T45	0	8	0	0
T46	0	1	0	0
T47	0	10	0	0
T48	0	15	0	0
T50	0	4	0	0
T51	0	14	0	0
T52	79762	0	0	0
T53	423	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7043	0	0
T1	1604	7	0	0
T2	1739	7	0	0
T3	12717	36	0	0
T4	4882	30	0	0
T5	13605	13	0	0
T6	17688	57	0	0
T12	7140	22	0	0
T13	421	1	0	0
T14	2065	4	0	0
T15	781	0	0	0
T20	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	121	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T11	0	3	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T22	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T108	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T4,T12
1	1	Covered	T1,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T8,T78,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Unreachable
1	0	Covered	T1,T2,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T6
DetectSt	168	Covered	T1,T2,T6
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T2,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T6
DebounceSt->IdleSt	163	Covered	T6,T8,T57
DetectSt->IdleSt	186	Covered	T8,T78,T79
DetectSt->StableSt	191	Covered	T1,T2,T6
IdleSt->DebounceSt	148	Covered	T1,T2,T6
StableSt->IdleSt	206	Covered	T1,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T6
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T8,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T8,T78,T79
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	190	0	0
CntIncr_A	8886315	204905	0	0
CntNoWrap_A	8886315	8213910	0	0
DetectStDropOut_A	8886315	8	0	0
DetectedOut_A	8886315	708583	0	0
DetectedPulseOut_A	8886315	57	0	0
DisabledIdleSt_A	8886315	6255619	0	0
DisabledNoDetection_A	8886315	6258052	0	0
EnterDebounceSt_A	8886315	126	0	0
EnterDetectSt_A	8886315	65	0	0
EnterStableSt_A	8886315	57	0	0
PulseIsPulse_A	8886315	57	0	0
StayInStableSt	8886315	708526	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	7043	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_sticky_sva.StableStDropOut_A	8886315	267123	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	190	0	0
T1	1604	4	0	0
T2	1739	2	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	4	0	0
T8	0	6	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	5	0	0
T67	0	8	0	0
T68	0	4	0	0
T69	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	204905	0	0
T1	1604	112	0	0
T2	1739	68	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	172	0	0
T8	0	248	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	51	0	0
T56	0	40	0	0
T57	0	105	0	0
T67	0	544	0	0
T68	0	162	0	0
T69	0	50	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213910	0	0
T1	1604	1199	0	0
T2	1739	1336	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8408	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8	0	0
T8	1736	1	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T54	3088	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	708583	0	0
T1	1604	598	0	0
T2	1739	525	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	404	0	0
T8	0	64	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	158	0	0
T56	0	186	0	0
T68	0	388	0	0
T69	0	79	0	0
T111	0	151	0	0
T112	0	644	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	57	0	0
T1	1604	2	0	0
T2	1739	1	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	1	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6255619	0	0
T1	1604	47	0	0
T2	1739	396	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	7323	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6258052	0	0
T1	1604	48	0	0
T2	1739	397	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	7350	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	126	0	0
T1	1604	2	0	0
T2	1739	1	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	3	0	0
T8	0	4	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	5	0	0
T67	0	8	0	0
T68	0	2	0	0
T69	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	65	0	0
T1	1604	2	0	0
T2	1739	1	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	2	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	57	0	0
T1	1604	2	0	0
T2	1739	1	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	1	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	57	0	0
T1	1604	2	0	0
T2	1739	1	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	1	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	708526	0	0
T1	1604	596	0	0
T2	1739	524	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	403	0	0
T8	0	63	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	157	0	0
T56	0	185	0	0
T68	0	386	0	0
T69	0	78	0	0
T111	0	150	0	0
T112	0	642	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7043	0	0
T1	1604	7	0	0
T2	1739	7	0	0
T3	12717	36	0	0
T4	4882	30	0	0
T5	13605	13	0	0
T6	17688	57	0	0
T12	7140	22	0	0
T13	421	1	0	0
T14	2065	4	0	0
T15	781	0	0	0
T20	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	267123	0	0
T1	1604	430	0	0
T2	1739	327	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	252	0	0
T8	0	115	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	150	0	0
T56	0	82	0	0
T68	0	85	0	0
T69	0	402	0	0
T111	0	198	0	0
T112	0	437	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T8,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T67,T68
0	1	Covered	T8,T56,T76
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T67,T68
0	1	Unreachable
1	0	Covered	T6,T67,T68

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T6
DetectSt	168	Covered	T6,T8,T56
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T67,T68

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T56
DebounceSt->IdleSt	163	Covered	T1,T2,T8
DetectSt->IdleSt	186	Covered	T8,T56,T76
DetectSt->StableSt	191	Covered	T6,T67,T68
IdleSt->DebounceSt	148	Covered	T1,T2,T6
StableSt->IdleSt	206	Covered	T6,T67,T68

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T56
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T2,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T8,T56,T76
DetectSt	-	-	-	-	0	1	-	Covered	T6,T67,T68
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T67,T68
StableSt	-	-	-	-	-	-	0	Covered	T6,T67,T68
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	209	0	0
CntIncr_A	8886315	307787	0	0
CntNoWrap_A	8886315	8213891	0	0
DetectStDropOut_A	8886315	18	0	0
DetectedOut_A	8886315	275203	0	0
DetectedPulseOut_A	8886315	54	0	0
DisabledIdleSt_A	8886315	6255619	0	0
DisabledNoDetection_A	8886315	6258052	0	0
EnterDebounceSt_A	8886315	138	0	0
EnterDetectSt_A	8886315	72	0	0
EnterStableSt_A	8886315	54	0	0
PulseIsPulse_A	8886315	54	0	0
StayInStableSt	8886315	275149	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_sticky_sva.StableStDropOut_A	8886315	910060	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	209	0	0
T1	1604	7	0	0
T2	1739	5	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	4	0	0
T8	0	8	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	2	0	0
T56	0	4	0	0
T57	0	5	0	0
T67	0	6	0	0
T68	0	4	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	307787	0	0
T1	1604	511	0	0
T2	1739	430	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	84	0	0
T8	0	500	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	32	0	0
T56	0	72	0	0
T57	0	210	0	0
T67	0	267	0	0
T68	0	92	0	0
T69	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213891	0	0
T1	1604	1196	0	0
T2	1739	1333	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8408	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	18	0	0
T8	1736	3	0	0
T9	1090	0	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T54	3088	0	0	0
T56	0	1	0	0
T76	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T116	0	1	0	0
T117	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0
T121	0	4	0	0
T122	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	275203	0	0
T6	17688	237	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0
T67	0	921	0	0
T68	0	189	0	0
T69	0	500	0	0
T76	0	200	0	0
T78	0	20792	0	0
T90	0	67	0	0
T94	0	249	0	0
T111	0	120	0	0
T112	0	489	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	54	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T76	0	2	0	0
T78	0	1	0	0
T90	0	1	0	0
T94	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6255619	0	0
T1	1604	47	0	0
T2	1739	396	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	7323	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6258052	0	0
T1	1604	48	0	0
T2	1739	397	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	7350	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	138	0	0
T1	1604	7	0	0
T2	1739	5	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	2	0	0
T8	0	5	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	2	0	0
T56	0	3	0	0
T57	0	5	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	72	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	3	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T78	0	1	0	0
T90	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	54	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T76	0	2	0	0
T78	0	1	0	0
T90	0	1	0	0
T94	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	54	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T76	0	2	0	0
T78	0	1	0	0
T90	0	1	0	0
T94	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	275149	0	0
T6	17688	235	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0
T67	0	918	0	0
T68	0	187	0	0
T69	0	499	0	0
T76	0	198	0	0
T78	0	20791	0	0
T90	0	66	0	0
T94	0	248	0	0
T111	0	119	0	0
T112	0	487	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	910060	0	0
T6	17688	723	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0
T67	0	641	0	0
T68	0	376	0	0
T69	0	65	0	0
T76	0	146	0	0
T78	0	48	0	0
T90	0	71	0	0
T94	0	86	0	0
T111	0	228	0	0
T112	0	594	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T1,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T2,T4,T12
1	1	Covered	T1,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Covered	T55,T76,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T8
0	1	Unreachable
1	0	Covered	T1,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T6
DetectSt	168	Covered	T1,T6,T8
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T1,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T8
DebounceSt->IdleSt	163	Covered	T2,T6,T55
DetectSt->IdleSt	186	Covered	T55,T76,T77
DetectSt->StableSt	191	Covered	T1,T6,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T6
StableSt->IdleSt	206	Covered	T1,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T8
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T6,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T55,T76,T77
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	201	0	0
CntIncr_A	8886315	125110	0	0
CntNoWrap_A	8886315	8213899	0	0
DetectStDropOut_A	8886315	14	0	0
DetectedOut_A	8886315	356750	0	0
DetectedPulseOut_A	8886315	59	0	0
DisabledIdleSt_A	8886315	6255619	0	0
DisabledNoDetection_A	8886315	6258052	0	0
EnterDebounceSt_A	8886315	129	0	0
EnterDetectSt_A	8886315	73	0	0
EnterStableSt_A	8886315	59	0	0
PulseIsPulse_A	8886315	59	0	0
StayInStableSt	8886315	356691	0	0
gen_high_event_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_sticky_sva.StableStDropOut_A	8886315	748997	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	201	0	0
T1	1604	4	0	0
T2	1739	5	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	6	0	0
T8	0	4	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	5	0	0
T56	0	2	0	0
T57	0	5	0	0
T67	0	6	0	0
T68	0	4	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	125110	0	0
T1	1604	22	0	0
T2	1739	120	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	430	0	0
T8	0	158	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	279	0	0
T56	0	22	0	0
T57	0	190	0	0
T67	0	279	0	0
T68	0	80	0	0
T69	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213899	0	0
T1	1604	1199	0	0
T2	1739	1333	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8406	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	14	0	0
T35	541	0	0	0
T42	19468	0	0	0
T55	1545	2	0	0
T56	758	0	0	0
T60	494	0	0	0
T61	1379	0	0	0
T76	0	1	0	0
T77	0	3	0	0
T118	0	1	0	0
T123	0	1	0	0
T124	0	2	0	0
T125	0	3	0	0
T126	0	1	0	0
T127	524	0	0	0
T128	522	0	0	0
T129	502	0	0	0
T130	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	356750	0	0
T1	1604	75	0	0
T2	1739	0	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	157	0	0
T8	0	289	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T56	0	95	0	0
T67	0	619	0	0
T68	0	118	0	0
T69	0	246	0	0
T111	0	294	0	0
T112	0	396	0	0
T113	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	59	0	0
T1	1604	2	0	0
T2	1739	0	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	2	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6255619	0	0
T1	1604	47	0	0
T2	1739	396	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	7323	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6258052	0	0
T1	1604	48	0	0
T2	1739	397	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	7350	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	129	0	0
T1	1604	2	0	0
T2	1739	5	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	5	0	0
T8	0	2	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	3	0	0
T56	0	1	0	0
T57	0	5	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	73	0	0
T1	1604	2	0	0
T2	1739	0	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	2	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	59	0	0
T1	1604	2	0	0
T2	1739	0	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	2	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	59	0	0
T1	1604	2	0	0
T2	1739	0	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T8	0	2	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T56	0	1	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	356691	0	0
T1	1604	73	0	0
T2	1739	0	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	156	0	0
T8	0	287	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T56	0	94	0	0
T67	0	616	0	0
T68	0	116	0	0
T69	0	245	0	0
T111	0	293	0	0
T112	0	394	0	0
T113	0	126	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	748997	0	0
T1	1604	1045	0	0
T2	1739	0	0	0
T3	12717	0	0	0
T4	4882	0	0	0
T5	13605	0	0	0
T6	17688	96	0	0
T8	0	214	0	0
T12	7140	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T56	0	204	0	0
T67	0	951	0	0
T68	0	467	0	0
T69	0	373	0	0
T111	0	46	0	0
T112	0	743	0	0
T113	0	315	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T29,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T9,T29,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T29,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T9,T29,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T29,T32
0	1	Covered	T73,T120
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T29,T32
0	1	Covered	T29,T39,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T29,T32
1	-	Covered	T29,T39,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T29,T32
DetectSt	168	Covered	T9,T29,T32
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T9,T29,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T29,T32
DebounceSt->IdleSt	163	Covered	T114,T70,T71
DetectSt->IdleSt	186	Covered	T73,T120
DetectSt->StableSt	191	Covered	T9,T29,T32
IdleSt->DebounceSt	148	Covered	T9,T29,T32
StableSt->IdleSt	206	Covered	T29,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T29,T32
0	1	Covered	T9,T29,T32
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T29,T32
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T29,T32
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T29,T32
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T29,T32
DetectSt	-	-	-	-	1	-	-	Covered	T73,T120
DetectSt	-	-	-	-	0	1	-	Covered	T9,T29,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T39,T36
StableSt	-	-	-	-	-	-	0	Covered	T9,T29,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	70	0	0
CntIncr_A	8886315	79912	0	0
CntNoWrap_A	8886315	8214030	0	0
DetectStDropOut_A	8886315	2	0	0
DetectedOut_A	8886315	2762	0	0
DetectedPulseOut_A	8886315	32	0	0
DisabledIdleSt_A	8886315	7772536	0	0
DisabledNoDetection_A	8886315	7774917	0	0
EnterDebounceSt_A	8886315	37	0	0
EnterDetectSt_A	8886315	34	0	0
EnterStableSt_A	8886315	32	0	0
PulseIsPulse_A	8886315	32	0	0
StayInStableSt	8886315	2709	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	70	0	0
T9	1090	2	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T36	0	4	0	0
T39	0	4	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	79912	0	0
T9	1090	73	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	60	0	0
T32	0	76	0	0
T34	0	44	0	0
T36	0	78056	0	0
T39	0	48	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	70	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	88	0	0
T131	0	40	0	0
T132	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8214030	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2	0	0
T73	762	1	0	0
T95	6670	0	0	0
T119	1245	0	0	0
T120	0	1	0	0
T133	406	0	0	0
T134	724	0	0	0
T135	713	0	0	0
T136	424	0	0	0
T137	11411	0	0	0
T138	13283	0	0	0
T139	8439	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2762	0	0
T9	1090	184	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	43	0	0
T32	0	459	0	0
T34	0	192	0	0
T36	0	51	0	0
T39	0	118	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	237	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	43	0	0
T131	0	46	0	0
T132	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	32	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7772536	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7774917	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	37	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	34	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	32	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	32	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T39	0	2	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2709	0	0
T9	1090	182	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	42	0	0
T32	0	457	0	0
T34	0	190	0	0
T36	0	48	0	0
T39	0	115	0	0
T45	597	0	0	0
T54	3088	0	0	0
T76	0	235	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	41	0	0
T131	0	44	0	0
T132	0	35	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	11	0	0
T23	7818	0	0	0
T26	16346	0	0	0
T27	2312	0	0	0
T29	11868	1	0	0
T30	505	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T132	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	696	0	0	0
T147	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T29,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T9,T29,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T29,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T29
1	0	Covered	T3,T13,T14
1	1	Covered	T9,T29,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T29,T38
0	1	Covered	T148,T149
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T29,T38
0	1	Covered	T9,T29,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T29,T38
1	-	Covered	T9,T29,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T29,T38
DetectSt	168	Covered	T9,T29,T38
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T9,T29,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T29,T38
DebounceSt->IdleSt	163	Covered	T150,T70,T151
DetectSt->IdleSt	186	Covered	T148,T149
DetectSt->StableSt	191	Covered	T9,T29,T38
IdleSt->DebounceSt	148	Covered	T9,T29,T38
StableSt->IdleSt	206	Covered	T9,T29,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T29,T38
0	1	Covered	T9,T29,T38
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T29,T38
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T29,T38
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T29,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T29,T38
DetectSt	-	-	-	-	1	-	-	Covered	T148,T149
DetectSt	-	-	-	-	0	1	-	Covered	T9,T29,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T29,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T29,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	100	0	0
CntIncr_A	8886315	129343	0	0
CntNoWrap_A	8886315	8214000	0	0
DetectStDropOut_A	8886315	2	0	0
DetectedOut_A	8886315	4274	0	0
DetectedPulseOut_A	8886315	46	0	0
DisabledIdleSt_A	8886315	7931011	0	0
DisabledNoDetection_A	8886315	7933402	0	0
EnterDebounceSt_A	8886315	53	0	0
EnterDetectSt_A	8886315	48	0	0
EnterStableSt_A	8886315	46	0	0
PulseIsPulse_A	8886315	46	0	0
StayInStableSt	8886315	4203	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	2713	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	100	0	0
T9	1090	2	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	6	0	0
T34	0	2	0	0
T38	0	2	0	0
T45	597	0	0	0
T54	3088	0	0	0
T70	0	1	0	0
T73	0	4	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	2	0	0
T131	0	2	0	0
T150	0	1	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	129343	0	0
T9	1090	73	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	210	0	0
T34	0	44	0	0
T38	0	75	0	0
T45	597	0	0	0
T54	3088	0	0	0
T70	0	28	0	0
T73	0	58	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	88	0	0
T131	0	40	0	0
T150	0	85	0	0
T152	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8214000	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2	0	0
T124	313261	0	0	0
T148	874	1	0	0
T149	0	1	0	0
T153	9188	0	0	0
T154	5416	0	0	0
T155	5449	0	0	0
T156	527	0	0	0
T157	403	0	0	0
T158	436	0	0	0
T159	440	0	0	0
T160	10081	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	4274	0	0
T9	1090	350	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	392	0	0
T34	0	91	0	0
T38	0	40	0	0
T45	597	0	0	0
T54	3088	0	0	0
T73	0	141	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	130	0	0
T131	0	160	0	0
T152	0	116	0	0
T161	0	44	0	0
T162	0	279	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	3	0	0
T34	0	1	0	0
T38	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T73	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7931011	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7933402	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	53	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	3	0	0
T34	0	1	0	0
T38	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T70	0	1	0	0
T73	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	48	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	3	0	0
T34	0	1	0	0
T38	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T73	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	3	0	0
T34	0	1	0	0
T38	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T73	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	3	0	0
T34	0	1	0	0
T38	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T73	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T131	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0
T162	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	4203	0	0
T9	1090	349	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	387	0	0
T34	0	90	0	0
T38	0	38	0	0
T45	597	0	0	0
T54	3088	0	0	0
T73	0	139	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	129	0	0
T131	0	159	0	0
T152	0	114	0	0
T161	0	43	0	0
T162	0	276	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2713	0	0
T3	12717	26	0	0
T5	13605	0	0	0
T6	17688	46	0	0
T7	17691	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T13	421	2	0	0
T14	2065	6	0	0
T15	781	0	0	0
T20	503	4	0	0
T21	0	5	0	0
T52	79762	0	0	0
T53	423	2	0	0
T82	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	21	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T29	0	1	0	0
T34	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T73	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T112	0	1	0	0
T120	0	1	0	0
T131	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0