Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T35,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T10,T35,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T35,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T10,T29
1	0	Covered	T1,T2,T4
1	1	Covered	T10,T35,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T33
0	1	Covered	T10,T73,T114
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T35,T33
1	-	Covered	T10,T73,T114

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T35,T33
DetectSt	168	Covered	T10,T35,T33
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T10,T35,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T35,T33
DebounceSt->IdleSt	163	Covered	T70,T164,T143
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T35,T33
IdleSt->DebounceSt	148	Covered	T10,T35,T33
StableSt->IdleSt	206	Covered	T10,T112,T76

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T35,T33
0	1	Covered	T10,T35,T33
0	0	Excluded	T1,T2,T4	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T35,T33
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T35,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T35,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T143
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T35,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T35,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T73,T114
StableSt	-	-	-	-	-	-	0	Covered	T10,T35,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	69	0	0
CntIncr_A	8886315	133818	0	0
CntNoWrap_A	8886315	8214031	0	0
DetectStDropOut_A	8886315	0	0	0
DetectedOut_A	8886315	106060	0	0
DetectedPulseOut_A	8886315	33	0	0
DisabledIdleSt_A	8886315	7764312	0	0
DisabledNoDetection_A	8886315	7766692	0	0
EnterDebounceSt_A	8886315	37	0	0
EnterDetectSt_A	8886315	33	0	0
EnterStableSt_A	8886315	33	0	0
PulseIsPulse_A	8886315	33	0	0
StayInStableSt	8886315	106002	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	8	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8886315	69
T10	889	2
T11	9850	0
T21	522	0
T33	0	2
T35	0	2
T45	597	0
T46	789	0
T54	3088	0
T73	0	4
T76	0	2
T80	0	2
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	2
T114	0	2
T132	0	2
T165	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8886315	133818
T10	889	57
T11	9850	0
T21	522	0
T33	0	73
T35	0	38
T45	597	0
T46	789	0
T54	3088	0
T73	0	58
T76	0	70
T80	0	44
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	70
T114	0	23
T132	0	48
T165	0	86

CntNoWrap_A

Name	Attempts	Real Successes
Total	8886315	8214031
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8412
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8886315	106060
T10	889	44
T11	9850	0
T21	522	0
T33	0	41
T35	0	41
T45	597	0
T46	789	0
T54	3088	0
T73	0	96
T76	0	238
T80	0	40
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	43
T114	0	69
T132	0	43
T165	0	45

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8886315	33
T10	889	1
T11	9850	0
T21	522	0
T33	0	1
T35	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T76	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T114	0	1
T132	0	1
T165	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8886315	7764312
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8228
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8886315	7766692
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8254
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8886315	37
T10	889	1
T11	9850	0
T21	522	0
T33	0	1
T35	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T76	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T114	0	1
T132	0	1
T165	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8886315	33
T10	889	1
T11	9850	0
T21	522	0
T33	0	1
T35	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T76	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T114	0	1
T132	0	1
T165	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8886315	33
T10	889	1
T11	9850	0
T21	522	0
T33	0	1
T35	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T76	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T114	0	1
T132	0	1
T165	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8886315	33
T10	889	1
T11	9850	0
T21	522	0
T33	0	1
T35	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T76	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T114	0	1
T132	0	1
T165	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8886315	106002
T10	889	43
T11	9850	0
T21	522	0
T33	0	39
T35	0	39
T45	597	0
T46	789	0
T54	3088	0
T73	0	94
T76	0	236
T80	0	38
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	41
T114	0	68
T132	0	41
T165	0	43

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8886315	8216536
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8886315	8
T10	889	1
T11	9850	0
T21	522	0
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T114	0	1
T151	0	1
T166	0	1
T167	0	1
T168	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T29,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T10,T29,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T29,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T29,T31
1	0	Covered	T3,T13,T14
1	1	Covered	T10,T29,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T29,T31
0	1	Covered	T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T29,T31
0	1	Covered	T10,T29,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T29,T31
1	-	Covered	T10,T29,T35

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T29,T31
DetectSt	168	Covered	T10,T29,T31
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T10,T29,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T29,T31
DebounceSt->IdleSt	163	Covered	T80,T70,T162
DetectSt->IdleSt	186	Covered	T72
DetectSt->StableSt	191	Covered	T10,T29,T31
IdleSt->DebounceSt	148	Covered	T10,T29,T31
StableSt->IdleSt	206	Covered	T10,T29,T35

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T29,T31
0	1	Covered	T10,T29,T31
0	0	Excluded	T1,T2,T4	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T29,T31
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T29,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T29,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T162,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T29,T31
DetectSt	-	-	-	-	1	-	-	Covered	T72
DetectSt	-	-	-	-	0	1	-	Covered	T10,T29,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T29,T35
StableSt	-	-	-	-	-	-	0	Covered	T10,T29,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	121	0	0
CntIncr_A	8886315	231115	0	0
CntNoWrap_A	8886315	8213979	0	0
DetectStDropOut_A	8886315	1	0	0
DetectedOut_A	8886315	68792	0	0
DetectedPulseOut_A	8886315	56	0	0
DisabledIdleSt_A	8886315	7599456	0	0
DisabledNoDetection_A	8886315	7601840	0	0
EnterDebounceSt_A	8886315	64	0	0
EnterDetectSt_A	8886315	57	0	0
EnterStableSt_A	8886315	56	0	0
PulseIsPulse_A	8886315	56	0	0
StayInStableSt	8886315	68716	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	2992	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	36	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8886315	121
T10	889	4
T11	9850	0
T21	522	0
T29	0	4
T31	0	2
T33	0	2
T35	0	2
T37	0	4
T39	0	2
T45	597	0
T46	789	0
T54	3088	0
T72	0	4
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	8886315	231115
T10	889	114
T11	9850	0
T21	522	0
T29	0	150
T31	0	69
T33	0	73
T35	0	38
T37	0	120
T39	0	24
T45	597	0
T46	789	0
T54	3088	0
T72	0	180
T80	0	44
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	88

CntNoWrap_A

Name	Attempts	Real Successes
Total	8886315	8213979
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8412
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8886315	1
T33	669	0
T66	5466	0
T67	2353	0
T72	1189	1
T102	18044	0
T108	749	0
T170	446	0
T171	527	0
T172	403	0
T173	433	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8886315	68792
T10	889	189
T11	9850	0
T21	522	0
T29	0	213
T31	0	41
T33	0	71
T35	0	14
T37	0	152
T39	0	77
T45	597	0
T46	789	0
T54	3088	0
T72	0	81
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	39
T132	0	129

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8886315	56
T10	889	2
T11	9850	0
T21	522	0
T29	0	2
T31	0	1
T33	0	1
T35	0	1
T37	0	2
T39	0	1
T45	597	0
T46	789	0
T54	3088	0
T72	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T132	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8886315	7599456
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8412
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8886315	7601840
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8886315	64
T10	889	2
T11	9850	0
T21	522	0
T29	0	2
T31	0	1
T33	0	1
T35	0	1
T37	0	2
T39	0	1
T45	597	0
T46	789	0
T54	3088	0
T72	0	2
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8886315	57
T10	889	2
T11	9850	0
T21	522	0
T29	0	2
T31	0	1
T33	0	1
T35	0	1
T37	0	2
T39	0	1
T45	597	0
T46	789	0
T54	3088	0
T72	0	2
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T132	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8886315	56
T10	889	2
T11	9850	0
T21	522	0
T29	0	2
T31	0	1
T33	0	1
T35	0	1
T37	0	2
T39	0	1
T45	597	0
T46	789	0
T54	3088	0
T72	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T132	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8886315	56
T10	889	2
T11	9850	0
T21	522	0
T29	0	2
T31	0	1
T33	0	1
T35	0	1
T37	0	2
T39	0	1
T45	597	0
T46	789	0
T54	3088	0
T72	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T132	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8886315	68716
T10	889	186
T11	9850	0
T21	522	0
T29	0	210
T31	0	39
T33	0	70
T35	0	13
T37	0	149
T39	0	76
T45	597	0
T46	789	0
T54	3088	0
T72	0	80
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	38
T132	0	128

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8886315	2992
T3	12717	29
T5	13605	0
T6	17688	61
T7	17691	0
T9	0	2
T10	0	2
T13	421	2
T14	2065	3
T15	781	5
T20	503	4
T52	79762	4
T53	423	2

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8886315	8216536
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8886315	36
T10	889	1
T11	9850	0
T21	522	0
T29	0	1
T33	0	1
T35	0	1
T37	0	1
T39	0	1
T45	597	0
T46	789	0
T54	3088	0
T72	0	1
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T112	0	1
T132	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T9,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T9,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T9,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T29
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T9,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T29
0	1	Covered	T36,T174,T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T29
0	1	Covered	T9,T29,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T29
1	-	Covered	T9,T29,T32

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T29
DetectSt	168	Covered	T6,T9,T29
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T9,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T29
DebounceSt->IdleSt	163	Covered	T34,T80,T70
DetectSt->IdleSt	186	Covered	T36,T174,T169
DetectSt->StableSt	191	Covered	T6,T9,T29
IdleSt->DebounceSt	148	Covered	T6,T9,T29
StableSt->IdleSt	206	Covered	T6,T9,T29

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T29
0	1	Covered	T6,T9,T29
0	0	Excluded	T1,T2,T4	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T29
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T29
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T80,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T29
DetectSt	-	-	-	-	1	-	-	Covered	T36,T174,T169
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T29,T32
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	147	0	0
CntIncr_A	8886315	189404	0	0
CntNoWrap_A	8886315	8213953	0	0
DetectStDropOut_A	8886315	6	0	0
DetectedOut_A	8886315	80326	0	0
DetectedPulseOut_A	8886315	65	0	0
DisabledIdleSt_A	8886315	7678752	0	0
DisabledNoDetection_A	8886315	7681121	0	0
EnterDebounceSt_A	8886315	77	0	0
EnterDetectSt_A	8886315	71	0	0
EnterStableSt_A	8886315	65	0	0
PulseIsPulse_A	8886315	65	0	0
StayInStableSt	8886315	80229	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	33	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8886315	147
T6	17688	2
T7	17691	0
T8	1736	0
T9	1090	4
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	4
T31	0	2
T32	0	4
T33	0	2
T34	0	1
T36	0	4
T37	0	2
T52	79762	0
T53	423	0
T80	0	1

CntIncr_A

Name	Attempts	Real Successes
Total	8886315	189404
T6	17688	89
T7	17691	0
T8	1736	0
T9	1090	146
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	120
T31	0	69
T32	0	152
T33	0	73
T34	0	44
T36	0	78056
T37	0	60
T52	79762	0
T53	423	0
T80	0	44

CntNoWrap_A

Name	Attempts	Real Successes
Total	8886315	8213953
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8410
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8886315	6
T34	781	0
T36	229395	1
T86	5316	0
T148	0	1
T169	0	1
T174	0	1
T176	0	2
T177	788	0
T178	522	0
T179	7037	0
T180	737	0
T181	1408	0
T182	32376	0
T183	406	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8886315	80326
T6	17688	43
T7	17691	0
T8	1736	0
T9	1090	302
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	195
T31	0	111
T32	0	363
T33	0	42
T36	0	50
T37	0	108
T52	79762	0
T53	423	0
T76	0	338
T94	0	115

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8886315	65
T6	17688	1
T7	17691	0
T8	1736	0
T9	1090	2
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	2
T31	0	1
T32	0	2
T33	0	1
T36	0	1
T37	0	1
T52	79762	0
T53	423	0
T76	0	2
T94	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8886315	7678752
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8228
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8886315	7681121
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8254
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8886315	77
T6	17688	1
T7	17691	0
T8	1736	0
T9	1090	2
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	2
T31	0	1
T32	0	2
T33	0	1
T34	0	1
T36	0	2
T37	0	1
T52	79762	0
T53	423	0
T80	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8886315	71
T6	17688	1
T7	17691	0
T8	1736	0
T9	1090	2
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	2
T31	0	1
T32	0	2
T33	0	1
T36	0	2
T37	0	1
T52	79762	0
T53	423	0
T76	0	2
T94	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	8886315	65
T6	17688	1
T7	17691	0
T8	1736	0
T9	1090	2
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	2
T31	0	1
T32	0	2
T33	0	1
T36	0	1
T37	0	1
T52	79762	0
T53	423	0
T76	0	2
T94	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8886315	65
T6	17688	1
T7	17691	0
T8	1736	0
T9	1090	2
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	2
T31	0	1
T32	0	2
T33	0	1
T36	0	1
T37	0	1
T52	79762	0
T53	423	0
T76	0	2
T94	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	8886315	80229
T6	17688	41
T7	17691	0
T8	1736	0
T9	1090	300
T10	889	0
T20	503	0
T21	522	0
T22	610	0
T29	0	192
T31	0	109
T32	0	360
T33	0	40
T36	0	48
T37	0	107
T52	79762	0
T53	423	0
T76	0	335
T94	0	112

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8886315	8216536
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8886315	33
T9	1090	2
T10	889	0
T11	9850	0
T21	522	0
T29	0	1
T32	0	1
T37	0	1
T45	597	0
T54	3088	0
T73	0	1
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T94	0	1
T141	0	1
T184	0	1
T185	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T10,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T29
1	0	Covered	T1,T2,T4
1	1	Covered	T10,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T36,T37
0	1	Covered	T186
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T36,T37
0	1	Covered	T36,T131,T73
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T36,T37
1	-	Covered	T36,T131,T73

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T36,T37
DetectSt	168	Covered	T10,T36,T37
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T10,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T36,T37
DebounceSt->IdleSt	163	Covered	T152,T70,T187
DetectSt->IdleSt	186	Covered	T186
DetectSt->StableSt	191	Covered	T10,T36,T37
IdleSt->DebounceSt	148	Covered	T10,T36,T37
StableSt->IdleSt	206	Covered	T36,T131,T76

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T36,T37
0	1	Covered	T10,T36,T37
0	0	Excluded	T1,T2,T4	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T36,T37
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T152,T187,T188
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T186
DetectSt	-	-	-	-	0	1	-	Covered	T10,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T131,T73
StableSt	-	-	-	-	-	-	0	Covered	T10,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	67	0	0
CntIncr_A	8886315	114833	0	0
CntNoWrap_A	8886315	8214033	0	0
DetectStDropOut_A	8886315	1	0	0
DetectedOut_A	8886315	152045	0	0
DetectedPulseOut_A	8886315	29	0	0
DisabledIdleSt_A	8886315	7624803	0	0
DisabledNoDetection_A	8886315	7627187	0	0
EnterDebounceSt_A	8886315	37	0	0
EnterDetectSt_A	8886315	30	0	0
EnterStableSt_A	8886315	29	0	0
PulseIsPulse_A	8886315	29	0	0
StayInStableSt	8886315	152001	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	6753	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	14	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8886315	67
T10	889	2
T11	9850	0
T21	522	0
T36	0	2
T37	0	2
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T76	0	2
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	2
T132	0	2
T141	0	2
T152	0	1
T167	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	8886315	114833
T10	889	57
T11	9850	0
T21	522	0
T36	0	39028
T37	0	60
T45	597	0
T46	789	0
T54	3088	0
T73	0	29
T76	0	17
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	40
T132	0	48
T141	0	33
T152	0	13
T167	0	74074

CntNoWrap_A

Name	Attempts	Real Successes
Total	8886315	8214033
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8412
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8886315	1
T161	596	0
T162	9428	0
T186	16179	1
T189	9246	0
T190	404	0
T191	495	0
T192	1065	0
T193	493	0
T194	404	0
T195	524	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8886315	152045
T10	889	248
T11	9850	0
T21	522	0
T36	0	54427
T37	0	199
T45	597	0
T46	789	0
T54	3088	0
T73	0	27
T76	0	56
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	43
T132	0	128
T141	0	42
T167	0	95856
T196	0	40

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8886315	29
T10	889	1
T11	9850	0
T21	522	0
T36	0	1
T37	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T132	0	1
T141	0	1
T167	0	2
T196	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8886315	7624803
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8412
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8886315	7627187
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8886315	37
T10	889	1
T11	9850	0
T21	522	0
T36	0	1
T37	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T132	0	1
T141	0	1
T152	0	1
T167	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8886315	30
T10	889	1
T11	9850	0
T21	522	0
T36	0	1
T37	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T132	0	1
T141	0	1
T167	0	2
T196	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8886315	29
T10	889	1
T11	9850	0
T21	522	0
T36	0	1
T37	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T132	0	1
T141	0	1
T167	0	2
T196	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8886315	29
T10	889	1
T11	9850	0
T21	522	0
T36	0	1
T37	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T132	0	1
T141	0	1
T167	0	2
T196	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8886315	152001
T10	889	246
T11	9850	0
T21	522	0
T36	0	54426
T37	0	197
T45	597	0
T46	789	0
T54	3088	0
T73	0	26
T76	0	54
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	42
T132	0	126
T141	0	41
T167	0	95853
T196	0	39

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8886315	6753
T1	1604	7
T2	1739	7
T3	12717	33
T4	4882	20
T5	13605	13
T6	17688	60
T12	7140	29
T13	421	3
T14	2065	4
T15	781	0
T20	0	6

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8886315	8216536
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8886315	14
T34	781	0
T36	229395	1
T73	0	1
T86	5316	0
T131	0	1
T141	0	1
T142	0	1
T148	0	1
T167	0	1
T177	788	0
T178	522	0
T179	7037	0
T180	737	0
T181	1408	0
T182	32376	0
T183	406	0
T187	0	1
T196	0	1
T197	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T12,T3
1	1	Covered	T4,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T6,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T6,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T6,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T10
1	0	Covered	T4,T12,T3
1	1	Covered	T3,T6,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T30,T198,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T10
0	1	Covered	T10,T29,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T10
1	-	Covered	T10,T29,T35

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T10
DetectSt	168	Covered	T3,T6,T10
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T6,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T10
DebounceSt->IdleSt	163	Covered	T80,T150,T152
DetectSt->IdleSt	186	Covered	T30,T198,T175
DetectSt->StableSt	191	Covered	T3,T6,T10
IdleSt->DebounceSt	148	Covered	T3,T6,T10
StableSt->IdleSt	206	Covered	T3,T6,T10

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T10
0	1	Covered	T3,T6,T10
0	0	Excluded	T1,T2,T4	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T10
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T150,T152
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	1	-	-	Covered	T30,T198,T175
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T29,T35
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	119	0	0
CntIncr_A	8886315	61098	0	0
CntNoWrap_A	8886315	8213981	0	0
DetectStDropOut_A	8886315	3	0	0
DetectedOut_A	8886315	66558	0	0
DetectedPulseOut_A	8886315	52	0	0
DisabledIdleSt_A	8886315	8019161	0	0
DisabledNoDetection_A	8886315	8021548	0	0
EnterDebounceSt_A	8886315	64	0	0
EnterDetectSt_A	8886315	55	0	0
EnterStableSt_A	8886315	52	0	0
PulseIsPulse_A	8886315	52	0	0
StayInStableSt	8886315	66480	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	26	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8886315	119
T3	12717	2
T5	13605	0
T6	17688	2
T7	17691	0
T10	0	4
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	2
T30	0	2
T34	0	4
T35	0	2
T39	0	4
T52	79762	0
T53	423	0
T76	0	2
T80	0	1

CntIncr_A

Name	Attempts	Real Successes
Total	8886315	61098
T3	12717	89
T5	13605	0
T6	17688	71
T7	17691	0
T10	0	114
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	60
T30	0	27
T34	0	88
T35	0	38
T39	0	48
T52	79762	0
T53	423	0
T76	0	17
T80	0	44

CntNoWrap_A

Name	Attempts	Real Successes
Total	8886315	8213981
T1	1604	1203
T2	1739	1338
T3	12717	5872
T4	4882	4481
T5	13605	13178
T6	17688	8410
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8886315	3
T30	505	1
T41	26234	0
T58	494	0
T59	493	0
T63	503	0
T64	1764	0
T104	905	0
T105	586	0
T106	1646	0
T107	503	0
T175	0	1
T198	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	8886315	66558
T3	12717	210
T5	13605	0
T6	17688	40
T7	17691	0
T10	0	60
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	43
T34	0	152
T35	0	14
T39	0	63
T52	79762	0
T53	423	0
T76	0	2
T184	0	147
T199	0	22

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8886315	52
T3	12717	1
T5	13605	0
T6	17688	1
T7	17691	0
T10	0	2
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	1
T34	0	2
T35	0	1
T39	0	2
T52	79762	0
T53	423	0
T76	0	1
T184	0	2
T199	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8886315	8019161
T1	1604	1203
T2	1739	1338
T3	12717	5570
T4	4882	4481
T5	13605	13178
T6	17688	8032
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8886315	8021548
T1	1604	1204
T2	1739	1339
T3	12717	5594
T4	4882	4482
T5	13605	13183
T6	17688	8058
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8886315	64
T3	12717	1
T5	13605	0
T6	17688	1
T7	17691	0
T10	0	2
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	1
T30	0	1
T34	0	2
T35	0	1
T39	0	2
T52	79762	0
T53	423	0
T76	0	1
T80	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8886315	55
T3	12717	1
T5	13605	0
T6	17688	1
T7	17691	0
T10	0	2
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	1
T30	0	1
T34	0	2
T35	0	1
T39	0	2
T52	79762	0
T53	423	0
T76	0	1
T184	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	8886315	52
T3	12717	1
T5	13605	0
T6	17688	1
T7	17691	0
T10	0	2
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	1
T34	0	2
T35	0	1
T39	0	2
T52	79762	0
T53	423	0
T76	0	1
T184	0	2
T199	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8886315	52
T3	12717	1
T5	13605	0
T6	17688	1
T7	17691	0
T10	0	2
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	1
T34	0	2
T35	0	1
T39	0	2
T52	79762	0
T53	423	0
T76	0	1
T184	0	2
T199	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8886315	66480
T3	12717	208
T5	13605	0
T6	17688	38
T7	17691	0
T10	0	57
T13	421	0
T14	2065	0
T15	781	0
T20	503	0
T29	0	42
T34	0	149
T35	0	13
T39	0	60
T52	79762	0
T53	423	0
T76	0	1
T184	0	145
T199	0	21

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	8886315	8216536
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8886315	26
T10	889	1
T11	9850	0
T21	522	0
T29	0	1
T34	0	1
T35	0	1
T39	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T76	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T114	0	1
T184	0	2
T199	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T32,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T10,T32,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T10,T32,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T29,T31
1	0	Covered	T4,T12,T3
1	1	Covered	T10,T32,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T32,T35
0	1	Covered	T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T32,T35
0	1	Covered	T10,T32,T131
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T32,T35
1	-	Covered	T10,T32,T131

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T32,T35
DetectSt	168	Covered	T10,T32,T35
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T10,T32,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T32,T35
DebounceSt->IdleSt	163	Covered	T184,T70,T120
DetectSt->IdleSt	186	Covered	T73
DetectSt->StableSt	191	Covered	T10,T32,T35
IdleSt->DebounceSt	148	Covered	T10,T32,T35
StableSt->IdleSt	206	Covered	T10,T32,T38

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T32,T35
0	1	Covered	T10,T32,T35
0	0	Excluded	T1,T2,T4	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T10,T32,T35
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T32,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T32,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T184,T120,T200
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T32,T35
DetectSt	-	-	-	-	1	-	-	Covered	T73
DetectSt	-	-	-	-	0	1	-	Covered	T10,T32,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T32,T131
StableSt	-	-	-	-	-	-	0	Covered	T10,T32,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	82	0	0
CntIncr_A	8886315	76459	0	0
CntNoWrap_A	8886315	8214018	0	0
DetectStDropOut_A	8886315	1	0	0
DetectedOut_A	8886315	2878	0	0
DetectedPulseOut_A	8886315	37	0	0
DisabledIdleSt_A	8886315	7840177	0	0
DisabledNoDetection_A	8886315	7842558	0	0
EnterDebounceSt_A	8886315	45	0	0
EnterDetectSt_A	8886315	38	0	0
EnterStableSt_A	8886315	37	0	0
PulseIsPulse_A	8886315	37	0	0
StayInStableSt	8886315	2819	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	6416	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	15	0	0

CntClr_A

Name	Attempts	Real Successes
Total	8886315	82
T10	889	2
T11	9850	0
T21	522	0
T32	0	4
T35	0	2
T37	0	2
T38	0	2
T45	597	0
T46	789	0
T54	3088	0
T73	0	4
T80	0	2
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	2
T165	0	2
T184	0	3

CntIncr_A

Name	Attempts	Real Successes
Total	8886315	76459
T10	889	57
T11	9850	0
T21	522	0
T32	0	152
T35	0	38
T37	0	60
T38	0	75
T45	597	0
T46	789	0
T54	3088	0
T73	0	58
T80	0	44
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	40
T165	0	86
T184	0	166

CntNoWrap_A

Name	Attempts	Real Successes
Total	8886315	8214018
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8412
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DetectStDropOut_A

Name	Attempts	Real Successes
Total	8886315	1
T73	762	1
T95	6670	0
T119	1245	0
T133	406	0
T134	724	0
T135	713	0
T136	424	0
T137	11411	0
T138	13283	0
T139	8439	0

DetectedOut_A

Name	Attempts	Real Successes
Total	8886315	2878
T10	889	246
T11	9850	0
T21	522	0
T32	0	265
T35	0	41
T37	0	42
T38	0	40
T45	597	0
T46	789	0
T54	3088	0
T73	0	97
T80	0	41
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	37
T165	0	45
T184	0	130

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	8886315	37
T10	889	1
T11	9850	0
T21	522	0
T32	0	2
T35	0	1
T37	0	1
T38	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T165	0	1
T184	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	8886315	7840177
T1	1604	1203
T2	1739	1338
T3	12717	5874
T4	4882	4481
T5	13605	13178
T6	17688	8412
T12	7140	6739
T13	421	20
T14	2065	61
T15	781	380

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	8886315	7842558
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	8886315	45
T10	889	1
T11	9850	0
T21	522	0
T32	0	2
T35	0	1
T37	0	1
T38	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T165	0	1
T184	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	8886315	38
T10	889	1
T11	9850	0
T21	522	0
T32	0	2
T35	0	1
T37	0	1
T38	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	2
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T165	0	1
T184	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	8886315	37
T10	889	1
T11	9850	0
T21	522	0
T32	0	2
T35	0	1
T37	0	1
T38	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T165	0	1
T184	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	8886315	37
T10	889	1
T11	9850	0
T21	522	0
T32	0	2
T35	0	1
T37	0	1
T38	0	1
T45	597	0
T46	789	0
T54	3088	0
T73	0	1
T80	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	1
T165	0	1
T184	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	8886315	2819
T10	889	245
T11	9850	0
T21	522	0
T32	0	262
T35	0	39
T37	0	40
T38	0	38
T45	597	0
T46	789	0
T54	3088	0
T73	0	95
T80	0	39
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T131	0	36
T165	0	43
T184	0	128

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	8886315	6416
T3	12717	32
T4	4882	26
T5	13605	12
T6	17688	47
T7	0	9
T12	7140	22
T13	421	2
T14	2065	6
T15	781	0
T20	503	5
T52	79762	0
T53	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	8886315	8216536
T1	1604	1204
T2	1739	1339
T3	12717	5899
T4	4882	4482
T5	13605	13183
T6	17688	8439
T12	7140	6740
T13	421	21
T14	2065	65
T15	781	381

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	8886315	15
T10	889	1
T11	9850	0
T21	522	0
T32	0	1
T45	597	0
T46	789	0
T54	3088	0
T77	0	1
T82	422	0
T83	402	0
T84	441	0
T85	424	0
T125	0	1
T131	0	1
T141	0	1
T167	0	2
T186	0	1
T196	0	1
T201	0	1

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr