Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T12,T3
1	1	Covered	T4,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T10,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T10,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T10,T29

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T4,T12,T3
1	1	Covered	T3,T10,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T29
0	1	Covered	T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T29
0	1	Covered	T29,T72,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T10,T29
1	-	Covered	T29,T72,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T10,T11
DetectSt	168	Covered	T3,T10,T29
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T3,T10,T29

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T29
DebounceSt->IdleSt	163	Covered	T11,T31,T184
DetectSt->IdleSt	186	Covered	T114
DetectSt->StableSt	191	Covered	T3,T10,T29
IdleSt->DebounceSt	148	Covered	T3,T10,T11
StableSt->IdleSt	206	Covered	T3,T29,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T10,T11
0	1	Covered	T3,T10,T11
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T29
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T10,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T29
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T31,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	1	-	-	Covered	T114
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T29
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T29,T72,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T29
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	101	0	0
CntIncr_A	8886315	199377	0	0
CntNoWrap_A	8886315	8213999	0	0
DetectStDropOut_A	8886315	1	0	0
DetectedOut_A	8886315	16227	0	0
DetectedPulseOut_A	8886315	46	0	0
DisabledIdleSt_A	8886315	7672848	0	0
DisabledNoDetection_A	8886315	7675235	0	0
EnterDebounceSt_A	8886315	56	0	0
EnterDetectSt_A	8886315	47	0	0
EnterStableSt_A	8886315	46	0	0
PulseIsPulse_A	8886315	46	0	0
StayInStableSt	8886315	16157	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	101	0	0
T3	12717	2	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	2	0	0
T31	0	1	0	0
T32	0	2	0	0
T35	0	2	0	0
T40	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	2	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	199377	0	0
T3	12717	89	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	57	0	0
T11	0	48	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	60	0	0
T31	0	69	0	0
T32	0	76	0	0
T35	0	38	0	0
T40	0	25	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	26	0	0
T72	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213999	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5872	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1	0	0
T114	180475	1	0	0
T140	845	0	0	0
T202	2200	0	0	0
T203	452	0	0	0
T204	486	0	0	0
T205	2356	0	0	0
T206	295289	0	0	0
T207	493	0	0	0
T208	1038	0	0	0
T209	517	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	16227	0	0
T3	12717	209	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	47	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	192	0	0
T32	0	117	0	0
T35	0	93	0	0
T36	0	89	0	0
T37	0	170	0	0
T40	0	39	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	49	0	0
T72	0	33	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	1	0	0
T72	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7672848	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5570	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7675235	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5594	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	56	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	1	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	47	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	1	0	0
T72	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	1	0	0
T72	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	1	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	1	0	0
T72	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	16157	0	0
T3	12717	207	0	0
T5	13605	0	0	0
T6	17688	0	0	0
T7	17691	0	0	0
T10	0	45	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T29	0	191	0	0
T32	0	115	0	0
T35	0	91	0	0
T36	0	86	0	0
T37	0	169	0	0
T40	0	37	0	0
T52	79762	0	0	0
T53	423	0	0	0
T61	0	47	0	0
T72	0	32	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	22	0	0
T23	7818	0	0	0
T26	16346	0	0	0
T27	2312	0	0	0
T29	11868	1	0	0
T30	505	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T112	0	1	0	0
T132	0	1	0	0
T140	0	1	0	0
T146	696	0	0	0
T147	402	0	0	0
T186	0	2	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T31,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T11,T31,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T11,T31,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T31
1	0	Covered	T4,T12,T3
1	1	Covered	T11,T31,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T31,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T31,T34
0	1	Covered	T34,T132,T114
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T31,T34
1	-	Covered	T34,T132,T114

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T31,T34
DetectSt	168	Covered	T11,T31,T34
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T11,T31,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T31,T34
DebounceSt->IdleSt	163	Covered	T70,T71
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T31,T34
IdleSt->DebounceSt	148	Covered	T11,T31,T34
StableSt->IdleSt	206	Covered	T11,T34,T132

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T31,T34
0	1	Covered	T11,T31,T34
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T31,T34
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T31,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T31,T34
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T31,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T31,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T132,T114
StableSt	-	-	-	-	-	-	0	Covered	T11,T31,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	58	0	0
CntIncr_A	8886315	71345	0	0
CntNoWrap_A	8886315	8214042	0	0
DetectStDropOut_A	8886315	0	0	0
DetectedOut_A	8886315	64290	0	0
DetectedPulseOut_A	8886315	28	0	0
DisabledIdleSt_A	8886315	7906325	0	0
DisabledNoDetection_A	8886315	7908715	0	0
EnterDebounceSt_A	8886315	30	0	0
EnterDetectSt_A	8886315	28	0	0
EnterStableSt_A	8886315	28	0	0
PulseIsPulse_A	8886315	28	0	0
StayInStableSt	8886315	64246	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	6339	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	58	0	0
T11	9850	2	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	2	0	0
T34	0	2	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T70	0	1	0	0
T76	0	2	0	0
T114	0	2	0	0
T132	0	2	0	0
T140	0	2	0	0
T141	0	4	0	0
T199	0	2	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	71345	0	0
T11	9850	48	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	69	0	0
T34	0	44	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T70	0	29	0	0
T76	0	17	0	0
T114	0	11935	0	0
T132	0	48	0	0
T140	0	75	0	0
T141	0	66	0	0
T199	0	86	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8214042	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	64290	0	0
T11	9850	45	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	42	0	0
T34	0	102	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T76	0	55	0	0
T114	0	44	0	0
T120	0	42	0	0
T132	0	37	0	0
T140	0	40	0	0
T141	0	83	0	0
T199	0	43	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	28	0	0
T11	9850	1	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T76	0	1	0	0
T114	0	1	0	0
T120	0	1	0	0
T132	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T199	0	1	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7906325	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7908715	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	30	0	0
T11	9850	1	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T70	0	1	0	0
T76	0	1	0	0
T114	0	1	0	0
T132	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T199	0	1	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	28	0	0
T11	9850	1	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T76	0	1	0	0
T114	0	1	0	0
T120	0	1	0	0
T132	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T199	0	1	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	28	0	0
T11	9850	1	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T76	0	1	0	0
T114	0	1	0	0
T120	0	1	0	0
T132	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T199	0	1	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	28	0	0
T11	9850	1	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T76	0	1	0	0
T114	0	1	0	0
T120	0	1	0	0
T132	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T199	0	1	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	64246	0	0
T11	9850	43	0	0
T28	27746	0	0	0
T29	11868	0	0	0
T31	0	40	0	0
T34	0	101	0	0
T45	597	0	0	0
T46	789	0	0	0
T62	505	0	0	0
T76	0	53	0	0
T114	0	43	0	0
T120	0	40	0	0
T132	0	36	0	0
T140	0	39	0	0
T141	0	80	0	0
T199	0	41	0	0
T210	437	0	0	0
T211	445	0	0	0
T212	417	0	0	0
T213	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6339	0	0
T3	12717	37	0	0
T4	4882	29	0	0
T5	13605	11	0	0
T6	17688	48	0	0
T7	0	9	0	0
T12	7140	30	0	0
T13	421	3	0	0
T14	2065	4	0	0
T15	781	0	0	0
T20	503	8	0	0
T52	79762	0	0	0
T53	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	12	0	0
T34	781	1	0	0
T68	1134	0	0	0
T114	0	1	0	0
T132	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T145	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0
T178	522	0	0	0
T179	7037	0	0	0
T180	737	0	0	0
T181	1408	0	0	0
T182	32376	0	0	0
T183	406	0	0	0
T201	0	1	0	0
T214	0	1	0	0
T215	424	0	0	0
T216	489	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T4,T12,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T4,T12,T3
1	1	Covered	T4,T12,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T6,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T3,T6,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T35
1	0	Covered	T4,T12,T3
1	1	Covered	T3,T6,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T39,T40
0	1	Covered	T131,T217,T175
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T39,T40
0	1	Covered	T39,T40,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T39,T40
1	-	Covered	T39,T40,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T39
DetectSt	168	Covered	T6,T39,T40
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T39,T40
DebounceSt->IdleSt	163	Covered	T3,T184,T141
DetectSt->IdleSt	186	Covered	T131,T217,T175
DetectSt->StableSt	191	Covered	T6,T39,T40
IdleSt->DebounceSt	148	Covered	T3,T6,T39
StableSt->IdleSt	206	Covered	T6,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T39
0	1	Covered	T3,T6,T39
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T39,T40
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T12,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T184,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T39
DetectSt	-	-	-	-	1	-	-	Covered	T131,T217,T175
DetectSt	-	-	-	-	0	1	-	Covered	T6,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T40,T37
StableSt	-	-	-	-	-	-	0	Covered	T6,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	111	0	0
CntIncr_A	8886315	70730	0	0
CntNoWrap_A	8886315	8213989	0	0
DetectStDropOut_A	8886315	4	0	0
DetectedOut_A	8886315	50351	0	0
DetectedPulseOut_A	8886315	46	0	0
DisabledIdleSt_A	8886315	8027740	0	0
DisabledNoDetection_A	8886315	8030129	0	0
EnterDebounceSt_A	8886315	62	0	0
EnterDetectSt_A	8886315	50	0	0
EnterStableSt_A	8886315	46	0	0
PulseIsPulse_A	8886315	46	0	0
StayInStableSt	8886315	50284	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	111	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T37	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	4	0	0
T76	0	4	0	0
T131	0	4	0	0
T141	0	3	0	0
T184	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	70730	0	0
T3	12717	89	0	0
T5	13605	0	0	0
T6	17688	71	0	0
T7	17691	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T37	0	120	0	0
T39	0	24	0	0
T40	0	25	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	58	0	0
T76	0	87	0	0
T131	0	80	0	0
T141	0	66	0	0
T184	0	249	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213989	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5873	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8410	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	4	0	0
T91	6116	0	0	0
T92	5115	0	0	0
T113	892	0	0	0
T131	697	1	0	0
T132	3095	0	0	0
T175	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	426	0	0	0
T220	1019	0	0	0
T221	402	0	0	0
T222	34926	0	0	0
T223	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	50351	0	0
T6	17688	305	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T37	0	135	0	0
T39	0	8	0	0
T40	0	20	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	64	0	0
T76	0	142	0	0
T131	0	122	0	0
T141	0	105	0	0
T174	0	42	0	0
T184	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	2	0	0
T76	0	2	0	0
T131	0	1	0	0
T141	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8027740	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5570	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8032	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8030129	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5594	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8058	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	62	0	0
T3	12717	1	0	0
T5	13605	0	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T13	421	0	0	0
T14	2065	0	0	0
T15	781	0	0	0
T20	503	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	2	0	0
T76	0	2	0	0
T131	0	2	0	0
T141	0	2	0	0
T184	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	50	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	2	0	0
T76	0	2	0	0
T131	0	2	0	0
T141	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	2	0	0
T76	0	2	0	0
T131	0	1	0	0
T141	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	2	0	0
T76	0	2	0	0
T131	0	1	0	0
T141	0	1	0	0
T174	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	50284	0	0
T6	17688	303	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T37	0	133	0	0
T39	0	7	0	0
T40	0	19	0	0
T52	79762	0	0	0
T53	423	0	0	0
T73	0	61	0	0
T76	0	140	0	0
T131	0	120	0	0
T141	0	104	0	0
T174	0	40	0	0
T184	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	25	0	0
T34	781	0	0	0
T36	229395	0	0	0
T37	0	2	0	0
T39	15033	1	0	0
T40	519	1	0	0
T73	0	1	0	0
T76	0	2	0	0
T86	5316	0	0	0
T141	0	1	0	0
T177	788	0	0	0
T178	522	0	0	0
T179	7037	0	0	0
T180	737	0	0	0
T201	0	1	0	0
T214	0	1	0	0
T224	0	1	0	0
T225	0	1	0	0
T226	490	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T12,T3
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T9,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T9,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T29
1	0	Covered	T4,T12,T3
1	1	Covered	T9,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T32,T33
0	1	Covered	T227
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T32,T33
0	1	Covered	T32,T34,T94
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T32,T33
1	-	Covered	T32,T34,T94

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T32,T33
DetectSt	168	Covered	T9,T32,T33
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T9,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T32,T33
DebounceSt->IdleSt	163	Covered	T70,T143,T71
DetectSt->IdleSt	186	Covered	T227
DetectSt->StableSt	191	Covered	T9,T32,T33
IdleSt->DebounceSt	148	Covered	T9,T32,T33
StableSt->IdleSt	206	Covered	T32,T34,T112

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T32,T33
0	1	Covered	T9,T32,T33
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T32,T33
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T143
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T32,T33
DetectSt	-	-	-	-	1	-	-	Covered	T227
DetectSt	-	-	-	-	0	1	-	Covered	T9,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T34,T94
StableSt	-	-	-	-	-	-	0	Covered	T9,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	89	0	0
CntIncr_A	8886315	60181	0	0
CntNoWrap_A	8886315	8214011	0	0
DetectStDropOut_A	8886315	1	0	0
DetectedOut_A	8886315	2825	0	0
DetectedPulseOut_A	8886315	42	0	0
DisabledIdleSt_A	8886315	7930692	0	0
DisabledNoDetection_A	8886315	7933068	0	0
EnterDebounceSt_A	8886315	46	0	0
EnterDetectSt_A	8886315	43	0	0
EnterStableSt_A	8886315	42	0	0
PulseIsPulse_A	8886315	42	0	0
StayInStableSt	8886315	2759	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	6480	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	89	0	0
T9	1090	2	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	4	0	0
T40	0	2	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	2	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	4	0	0
T112	0	2	0	0
T132	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	60181	0	0
T9	1090	73	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	76	0	0
T33	0	73	0	0
T34	0	88	0	0
T40	0	25	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	44	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	24	0	0
T112	0	88	0	0
T132	0	48	0	0
T165	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8214011	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8412	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1	0	0
T227	647	1	0	0
T228	493	0	0	0
T229	7043	0	0	0
T230	1678	0	0	0
T231	33025	0	0	0
T232	22559	0	0	0
T233	178124	0	0	0
T234	12237	0	0	0
T235	499	0	0	0
T236	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2825	0	0
T9	1090	43	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	148	0	0
T33	0	41	0	0
T34	0	236	0	0
T40	0	39	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	40	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	85	0	0
T112	0	132	0	0
T132	0	42	0	0
T165	0	159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	42	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T40	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	2	0	0
T112	0	1	0	0
T132	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7930692	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	7848	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7933068	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	7873	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T40	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	2	0	0
T112	0	1	0	0
T132	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	43	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T40	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	2	0	0
T112	0	1	0	0
T132	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	42	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T40	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	2	0	0
T112	0	1	0	0
T132	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	42	0	0
T9	1090	1	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	2	0	0
T40	0	1	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	1	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	2	0	0
T112	0	1	0	0
T132	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	2759	0	0
T9	1090	41	0	0
T10	889	0	0	0
T11	9850	0	0	0
T21	522	0	0	0
T32	0	147	0	0
T33	0	39	0	0
T34	0	233	0	0
T40	0	37	0	0
T45	597	0	0	0
T54	3088	0	0	0
T80	0	38	0	0
T82	422	0	0	0
T83	402	0	0	0
T84	441	0	0	0
T85	424	0	0	0
T94	0	82	0	0
T112	0	130	0	0
T132	0	40	0	0
T165	0	157	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	6480	0	0
T3	12717	33	0	0
T4	4882	24	0	0
T5	13605	12	0	0
T6	17688	51	0	0
T7	0	13	0	0
T12	7140	27	0	0
T13	421	3	0	0
T14	2065	6	0	0
T15	781	0	0	0
T20	503	7	0	0
T52	79762	0	0	0
T53	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	18	0	0
T32	1043	1	0	0
T34	0	1	0	0
T35	541	0	0	0
T42	19468	0	0	0
T48	6497	0	0	0
T55	1545	0	0	0
T56	758	0	0	0
T60	494	0	0	0
T61	1379	0	0	0
T77	0	1	0	0
T94	0	1	0	0
T114	0	1	0	0
T127	524	0	0	0
T128	522	0	0	0
T140	0	1	0	0
T141	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T198	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T9,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T9,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T9,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T31
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T9,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T32
0	1	Covered	T31,T224,T125
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T32
0	1	Covered	T6,T9,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T32
1	-	Covered	T6,T9,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T31
DetectSt	168	Covered	T6,T9,T31
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T6,T9,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T31
DebounceSt->IdleSt	163	Covered	T70,T237,T163
DetectSt->IdleSt	186	Covered	T31,T224,T125
DetectSt->StableSt	191	Covered	T6,T9,T32
IdleSt->DebounceSt	148	Covered	T6,T9,T31
StableSt->IdleSt	206	Covered	T6,T9,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T31
0	1	Covered	T6,T9,T31
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T31
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T163,T143,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T31
DetectSt	-	-	-	-	1	-	-	Covered	T31,T224,T125
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T32
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T32
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	107	0	0
CntIncr_A	8886315	77146	0	0
CntNoWrap_A	8886315	8213993	0	0
DetectStDropOut_A	8886315	3	0	0
DetectedOut_A	8886315	110238	0	0
DetectedPulseOut_A	8886315	48	0	0
DisabledIdleSt_A	8886315	7935809	0	0
DisabledNoDetection_A	8886315	7938200	0	0
EnterDebounceSt_A	8886315	57	0	0
EnterDetectSt_A	8886315	51	0	0
EnterStableSt_A	8886315	48	0	0
PulseIsPulse_A	8886315	48	0	0
StayInStableSt	8886315	110167	0	0
gen_high_level_sva.HighLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	107	0	0
T6	17688	4	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	4	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T31	0	2	0	0
T32	0	4	0	0
T35	0	2	0	0
T39	0	4	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	2	0	0
T114	0	4	0	0
T131	0	2	0	0
T165	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	77146	0	0
T6	17688	142	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	146	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T31	0	69	0	0
T32	0	152	0	0
T35	0	38	0	0
T39	0	48	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	88	0	0
T114	0	46	0	0
T131	0	40	0	0
T165	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8213993	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8408	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	3	0	0
T31	590	1	0	0
T32	1043	0	0	0
T35	541	0	0	0
T42	19468	0	0	0
T48	6497	0	0	0
T55	1545	0	0	0
T56	758	0	0	0
T60	494	0	0	0
T125	0	1	0	0
T127	524	0	0	0
T128	522	0	0	0
T224	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	110238	0	0
T6	17688	80	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	315	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T32	0	286	0	0
T35	0	94	0	0
T39	0	103	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	210	0	0
T114	0	151	0	0
T131	0	248	0	0
T140	0	361	0	0
T165	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	48	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	2	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T39	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	1	0	0
T114	0	2	0	0
T131	0	1	0	0
T140	0	1	0	0
T165	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7935809	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	7848	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7938200	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	7873	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	57	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	2	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T35	0	1	0	0
T39	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	1	0	0
T114	0	2	0	0
T131	0	1	0	0
T165	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	51	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	2	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T35	0	1	0	0
T39	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	1	0	0
T114	0	2	0	0
T131	0	1	0	0
T165	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	48	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	2	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T39	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	1	0	0
T114	0	2	0	0
T131	0	1	0	0
T140	0	1	0	0
T165	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	48	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	2	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T39	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	1	0	0
T114	0	2	0	0
T131	0	1	0	0
T140	0	1	0	0
T165	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	110167	0	0
T6	17688	77	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	312	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T32	0	283	0	0
T35	0	92	0	0
T39	0	100	0	0
T52	79762	0	0	0
T53	423	0	0	0
T112	0	209	0	0
T114	0	148	0	0
T131	0	246	0	0
T140	0	359	0	0
T165	0	158	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	25	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	1	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T32	0	1	0	0
T39	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T77	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0
T166	0	2	0	0
T167	0	2	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T2,T4	VC_COV_UNR
1	Covered	T6,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T6,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T29,T30
1	0	Covered	T1,T2,T4
1	1	Covered	T6,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T6
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T32,T34,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T30,T31
1	-	Covered	T32,T34,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T29,T30
DetectSt	168	Covered	T6,T29,T30
IdleSt	163	Covered	T1,T2,T4
StableSt	191	Covered	T29,T30,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T29,T30
DebounceSt->IdleSt	163	Covered	T94,T70,T239
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T29,T30,T31
IdleSt->DebounceSt	148	Covered	T6,T29,T30
StableSt->IdleSt	206	Covered	T29,T32,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T29,T30
0	1	Covered	T6,T29,T30
0	0	Excluded	T1,T2,T4	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T29,T30
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T70,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T29,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T239
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T6
DetectSt	-	-	-	-	0	1	-	Covered	T29,T30,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T34,T37
StableSt	-	-	-	-	-	-	0	Covered	T29,T30,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8886315	87	0	0
CntIncr_A	8886315	97843	0	0
CntNoWrap_A	8886315	8214013	0	0
DetectStDropOut_A	8886315	1	0	0
DetectedOut_A	8886315	7593	0	0
DetectedPulseOut_A	8886315	40	0	0
DisabledIdleSt_A	8886315	7896676	0	0
DisabledNoDetection_A	8886315	7899050	0	0
EnterDebounceSt_A	8886315	46	0	0
EnterDetectSt_A	8886315	41	0	0
EnterStableSt_A	8886315	40	0	0
PulseIsPulse_A	8886315	40	0	0
StayInStableSt	8886315	7532	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8886315	7043	0	0
gen_low_level_sva.LowLevelEvent_A	8886315	8216536	0	0
gen_not_sticky_sva.StableStDropOut_A	8886315	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	87	0	0
T6	17688	2	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T29	0	2	0	0
T30	0	2	0	0
T31	0	2	0	0
T32	0	2	0	0
T34	0	4	0	0
T37	0	2	0	0
T52	79762	0	0	0
T53	423	0	0	0
T94	0	3	0	0
T150	0	2	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	97843	0	0
T6	17688	71	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T29	0	90	0	0
T30	0	27	0	0
T31	0	69	0	0
T32	0	76	0	0
T34	0	88	0	0
T37	0	60	0	0
T52	79762	0	0	0
T53	423	0	0	0
T94	0	24	0	0
T150	0	85	0	0
T184	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8214013	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8410	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	1	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T52	79762	0	0	0
T53	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7593	0	0
T23	7818	0	0	0
T26	16346	0	0	0
T27	2312	0	0	0
T29	11868	39	0	0
T30	505	40	0	0
T31	0	42	0	0
T32	0	117	0	0
T34	0	132	0	0
T37	0	110	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T94	0	6	0	0
T114	0	87	0	0
T146	696	0	0	0
T147	402	0	0	0
T150	0	43	0	0
T184	0	130	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	40	0	0
T23	7818	0	0	0
T26	16346	0	0	0
T27	2312	0	0	0
T29	11868	1	0	0
T30	505	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T94	0	1	0	0
T114	0	1	0	0
T146	696	0	0	0
T147	402	0	0	0
T150	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7896676	0	0
T1	1604	1203	0	0
T2	1739	1338	0	0
T3	12717	5874	0	0
T4	4882	4481	0	0
T5	13605	13178	0	0
T6	17688	8032	0	0
T12	7140	6739	0	0
T13	421	20	0	0
T14	2065	61	0	0
T15	781	380	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7899050	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8058	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	46	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T94	0	2	0	0
T150	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	41	0	0
T6	17688	1	0	0
T7	17691	0	0	0
T8	1736	0	0	0
T9	1090	0	0	0
T10	889	0	0	0
T20	503	0	0	0
T21	522	0	0	0
T22	610	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T52	79762	0	0	0
T53	423	0	0	0
T94	0	1	0	0
T150	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	40	0	0
T23	7818	0	0	0
T26	16346	0	0	0
T27	2312	0	0	0
T29	11868	1	0	0
T30	505	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T94	0	1	0	0
T114	0	1	0	0
T146	696	0	0	0
T147	402	0	0	0
T150	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	40	0	0
T23	7818	0	0	0
T26	16346	0	0	0
T27	2312	0	0	0
T29	11868	1	0	0
T30	505	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T37	0	1	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T94	0	1	0	0
T114	0	1	0	0
T146	696	0	0	0
T147	402	0	0	0
T150	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7532	0	0
T23	7818	0	0	0
T26	16346	0	0	0
T27	2312	0	0	0
T29	11868	37	0	0
T30	505	38	0	0
T31	0	40	0	0
T32	0	116	0	0
T34	0	129	0	0
T37	0	109	0	0
T41	26234	0	0	0
T47	795	0	0	0
T63	503	0	0	0
T94	0	5	0	0
T114	0	86	0	0
T146	696	0	0	0
T147	402	0	0	0
T150	0	41	0	0
T184	0	128	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	7043	0	0
T1	1604	7	0	0
T2	1739	7	0	0
T3	12717	36	0	0
T4	4882	30	0	0
T5	13605	13	0	0
T6	17688	57	0	0
T12	7140	22	0	0
T13	421	1	0	0
T14	2065	4	0	0
T15	781	0	0	0
T20	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	8216536	0	0
T1	1604	1204	0	0
T2	1739	1339	0	0
T3	12717	5899	0	0
T4	4882	4482	0	0
T5	13605	13183	0	0
T6	17688	8439	0	0
T12	7140	6740	0	0
T13	421	21	0	0
T14	2065	65	0	0
T15	781	381	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8886315	19	0	0
T32	1043	1	0	0
T34	0	1	0	0
T35	541	0	0	0
T37	0	1	0	0
T42	19468	0	0	0
T48	6497	0	0	0
T55	1545	0	0	0
T56	758	0	0	0
T60	494	0	0	0
T61	1379	0	0	0
T77	0	1	0	0
T94	0	1	0	0
T114	0	1	0	0
T127	524	0	0	0
T128	522	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T162	0	1	0	0
T201	0	1	0	0